/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
Line | Count | Source (jump to first uncovered line) |
1 | | //===-- RISCVTargetTransformInfo.cpp - RISC-V specific TTI ----------------===// |
2 | | // |
3 | | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | | // See https://llvm.org/LICENSE.txt for license information. |
5 | | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | | // |
7 | | //===----------------------------------------------------------------------===// |
8 | | |
9 | | #include "RISCVTargetTransformInfo.h" |
10 | | #include "Utils/RISCVMatInt.h" |
11 | | #include "llvm/Analysis/TargetTransformInfo.h" |
12 | | #include "llvm/CodeGen/BasicTTIImpl.h" |
13 | | #include "llvm/CodeGen/TargetLowering.h" |
14 | | using namespace llvm; |
15 | | |
16 | | #define DEBUG_TYPE "riscvtti" |
17 | | |
18 | 345 | int RISCVTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) { |
19 | 345 | assert(Ty->isIntegerTy() && |
20 | 345 | "getIntImmCost can only estimate cost of materialising integers"); |
21 | 345 | |
22 | 345 | // We have a Zero register, so 0 is always free. |
23 | 345 | if (Imm == 0) |
24 | 0 | return TTI::TCC_Free; |
25 | 345 | |
26 | 345 | // Otherwise, we check how many instructions it will take to materialise. |
27 | 345 | const DataLayout &DL = getDataLayout(); |
28 | 345 | return RISCVMatInt::getIntMatCost(Imm, DL.getTypeSizeInBits(Ty), |
29 | 345 | getST()->is64Bit()); |
30 | 345 | } |
31 | | |
32 | | int RISCVTTIImpl::getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, |
33 | 3.50k | Type *Ty) { |
34 | 3.50k | assert(Ty->isIntegerTy() && |
35 | 3.50k | "getIntImmCost can only estimate cost of materialising integers"); |
36 | 3.50k | |
37 | 3.50k | // We have a Zero register, so 0 is always free. |
38 | 3.50k | if (Imm == 0) |
39 | 439 | return TTI::TCC_Free; |
40 | 3.07k | |
41 | 3.07k | // Some instructions in RISC-V can take a 12-bit immediate. Some of these are |
42 | 3.07k | // commutative, in others the immediate comes from a specific argument index. |
43 | 3.07k | bool Takes12BitImm = false; |
44 | 3.07k | unsigned ImmArgIdx = ~0U; |
45 | 3.07k | |
46 | 3.07k | switch (Opcode) { |
47 | 3.07k | case Instruction::GetElementPtr: |
48 | 89 | // Never hoist any arguments to a GetElementPtr. CodeGenPrepare will |
49 | 89 | // split up large offsets in GEP into better parts than ConstantHoisting |
50 | 89 | // can. |
51 | 89 | return TTI::TCC_Free; |
52 | 3.07k | case Instruction::Add: |
53 | 948 | case Instruction::And: |
54 | 948 | case Instruction::Or: |
55 | 948 | case Instruction::Xor: |
56 | 948 | case Instruction::Mul: |
57 | 948 | Takes12BitImm = true; |
58 | 948 | break; |
59 | 948 | case Instruction::Sub: |
60 | 647 | case Instruction::Shl: |
61 | 647 | case Instruction::LShr: |
62 | 647 | case Instruction::AShr: |
63 | 647 | Takes12BitImm = true; |
64 | 647 | ImmArgIdx = 1; |
65 | 647 | break; |
66 | 1.38k | default: |
67 | 1.38k | break; |
68 | 2.98k | } |
69 | 2.98k | |
70 | 2.98k | if (Takes12BitImm) { |
71 | 1.59k | // Check immediate is the correct argument... |
72 | 1.59k | if (Instruction::isCommutative(Opcode) || Idx == ImmArgIdx647 ) { |
73 | 1.29k | // ... and fits into the 12-bit immediate. |
74 | 1.29k | if (Imm.getMinSignedBits() <= 64 && |
75 | 1.29k | getTLI()->isLegalAddImmediate(Imm.getSExtValue())1.28k ) { |
76 | 1.25k | return TTI::TCC_Free; |
77 | 1.25k | } |
78 | 344 | } |
79 | 344 | |
80 | 344 | // Otherwise, use the full materialisation cost. |
81 | 344 | return getIntImmCost(Imm, Ty); |
82 | 344 | } |
83 | 1.38k | |
84 | 1.38k | // By default, prevent hoisting. |
85 | 1.38k | return TTI::TCC_Free; |
86 | 1.38k | } |
87 | | |
88 | | int RISCVTTIImpl::getIntImmCost(Intrinsic::ID IID, unsigned Idx, |
89 | 776 | const APInt &Imm, Type *Ty) { |
90 | 776 | // Prevent hoisting in unknown cases. |
91 | 776 | return TTI::TCC_Free; |
92 | 776 | } |