Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
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//===-- RISCVBaseInfo.h - Top level definitions for RISCV MC ----*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains small standalone enum definitions for the RISCV target
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// useful for the compiler back-end and the MC libraries.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
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#define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
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#include "MCTargetDesc/RISCVMCTargetDesc.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/ADT/StringSwitch.h"
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#include "llvm/MC/SubtargetFeature.h"
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namespace llvm {
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// RISCVII - This namespace holds all of the target specific flags that
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// instruction info tracks. All definitions must match RISCVInstrFormats.td.
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namespace RISCVII {
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enum {
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  InstFormatPseudo = 0,
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  InstFormatR = 1,
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  InstFormatR4 = 2,
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  InstFormatI = 3,
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  InstFormatS = 4,
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  InstFormatB = 5,
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  InstFormatU = 6,
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  InstFormatJ = 7,
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  InstFormatCR = 8,
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  InstFormatCI = 9,
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  InstFormatCSS = 10,
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  InstFormatCIW = 11,
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  InstFormatCL = 12,
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  InstFormatCS = 13,
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  InstFormatCA = 14,
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  InstFormatCB = 15,
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  InstFormatCJ = 16,
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  InstFormatOther = 17,
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  InstFormatMask = 31
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};
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enum {
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  MO_None,
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  MO_CALL,
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  MO_PLT,
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  MO_LO,
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  MO_HI,
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  MO_PCREL_LO,
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  MO_PCREL_HI,
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  MO_GOT_HI,
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  MO_TPREL_LO,
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  MO_TPREL_HI,
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  MO_TPREL_ADD,
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  MO_TLS_GOT_HI,
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  MO_TLS_GD_HI,
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};
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} // namespace RISCVII
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// Describes the predecessor/successor bits used in the FENCE instruction.
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namespace RISCVFenceField {
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enum FenceField {
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  I = 8,
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  O = 4,
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  R = 2,
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  W = 1
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};
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}
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// Describes the supported floating point rounding mode encodings.
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namespace RISCVFPRndMode {
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enum RoundingMode {
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  RNE = 0,
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  RTZ = 1,
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  RDN = 2,
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  RUP = 3,
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  RMM = 4,
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  DYN = 7,
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  Invalid
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};
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inline static StringRef roundingModeToString(RoundingMode RndMode) {
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  switch (RndMode) {
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  default:
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    llvm_unreachable("Unknown floating point rounding mode");
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  case RISCVFPRndMode::RNE:
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    return "rne";
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  case RISCVFPRndMode::RTZ:
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    return "rtz";
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  case RISCVFPRndMode::RDN:
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    return "rdn";
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  case RISCVFPRndMode::RUP:
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    return "rup";
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  case RISCVFPRndMode::RMM:
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    return "rmm";
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  case RISCVFPRndMode::DYN:
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    return "dyn";
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  }
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}
Unexecuted instantiation: RISCVAsmPrinter.cpp:llvm::RISCVFPRndMode::roundingModeToString(llvm::RISCVFPRndMode::RoundingMode)
Unexecuted instantiation: RISCVExpandPseudoInsts.cpp:llvm::RISCVFPRndMode::roundingModeToString(llvm::RISCVFPRndMode::RoundingMode)
Unexecuted instantiation: RISCVFrameLowering.cpp:llvm::RISCVFPRndMode::roundingModeToString(llvm::RISCVFPRndMode::RoundingMode)
Unexecuted instantiation: RISCVInstrInfo.cpp:llvm::RISCVFPRndMode::roundingModeToString(llvm::RISCVFPRndMode::RoundingMode)
Unexecuted instantiation: RISCVISelDAGToDAG.cpp:llvm::RISCVFPRndMode::roundingModeToString(llvm::RISCVFPRndMode::RoundingMode)
Unexecuted instantiation: RISCVISelLowering.cpp:llvm::RISCVFPRndMode::roundingModeToString(llvm::RISCVFPRndMode::RoundingMode)
Unexecuted instantiation: RISCVMCInstLower.cpp:llvm::RISCVFPRndMode::roundingModeToString(llvm::RISCVFPRndMode::RoundingMode)
Unexecuted instantiation: RISCVMergeBaseOffset.cpp:llvm::RISCVFPRndMode::roundingModeToString(llvm::RISCVFPRndMode::RoundingMode)
Unexecuted instantiation: RISCVRegisterInfo.cpp:llvm::RISCVFPRndMode::roundingModeToString(llvm::RISCVFPRndMode::RoundingMode)
Unexecuted instantiation: RISCVSubtarget.cpp:llvm::RISCVFPRndMode::roundingModeToString(llvm::RISCVFPRndMode::RoundingMode)
Unexecuted instantiation: RISCVTargetMachine.cpp:llvm::RISCVFPRndMode::roundingModeToString(llvm::RISCVFPRndMode::RoundingMode)
Unexecuted instantiation: RISCVTargetObjectFile.cpp:llvm::RISCVFPRndMode::roundingModeToString(llvm::RISCVFPRndMode::RoundingMode)
Unexecuted instantiation: RISCVTargetTransformInfo.cpp:llvm::RISCVFPRndMode::roundingModeToString(llvm::RISCVFPRndMode::RoundingMode)
Unexecuted instantiation: RISCVAsmParser.cpp:llvm::RISCVFPRndMode::roundingModeToString(llvm::RISCVFPRndMode::RoundingMode)
Unexecuted instantiation: RISCVAsmBackend.cpp:llvm::RISCVFPRndMode::roundingModeToString(llvm::RISCVFPRndMode::RoundingMode)
RISCVInstPrinter.cpp:llvm::RISCVFPRndMode::roundingModeToString(llvm::RISCVFPRndMode::RoundingMode)
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inline static StringRef roundingModeToString(RoundingMode RndMode) {
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  switch (RndMode) {
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  default:
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    llvm_unreachable("Unknown floating point rounding mode");
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  case RISCVFPRndMode::RNE:
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    return "rne";
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  case RISCVFPRndMode::RTZ:
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    return "rtz";
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  case RISCVFPRndMode::RDN:
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    return "rdn";
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  case RISCVFPRndMode::RUP:
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    return "rup";
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  case RISCVFPRndMode::RMM:
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    return "rmm";
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  case RISCVFPRndMode::DYN:
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    return "dyn";
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  }
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}
Unexecuted instantiation: RISCVMCCodeEmitter.cpp:llvm::RISCVFPRndMode::roundingModeToString(llvm::RISCVFPRndMode::RoundingMode)
Unexecuted instantiation: RISCVMCExpr.cpp:llvm::RISCVFPRndMode::roundingModeToString(llvm::RISCVFPRndMode::RoundingMode)
Unexecuted instantiation: RISCVELFStreamer.cpp:llvm::RISCVFPRndMode::roundingModeToString(llvm::RISCVFPRndMode::RoundingMode)
Unexecuted instantiation: RISCVBaseInfo.cpp:llvm::RISCVFPRndMode::roundingModeToString(llvm::RISCVFPRndMode::RoundingMode)
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inline static RoundingMode stringToRoundingMode(StringRef Str) {
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  return StringSwitch<RoundingMode>(Str)
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      .Case("rne", RISCVFPRndMode::RNE)
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      .Case("rtz", RISCVFPRndMode::RTZ)
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      .Case("rdn", RISCVFPRndMode::RDN)
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      .Case("rup", RISCVFPRndMode::RUP)
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      .Case("rmm", RISCVFPRndMode::RMM)
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      .Case("dyn", RISCVFPRndMode::DYN)
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      .Default(RISCVFPRndMode::Invalid);
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}
Unexecuted instantiation: RISCVAsmPrinter.cpp:llvm::RISCVFPRndMode::stringToRoundingMode(llvm::StringRef)
Unexecuted instantiation: RISCVExpandPseudoInsts.cpp:llvm::RISCVFPRndMode::stringToRoundingMode(llvm::StringRef)
Unexecuted instantiation: RISCVFrameLowering.cpp:llvm::RISCVFPRndMode::stringToRoundingMode(llvm::StringRef)
Unexecuted instantiation: RISCVInstrInfo.cpp:llvm::RISCVFPRndMode::stringToRoundingMode(llvm::StringRef)
Unexecuted instantiation: RISCVISelDAGToDAG.cpp:llvm::RISCVFPRndMode::stringToRoundingMode(llvm::StringRef)
Unexecuted instantiation: RISCVISelLowering.cpp:llvm::RISCVFPRndMode::stringToRoundingMode(llvm::StringRef)
Unexecuted instantiation: RISCVMCInstLower.cpp:llvm::RISCVFPRndMode::stringToRoundingMode(llvm::StringRef)
Unexecuted instantiation: RISCVMergeBaseOffset.cpp:llvm::RISCVFPRndMode::stringToRoundingMode(llvm::StringRef)
Unexecuted instantiation: RISCVRegisterInfo.cpp:llvm::RISCVFPRndMode::stringToRoundingMode(llvm::StringRef)
Unexecuted instantiation: RISCVSubtarget.cpp:llvm::RISCVFPRndMode::stringToRoundingMode(llvm::StringRef)
Unexecuted instantiation: RISCVTargetMachine.cpp:llvm::RISCVFPRndMode::stringToRoundingMode(llvm::StringRef)
Unexecuted instantiation: RISCVTargetObjectFile.cpp:llvm::RISCVFPRndMode::stringToRoundingMode(llvm::StringRef)
Unexecuted instantiation: RISCVTargetTransformInfo.cpp:llvm::RISCVFPRndMode::stringToRoundingMode(llvm::StringRef)
RISCVAsmParser.cpp:llvm::RISCVFPRndMode::stringToRoundingMode(llvm::StringRef)
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inline static RoundingMode stringToRoundingMode(StringRef Str) {
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  return StringSwitch<RoundingMode>(Str)
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      .Case("rne", RISCVFPRndMode::RNE)
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      .Case("rtz", RISCVFPRndMode::RTZ)
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      .Case("rdn", RISCVFPRndMode::RDN)
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      .Case("rup", RISCVFPRndMode::RUP)
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      .Case("rmm", RISCVFPRndMode::RMM)
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      .Case("dyn", RISCVFPRndMode::DYN)
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      .Default(RISCVFPRndMode::Invalid);
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}
Unexecuted instantiation: RISCVAsmBackend.cpp:llvm::RISCVFPRndMode::stringToRoundingMode(llvm::StringRef)
Unexecuted instantiation: RISCVInstPrinter.cpp:llvm::RISCVFPRndMode::stringToRoundingMode(llvm::StringRef)
Unexecuted instantiation: RISCVMCCodeEmitter.cpp:llvm::RISCVFPRndMode::stringToRoundingMode(llvm::StringRef)
Unexecuted instantiation: RISCVMCExpr.cpp:llvm::RISCVFPRndMode::stringToRoundingMode(llvm::StringRef)
Unexecuted instantiation: RISCVELFStreamer.cpp:llvm::RISCVFPRndMode::stringToRoundingMode(llvm::StringRef)
Unexecuted instantiation: RISCVBaseInfo.cpp:llvm::RISCVFPRndMode::stringToRoundingMode(llvm::StringRef)
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inline static bool isValidRoundingMode(unsigned Mode) {
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  switch (Mode) {
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  default:
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    return false;
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  case RISCVFPRndMode::RNE:
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  case RISCVFPRndMode::RTZ:
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  case RISCVFPRndMode::RDN:
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  case RISCVFPRndMode::RUP:
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  case RISCVFPRndMode::RMM:
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  case RISCVFPRndMode::DYN:
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    return true;
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  }
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}
Unexecuted instantiation: RISCVAsmPrinter.cpp:llvm::RISCVFPRndMode::isValidRoundingMode(unsigned int)
Unexecuted instantiation: RISCVExpandPseudoInsts.cpp:llvm::RISCVFPRndMode::isValidRoundingMode(unsigned int)
Unexecuted instantiation: RISCVFrameLowering.cpp:llvm::RISCVFPRndMode::isValidRoundingMode(unsigned int)
Unexecuted instantiation: RISCVInstrInfo.cpp:llvm::RISCVFPRndMode::isValidRoundingMode(unsigned int)
Unexecuted instantiation: RISCVISelDAGToDAG.cpp:llvm::RISCVFPRndMode::isValidRoundingMode(unsigned int)
Unexecuted instantiation: RISCVISelLowering.cpp:llvm::RISCVFPRndMode::isValidRoundingMode(unsigned int)
Unexecuted instantiation: RISCVMCInstLower.cpp:llvm::RISCVFPRndMode::isValidRoundingMode(unsigned int)
Unexecuted instantiation: RISCVMergeBaseOffset.cpp:llvm::RISCVFPRndMode::isValidRoundingMode(unsigned int)
Unexecuted instantiation: RISCVRegisterInfo.cpp:llvm::RISCVFPRndMode::isValidRoundingMode(unsigned int)
Unexecuted instantiation: RISCVSubtarget.cpp:llvm::RISCVFPRndMode::isValidRoundingMode(unsigned int)
Unexecuted instantiation: RISCVTargetMachine.cpp:llvm::RISCVFPRndMode::isValidRoundingMode(unsigned int)
Unexecuted instantiation: RISCVTargetObjectFile.cpp:llvm::RISCVFPRndMode::isValidRoundingMode(unsigned int)
Unexecuted instantiation: RISCVTargetTransformInfo.cpp:llvm::RISCVFPRndMode::isValidRoundingMode(unsigned int)
Unexecuted instantiation: RISCVAsmParser.cpp:llvm::RISCVFPRndMode::isValidRoundingMode(unsigned int)
Unexecuted instantiation: RISCVAsmBackend.cpp:llvm::RISCVFPRndMode::isValidRoundingMode(unsigned int)
Unexecuted instantiation: RISCVInstPrinter.cpp:llvm::RISCVFPRndMode::isValidRoundingMode(unsigned int)
Unexecuted instantiation: RISCVMCCodeEmitter.cpp:llvm::RISCVFPRndMode::isValidRoundingMode(unsigned int)
Unexecuted instantiation: RISCVMCExpr.cpp:llvm::RISCVFPRndMode::isValidRoundingMode(unsigned int)
Unexecuted instantiation: RISCVELFStreamer.cpp:llvm::RISCVFPRndMode::isValidRoundingMode(unsigned int)
Unexecuted instantiation: RISCVBaseInfo.cpp:llvm::RISCVFPRndMode::isValidRoundingMode(unsigned int)
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} // namespace RISCVFPRndMode
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namespace RISCVSysReg {
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struct SysReg {
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  const char *Name;
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  unsigned Encoding;
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  // FIXME: add these additional fields when needed.
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  // Privilege Access: Read, Write, Read-Only.
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  // unsigned ReadWrite;
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  // Privilege Mode: User, System or Machine.
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  // unsigned Mode;
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  // Check field name.
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  // unsigned Extra;
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  // Register number without the privilege bits.
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  // unsigned Number;
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  FeatureBitset FeaturesRequired;
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  bool isRV32Only;
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2.45k
  bool haveRequiredFeatures(FeatureBitset ActiveFeatures) const {
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    // Not in 32-bit mode.
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2.45k
    if (isRV32Only && 
ActiveFeatures[RISCV::Feature64Bit]585
)
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      return false;
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2.26k
    // No required feature associated with the system register.
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    if (FeaturesRequired.none())
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      return true;
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    return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
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  }
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};
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#define GET_SysRegsList_DECL
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#include "RISCVGenSystemOperands.inc"
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} // end namespace RISCVSysReg
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namespace RISCVABI {
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enum ABI {
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  ABI_ILP32,
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  ABI_ILP32F,
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  ABI_ILP32D,
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  ABI_ILP32E,
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  ABI_LP64,
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  ABI_LP64F,
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  ABI_LP64D,
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  ABI_Unknown
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};
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// Returns the target ABI, or else a StringError if the requested ABIName is
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// not supported for the given TT and FeatureBits combination.
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ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits,
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                     StringRef ABIName);
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} // namespace RISCVABI
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namespace RISCVFeatures {
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// Validates if the given combination of features are valid for the target
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// triple. Exits with report_fatal_error if not.
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void validate(const Triple &TT, const FeatureBitset &FeatureBits);
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} // namespace RISCVFeatures
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} // namespace llvm
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#endif