Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/RISCV/Utils/RISCVMatInt.cpp
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//===- RISCVMatInt.cpp - Immediate materialisation -------------*- C++ -*--===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "RISCVMatInt.h"
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#include "MCTargetDesc/RISCVMCTargetDesc.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/Support/MachineValueType.h"
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#include "llvm/Support/MathExtras.h"
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#include <cstdint>
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namespace llvm {
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namespace RISCVMatInt {
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void generateInstSeq(int64_t Val, bool IsRV64, InstSeq &Res) {
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  if (isInt<32>(Val)) {
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    // Depending on the active bits in the immediate Value v, the following
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    // instruction sequences are emitted:
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    //
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    // v == 0                        : ADDI
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    // v[0,12) != 0 && v[12,32) == 0 : ADDI
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    // v[0,12) == 0 && v[12,32) != 0 : LUI
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    // v[0,32) != 0                  : LUI+ADDI(W)
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    int64_t Hi20 = ((Val + 0x800) >> 12) & 0xFFFFF;
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    int64_t Lo12 = SignExtend64<12>(Val);
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    if (Hi20)
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      Res.push_back(Inst(RISCV::LUI, Hi20));
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    if (Lo12 || 
Hi20 == 099
) {
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      unsigned AddiOpc = (IsRV64 && 
Hi201.05k
) ?
RISCV::ADDIW276
:
RISCV::ADDI1.07k
;
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      Res.push_back(Inst(AddiOpc, Lo12));
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    }
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    return;
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  }
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  assert(IsRV64 && "Can't emit >32-bit imm for non-RV64 target");
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  // In the worst case, for a full 64-bit constant, a sequence of 8 instructions
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  // (i.e., LUI+ADDIW+SLLI+ADDI+SLLI+ADDI+SLLI+ADDI) has to be emmitted. Note
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  // that the first two instructions (LUI+ADDIW) can contribute up to 32 bits
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  // while the following ADDI instructions contribute up to 12 bits each.
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  //
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  // On the first glance, implementing this seems to be possible by simply
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  // emitting the most significant 32 bits (LUI+ADDIW) followed by as many left
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  // shift (SLLI) and immediate additions (ADDI) as needed. However, due to the
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  // fact that ADDI performs a sign extended addition, doing it like that would
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  // only be possible when at most 11 bits of the ADDI instructions are used.
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  // Using all 12 bits of the ADDI instructions, like done by GAS, actually
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  // requires that the constant is processed starting with the least significant
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  // bit.
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  //
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  // In the following, constants are processed from LSB to MSB but instruction
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  // emission is performed from MSB to LSB by recursively calling
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  // generateInstSeq. In each recursion, first the lowest 12 bits are removed
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  // from the constant and the optimal shift amount, which can be greater than
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  // 12 bits if the constant is sparse, is determined. Then, the shifted
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  // remaining constant is processed recursively and gets emitted as soon as it
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  // fits into 32 bits. The emission of the shifts and additions is subsequently
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  // performed when the recursion returns.
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  int64_t Lo12 = SignExtend64<12>(Val);
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  int64_t Hi52 = ((uint64_t)Val + 0x800ull) >> 12;
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  int ShiftAmount = 12 + findFirstSet((uint64_t)Hi52);
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  Hi52 = SignExtend64(Hi52 >> (ShiftAmount - 12), 64 - ShiftAmount);
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  generateInstSeq(Hi52, IsRV64, Res);
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  Res.push_back(Inst(RISCV::SLLI, ShiftAmount));
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  if (Lo12)
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    Res.push_back(Inst(RISCV::ADDI, Lo12));
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}
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int getIntMatCost(const APInt &Val, unsigned Size, bool IsRV64) {
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  int PlatRegSize = IsRV64 ? 
64173
:
32180
;
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  // Split the constant into platform register sized chunks, and calculate cost
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  // of each chunk.
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  int Cost = 0;
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  for (unsigned ShiftVal = 0; ShiftVal < Size; 
ShiftVal += PlatRegSize369
) {
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    APInt Chunk = Val.ashr(ShiftVal).sextOrTrunc(PlatRegSize);
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    InstSeq MatSeq;
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    generateInstSeq(Chunk.getSExtValue(), IsRV64, MatSeq);
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    Cost += MatSeq.size();
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  }
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  return std::max(1, Cost);
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}
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} // namespace RISCVMatInt
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} // namespace llvm