Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/Sparc/SparcFrameLowering.cpp
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//===-- SparcFrameLowering.cpp - Sparc Frame Information ------------------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file contains the Sparc implementation of TargetFrameLowering class.
10
//
11
//===----------------------------------------------------------------------===//
12
13
#include "SparcFrameLowering.h"
14
#include "SparcInstrInfo.h"
15
#include "SparcMachineFunctionInfo.h"
16
#include "SparcSubtarget.h"
17
#include "llvm/CodeGen/MachineFrameInfo.h"
18
#include "llvm/CodeGen/MachineFunction.h"
19
#include "llvm/CodeGen/MachineInstrBuilder.h"
20
#include "llvm/CodeGen/MachineModuleInfo.h"
21
#include "llvm/CodeGen/MachineRegisterInfo.h"
22
#include "llvm/IR/DataLayout.h"
23
#include "llvm/IR/Function.h"
24
#include "llvm/Support/CommandLine.h"
25
#include "llvm/Target/TargetOptions.h"
26
27
using namespace llvm;
28
29
static cl::opt<bool>
30
DisableLeafProc("disable-sparc-leaf-proc",
31
                cl::init(false),
32
                cl::desc("Disable Sparc leaf procedure optimization."),
33
                cl::Hidden);
34
35
SparcFrameLowering::SparcFrameLowering(const SparcSubtarget &ST)
36
    : TargetFrameLowering(TargetFrameLowering::StackGrowsDown,
37
425
                          ST.is64Bit() ? 16 : 8, 0, ST.is64Bit() ? 16 : 8) {}
38
39
void SparcFrameLowering::emitSPAdjustment(MachineFunction &MF,
40
                                          MachineBasicBlock &MBB,
41
                                          MachineBasicBlock::iterator MBBI,
42
                                          int NumBytes,
43
                                          unsigned ADDrr,
44
566
                                          unsigned ADDri) const {
45
566
46
566
  DebugLoc dl;
47
566
  const SparcInstrInfo &TII =
48
566
      *static_cast<const SparcInstrInfo *>(MF.getSubtarget().getInstrInfo());
49
566
50
566
  if (NumBytes >= -4096 && 
NumBytes < 4096560
) {
51
560
    BuildMI(MBB, MBBI, dl, TII.get(ADDri), SP::O6)
52
560
      .addReg(SP::O6).addImm(NumBytes);
53
560
    return;
54
560
  }
55
6
56
6
  // Emit this the hard way.  This clobbers G1 which we always know is
57
6
  // available here.
58
6
  if (NumBytes >= 0) {
59
0
    // Emit nonnegative numbers with sethi + or.
60
0
    // sethi %hi(NumBytes), %g1
61
0
    // or %g1, %lo(NumBytes), %g1
62
0
    // add %sp, %g1, %sp
63
0
    BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1)
64
0
      .addImm(HI22(NumBytes));
65
0
    BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1)
66
0
      .addReg(SP::G1).addImm(LO10(NumBytes));
67
0
    BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6)
68
0
      .addReg(SP::O6).addReg(SP::G1);
69
0
    return ;
70
0
  }
71
6
72
6
  // Emit negative numbers with sethi + xor.
73
6
  // sethi %hix(NumBytes), %g1
74
6
  // xor %g1, %lox(NumBytes), %g1
75
6
  // add %sp, %g1, %sp
76
6
  BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1)
77
6
    .addImm(HIX22(NumBytes));
78
6
  BuildMI(MBB, MBBI, dl, TII.get(SP::XORri), SP::G1)
79
6
    .addReg(SP::G1).addImm(LOX10(NumBytes));
80
6
  BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6)
81
6
    .addReg(SP::O6).addReg(SP::G1);
82
6
}
83
84
void SparcFrameLowering::emitPrologue(MachineFunction &MF,
85
693
                                      MachineBasicBlock &MBB) const {
86
693
  SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
87
693
88
693
  assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
89
693
  MachineFrameInfo &MFI = MF.getFrameInfo();
90
693
  const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>();
91
693
  const SparcInstrInfo &TII =
92
693
      *static_cast<const SparcInstrInfo *>(Subtarget.getInstrInfo());
93
693
  const SparcRegisterInfo &RegInfo =
94
693
      *static_cast<const SparcRegisterInfo *>(Subtarget.getRegisterInfo());
95
693
  MachineBasicBlock::iterator MBBI = MBB.begin();
96
693
  // Debug location must be unknown since the first debug location is used
97
693
  // to determine the end of the prologue.
98
693
  DebugLoc dl;
99
693
  bool NeedsStackRealignment = RegInfo.needsStackRealignment(MF);
100
693
101
693
  // FIXME: unfortunately, returning false from canRealignStack
102
693
  // actually just causes needsStackRealignment to return false,
103
693
  // rather than reporting an error, as would be sensible. This is
104
693
  // poor, but fixing that bogosity is going to be a large project.
105
693
  // For now, just see if it's lied, and report an error here.
106
693
  if (!NeedsStackRealignment && 
MFI.getMaxAlignment() > getStackAlignment()679
)
107
2
    report_fatal_error("Function \"" + Twine(MF.getName()) + "\" required "
108
2
                       "stack re-alignment, but LLVM couldn't handle it "
109
2
                       "(probably because it has a dynamic alloca).");
110
691
111
691
  // Get the number of bytes to allocate from the FrameInfo
112
691
  int NumBytes = (int) MFI.getStackSize();
113
691
114
691
  unsigned SAVEri = SP::SAVEri;
115
691
  unsigned SAVErr = SP::SAVErr;
116
691
  if (FuncInfo->isLeafProc()) {
117
307
    if (NumBytes == 0)
118
220
      return;
119
87
    SAVEri = SP::ADDri;
120
87
    SAVErr = SP::ADDrr;
121
87
  }
122
691
123
691
  // The SPARC ABI is a bit odd in that it requires a reserved 92-byte
124
691
  // (128 in v9) area in the user's stack, starting at %sp. Thus, the
125
691
  // first part of the stack that can actually be used is located at
126
691
  // %sp + 92.
127
691
  //
128
691
  // We therefore need to add that offset to the total stack size
129
691
  // after all the stack objects are placed by
130
691
  // PrologEpilogInserter calculateFrameObjectOffsets. However, since the stack needs to be
131
691
  // aligned *after* the extra size is added, we need to disable
132
691
  // calculateFrameObjectOffsets's built-in stack alignment, by having
133
691
  // targetHandlesStackFrameRounding return true.
134
691
135
691
136
691
  // Add the extra call frame stack size, if needed. (This is the same
137
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  // code as in PrologEpilogInserter, but also gets disabled by
138
691
  // targetHandlesStackFrameRounding)
139
691
  
if (471
MFI.adjustsStack()471
&&
hasReservedCallFrame(MF)246
)
140
244
    NumBytes += MFI.getMaxCallFrameSize();
141
471
142
471
  // Adds the SPARC subtarget-specific spill area to the stack
143
471
  // size. Also ensures target-required alignment.
144
471
  NumBytes = Subtarget.getAdjustedFrameSize(NumBytes);
145
471
146
471
  // Finally, ensure that the size is sufficiently aligned for the
147
471
  // data on the stack.
148
471
  if (MFI.getMaxAlignment() > 0) {
149
386
    NumBytes = alignTo(NumBytes, MFI.getMaxAlignment());
150
386
  }
151
471
152
471
  // Update stack size with corrected value.
153
471
  MFI.setStackSize(NumBytes);
154
471
155
471
  emitSPAdjustment(MF, MBB, MBBI, -NumBytes, SAVErr, SAVEri);
156
471
157
471
  unsigned regFP = RegInfo.getDwarfRegNum(SP::I6, true);
158
471
159
471
  // Emit ".cfi_def_cfa_register 30".
160
471
  unsigned CFIIndex =
161
471
      MF.addFrameInst(MCCFIInstruction::createDefCfaRegister(nullptr, regFP));
162
471
  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
163
471
      .addCFIIndex(CFIIndex);
164
471
165
471
  // Emit ".cfi_window_save".
166
471
  CFIIndex = MF.addFrameInst(MCCFIInstruction::createWindowSave(nullptr));
167
471
  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
168
471
      .addCFIIndex(CFIIndex);
169
471
170
471
  unsigned regInRA = RegInfo.getDwarfRegNum(SP::I7, true);
171
471
  unsigned regOutRA = RegInfo.getDwarfRegNum(SP::O7, true);
172
471
  // Emit ".cfi_register 15, 31".
173
471
  CFIIndex = MF.addFrameInst(
174
471
      MCCFIInstruction::createRegister(nullptr, regOutRA, regInRA));
175
471
  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
176
471
      .addCFIIndex(CFIIndex);
177
471
178
471
  if (NeedsStackRealignment) {
179
14
    int64_t Bias = Subtarget.getStackPointerBias();
180
14
    unsigned regUnbiased;
181
14
    if (Bias) {
182
1
      // This clobbers G1 which we always know is available here.
183
1
      regUnbiased = SP::G1;
184
1
      // add %o6, BIAS, %g1
185
1
      BuildMI(MBB, MBBI, dl, TII.get(SP::ADDri), regUnbiased)
186
1
        .addReg(SP::O6).addImm(Bias);
187
1
    } else
188
13
      regUnbiased = SP::O6;
189
14
190
14
    // andn %regUnbiased, MaxAlign-1, %regUnbiased
191
14
    int MaxAlign = MFI.getMaxAlignment();
192
14
    BuildMI(MBB, MBBI, dl, TII.get(SP::ANDNri), regUnbiased)
193
14
      .addReg(regUnbiased).addImm(MaxAlign - 1);
194
14
195
14
    if (Bias) {
196
1
      // add %g1, -BIAS, %o6
197
1
      BuildMI(MBB, MBBI, dl, TII.get(SP::ADDri), SP::O6)
198
1
        .addReg(regUnbiased).addImm(-Bias);
199
1
    }
200
14
  }
201
471
}
202
203
MachineBasicBlock::iterator SparcFrameLowering::
204
eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
205
734
                              MachineBasicBlock::iterator I) const {
206
734
  if (!hasReservedCallFrame(MF)) {
207
8
    MachineInstr &MI = *I;
208
8
    int Size = MI.getOperand(0).getImm();
209
8
    if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
210
4
      Size = -Size;
211
8
212
8
    if (Size)
213
6
      emitSPAdjustment(MF, MBB, I, Size, SP::ADDrr, SP::ADDri);
214
8
  }
215
734
  return MBB.erase(I);
216
734
}
217
218
219
void SparcFrameLowering::emitEpilogue(MachineFunction &MF,
220
704
                                  MachineBasicBlock &MBB) const {
221
704
  SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
222
704
  MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
223
704
  const SparcInstrInfo &TII =
224
704
      *static_cast<const SparcInstrInfo *>(MF.getSubtarget().getInstrInfo());
225
704
  DebugLoc dl = MBBI->getDebugLoc();
226
704
  assert(MBBI->getOpcode() == SP::RETL &&
227
704
         "Can only put epilog before 'retl' instruction!");
228
704
  if (!FuncInfo->isLeafProc()) {
229
393
    BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
230
393
      .addReg(SP::G0);
231
393
    return;
232
393
  }
233
311
  MachineFrameInfo &MFI = MF.getFrameInfo();
234
311
235
311
  int NumBytes = (int) MFI.getStackSize();
236
311
  if (NumBytes == 0)
237
222
    return;
238
89
239
89
  emitSPAdjustment(MF, MBB, MBBI, NumBytes, SP::ADDrr, SP::ADDri);
240
89
}
241
242
3.89k
bool SparcFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
243
3.89k
  // Reserve call frame if there are no variable sized objects on the stack.
244
3.89k
  return !MF.getFrameInfo().hasVarSizedObjects();
245
3.89k
}
246
247
// hasFP - Return true if the specified function should have a dedicated frame
248
// pointer register.  This is true if the function has variable sized allocas or
249
// if frame pointer elimination is disabled.
250
1.04k
bool SparcFrameLowering::hasFP(const MachineFunction &MF) const {
251
1.04k
  const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
252
1.04k
253
1.04k
  const MachineFrameInfo &MFI = MF.getFrameInfo();
254
1.04k
  return MF.getTarget().Options.DisableFramePointerElim(MF) ||
255
1.04k
      
RegInfo->needsStackRealignment(MF)1.03k
||
256
1.04k
      
MFI.hasVarSizedObjects()1.00k
||
257
1.04k
      
MFI.isFrameAddressTaken()997
;
258
1.04k
}
259
260
261
int SparcFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
262
3.40k
                                               unsigned &FrameReg) const {
263
3.40k
  const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>();
264
3.40k
  const MachineFrameInfo &MFI = MF.getFrameInfo();
265
3.40k
  const SparcRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
266
3.40k
  const SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
267
3.40k
  bool isFixed = MFI.isFixedObjectIndex(FI);
268
3.40k
269
3.40k
  // Addressable stack objects are accessed using neg. offsets from
270
3.40k
  // %fp, or positive offsets from %sp.
271
3.40k
  bool UseFP;
272
3.40k
273
3.40k
  // Sparc uses FP-based references in general, even when "hasFP" is
274
3.40k
  // false. That function is rather a misnomer, because %fp is
275
3.40k
  // actually always available, unless isLeafProc.
276
3.40k
  if (FuncInfo->isLeafProc()) {
277
435
    // If there's a leaf proc, all offsets need to be %sp-based,
278
435
    // because we haven't caused %fp to actually point to our frame.
279
435
    UseFP = false;
280
2.97k
  } else if (isFixed) {
281
99
    // Otherwise, argument access should always use %fp.
282
99
    UseFP = true;
283
2.87k
  } else if (RegInfo->needsStackRealignment(MF)) {
284
2.11k
    // If there is dynamic stack realignment, all local object
285
2.11k
    // references need to be via %sp, to take account of the
286
2.11k
    // re-alignment.
287
2.11k
    UseFP = false;
288
2.11k
  } else {
289
757
    // Finally, default to using %fp.
290
757
    UseFP = true;
291
757
  }
292
3.40k
293
3.40k
  int64_t FrameOffset = MF.getFrameInfo().getObjectOffset(FI) +
294
3.40k
      Subtarget.getStackPointerBias();
295
3.40k
296
3.40k
  if (UseFP) {
297
856
    FrameReg = RegInfo->getFrameRegister(MF);
298
856
    return FrameOffset;
299
2.55k
  } else {
300
2.55k
    FrameReg = SP::O6; // %sp
301
2.55k
    return FrameOffset + MF.getFrameInfo().getStackSize();
302
2.55k
  }
303
3.40k
}
304
305
static bool LLVM_ATTRIBUTE_UNUSED verifyLeafProcRegUse(MachineRegisterInfo *MRI)
306
0
{
307
0
308
0
  for (unsigned reg = SP::I0; reg <= SP::I7; ++reg)
309
0
    if (MRI->isPhysRegUsed(reg))
310
0
      return false;
311
0
312
0
  for (unsigned reg = SP::L0; reg <= SP::L7; ++reg)
313
0
    if (MRI->isPhysRegUsed(reg))
314
0
      return false;
315
0
316
0
  return true;
317
0
}
318
319
bool SparcFrameLowering::isLeafProc(MachineFunction &MF) const
320
581
{
321
581
322
581
  MachineRegisterInfo &MRI = MF.getRegInfo();
323
581
  MachineFrameInfo    &MFI = MF.getFrameInfo();
324
581
325
581
  return !(MFI.hasCalls()                  // has calls
326
581
           || 
MRI.isPhysRegUsed(SP::L0)360
// Too many registers needed
327
581
           || 
MRI.isPhysRegUsed(SP::O6)341
// %sp is used
328
581
           || 
hasFP(MF)341
); // need %fp
329
581
}
330
331
309
void SparcFrameLowering::remapRegsForLeafProc(MachineFunction &MF) const {
332
309
  MachineRegisterInfo &MRI = MF.getRegInfo();
333
309
  // Remap %i[0-7] to %o[0-7].
334
2.78k
  for (unsigned reg = SP::I0; reg <= SP::I7; 
++reg2.47k
) {
335
2.47k
    if (!MRI.isPhysRegUsed(reg))
336
1.76k
      continue;
337
712
338
712
    unsigned mapped_reg = reg - SP::I0 + SP::O0;
339
712
340
712
    // Replace I register with O register.
341
712
    MRI.replaceRegWith(reg, mapped_reg);
342
712
343
712
    // Also replace register pair super-registers.
344
712
    if ((reg - SP::I0) % 2 == 0) {
345
442
      unsigned preg = (reg - SP::I0) / 2 + SP::I0_I1;
346
442
      unsigned mapped_preg = preg - SP::I0_I1 + SP::O0_O1;
347
442
      MRI.replaceRegWith(preg, mapped_preg);
348
442
    }
349
712
  }
350
309
351
309
  // Rewrite MBB's Live-ins.
352
309
  for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
353
741
       MBB != E; 
++MBB432
) {
354
2.16k
    for (unsigned reg = SP::I0_I1; reg <= SP::I6_I7; 
++reg1.72k
) {
355
1.72k
      if (!MBB->isLiveIn(reg))
356
1.72k
        continue;
357
0
      MBB->removeLiveIn(reg);
358
0
      MBB->addLiveIn(reg - SP::I0_I1 + SP::O0_O1);
359
0
    }
360
3.88k
    for (unsigned reg = SP::I0; reg <= SP::I7; 
++reg3.45k
) {
361
3.45k
      if (!MBB->isLiveIn(reg))
362
2.85k
        continue;
363
605
      MBB->removeLiveIn(reg);
364
605
      MBB->addLiveIn(reg - SP::I0 + SP::O0);
365
605
    }
366
432
  }
367
309
368
309
  assert(verifyLeafProcRegUse(&MRI));
369
#ifdef EXPENSIVE_CHECKS
370
  MF.verify(0, "After LeafProc Remapping");
371
#endif
372
}
373
374
void SparcFrameLowering::determineCalleeSaves(MachineFunction &MF,
375
                                              BitVector &SavedRegs,
376
698
                                              RegScavenger *RS) const {
377
698
  TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
378
698
  if (!DisableLeafProc && 
isLeafProc(MF)581
) {
379
309
    SparcMachineFunctionInfo *MFI = MF.getInfo<SparcMachineFunctionInfo>();
380
309
    MFI->setLeafProc(true);
381
309
382
309
    remapRegsForLeafProc(MF);
383
309
  }
384
698
385
698
}