Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/Sparc/SparcISelLowering.cpp
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//===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file implements the interfaces that Sparc uses to lower LLVM code into a
10
// selection DAG.
11
//
12
//===----------------------------------------------------------------------===//
13
14
#include "SparcISelLowering.h"
15
#include "MCTargetDesc/SparcMCExpr.h"
16
#include "SparcMachineFunctionInfo.h"
17
#include "SparcRegisterInfo.h"
18
#include "SparcTargetMachine.h"
19
#include "SparcTargetObjectFile.h"
20
#include "llvm/ADT/StringExtras.h"
21
#include "llvm/ADT/StringSwitch.h"
22
#include "llvm/CodeGen/CallingConvLower.h"
23
#include "llvm/CodeGen/MachineFrameInfo.h"
24
#include "llvm/CodeGen/MachineFunction.h"
25
#include "llvm/CodeGen/MachineInstrBuilder.h"
26
#include "llvm/CodeGen/MachineRegisterInfo.h"
27
#include "llvm/CodeGen/SelectionDAG.h"
28
#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
29
#include "llvm/IR/DerivedTypes.h"
30
#include "llvm/IR/Function.h"
31
#include "llvm/IR/Module.h"
32
#include "llvm/Support/ErrorHandling.h"
33
#include "llvm/Support/KnownBits.h"
34
using namespace llvm;
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36
37
//===----------------------------------------------------------------------===//
38
// Calling Convention Implementation
39
//===----------------------------------------------------------------------===//
40
41
static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT,
42
                                 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
43
                                 ISD::ArgFlagsTy &ArgFlags, CCState &State)
44
60
{
45
60
  assert (ArgFlags.isSRet());
46
60
47
60
  // Assign SRet argument.
48
60
  State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
49
60
                                         0,
50
60
                                         LocVT, LocInfo));
51
60
  return true;
52
60
}
53
54
static bool CC_Sparc_Assign_Split_64(unsigned &ValNo, MVT &ValVT,
55
                                     MVT &LocVT, CCValAssign::LocInfo &LocInfo,
56
                                     ISD::ArgFlagsTy &ArgFlags, CCState &State)
57
68
{
58
68
  static const MCPhysReg RegList[] = {
59
68
    SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
60
68
  };
61
68
  // Try to get first reg.
62
68
  if (unsigned Reg = State.AllocateReg(RegList)) {
63
62
    State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
64
62
  } else {
65
6
    // Assign whole thing in stack.
66
6
    State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
67
6
                                           State.AllocateStack(8,4),
68
6
                                           LocVT, LocInfo));
69
6
    return true;
70
6
  }
71
62
72
62
  // Try to get second reg.
73
62
  if (unsigned Reg = State.AllocateReg(RegList))
74
58
    State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
75
4
  else
76
4
    State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
77
4
                                           State.AllocateStack(4,4),
78
4
                                           LocVT, LocInfo));
79
62
  return true;
80
62
}
81
82
static bool CC_Sparc_Assign_Ret_Split_64(unsigned &ValNo, MVT &ValVT,
83
                                         MVT &LocVT, CCValAssign::LocInfo &LocInfo,
84
                                         ISD::ArgFlagsTy &ArgFlags, CCState &State)
85
8
{
86
8
  static const MCPhysReg RegList[] = {
87
8
    SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
88
8
  };
89
8
90
8
  // Try to get first reg.
91
8
  if (unsigned Reg = State.AllocateReg(RegList))
92
8
    State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
93
0
  else
94
0
    return false;
95
8
96
8
  // Try to get second reg.
97
8
  if (unsigned Reg = State.AllocateReg(RegList))
98
8
    State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
99
0
  else
100
0
    return false;
101
8
102
8
  return true;
103
8
}
104
105
// Allocate a full-sized argument for the 64-bit ABI.
106
static bool CC_Sparc64_Full(unsigned &ValNo, MVT &ValVT,
107
                            MVT &LocVT, CCValAssign::LocInfo &LocInfo,
108
950
                            ISD::ArgFlagsTy &ArgFlags, CCState &State) {
109
950
  assert((LocVT == MVT::f32 || LocVT == MVT::f128
110
950
          || LocVT.getSizeInBits() == 64) &&
111
950
         "Can't handle non-64 bits locations");
112
950
113
950
  // Stack space is allocated for all arguments starting from [%fp+BIAS+128].
114
950
  unsigned size      = (LocVT == MVT::f128) ? 
169
:
8941
;
115
950
  unsigned alignment = (LocVT == MVT::f128) ? 
169
:
8941
;
116
950
  unsigned Offset = State.AllocateStack(size, alignment);
117
950
  unsigned Reg = 0;
118
950
119
950
  if (LocVT == MVT::i64 && 
Offset < 6*8832
)
120
781
    // Promote integers to %i0-%i5.
121
781
    Reg = SP::I0 + Offset/8;
122
169
  else if (LocVT == MVT::f64 && 
Offset < 16*857
)
123
55
    // Promote doubles to %d0-%d30. (Which LLVM calls D0-D15).
124
55
    Reg = SP::D0 + Offset/8;
125
114
  else if (LocVT == MVT::f32 && 
Offset < 16*852
)
126
50
    // Promote floats to %f1, %f3, ...
127
50
    Reg = SP::F1 + Offset/4;
128
64
  else if (LocVT == MVT::f128 && 
Offset < 16*89
)
129
9
    // Promote long doubles to %q0-%q28. (Which LLVM calls Q0-Q7).
130
9
    Reg = SP::Q0 + Offset/16;
131
950
132
950
  // Promote to register when possible, otherwise use the stack slot.
133
950
  if (Reg) {
134
895
    State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
135
895
    return true;
136
895
  }
137
55
138
55
  // This argument goes on the stack in an 8-byte slot.
139
55
  // When passing floats, LocVT is smaller than 8 bytes. Adjust the offset to
140
55
  // the right-aligned float. The first 4 bytes of the stack slot are undefined.
141
55
  if (LocVT == MVT::f32)
142
2
    Offset += 4;
143
55
144
55
  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
145
55
  return true;
146
55
}
147
148
// Allocate a half-sized argument for the 64-bit ABI.
149
//
150
// This is used when passing { float, int } structs by value in registers.
151
static bool CC_Sparc64_Half(unsigned &ValNo, MVT &ValVT,
152
                            MVT &LocVT, CCValAssign::LocInfo &LocInfo,
153
63
                            ISD::ArgFlagsTy &ArgFlags, CCState &State) {
154
63
  assert(LocVT.getSizeInBits() == 32 && "Can't handle non-32 bits locations");
155
63
  unsigned Offset = State.AllocateStack(4, 4);
156
63
157
63
  if (LocVT == MVT::f32 && 
Offset < 16*824
) {
158
24
    // Promote floats to %f0-%f31.
159
24
    State.addLoc(CCValAssign::getReg(ValNo, ValVT, SP::F0 + Offset/4,
160
24
                                     LocVT, LocInfo));
161
24
    return true;
162
24
  }
163
39
164
39
  if (LocVT == MVT::i32 && Offset < 6*8) {
165
39
    // Promote integers to %i0-%i5, using half the register.
166
39
    unsigned Reg = SP::I0 + Offset/8;
167
39
    LocVT = MVT::i64;
168
39
    LocInfo = CCValAssign::AExt;
169
39
170
39
    // Set the Custom bit if this i32 goes in the high bits of a register.
171
39
    if (Offset % 8 == 0)
172
21
      State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg,
173
21
                                             LocVT, LocInfo));
174
18
    else
175
18
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
176
39
    return true;
177
39
  }
178
0
179
0
  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
180
0
  return true;
181
0
}
182
183
#include "SparcGenCallingConv.inc"
184
185
// The calling conventions in SparcCallingConv.td are described in terms of the
186
// callee's register window. This function translates registers to the
187
// corresponding caller window %o register.
188
1.50k
static unsigned toCallerWindow(unsigned Reg) {
189
1.50k
  static_assert(SP::I0 + 7 == SP::I7 && SP::O0 + 7 == SP::O7,
190
1.50k
                "Unexpected enum");
191
1.50k
  if (Reg >= SP::I0 && 
Reg <= SP::I71.42k
)
192
1.42k
    return Reg - SP::I0 + SP::O0;
193
80
  return Reg;
194
80
}
195
196
SDValue
197
SparcTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
198
                                 bool IsVarArg,
199
                                 const SmallVectorImpl<ISD::OutputArg> &Outs,
200
                                 const SmallVectorImpl<SDValue> &OutVals,
201
706
                                 const SDLoc &DL, SelectionDAG &DAG) const {
202
706
  if (Subtarget->is64Bit())
203
252
    return LowerReturn_64(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
204
454
  return LowerReturn_32(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
205
454
}
206
207
SDValue
208
SparcTargetLowering::LowerReturn_32(SDValue Chain, CallingConv::ID CallConv,
209
                                    bool IsVarArg,
210
                                    const SmallVectorImpl<ISD::OutputArg> &Outs,
211
                                    const SmallVectorImpl<SDValue> &OutVals,
212
454
                                    const SDLoc &DL, SelectionDAG &DAG) const {
213
454
  MachineFunction &MF = DAG.getMachineFunction();
214
454
215
454
  // CCValAssign - represent the assignment of the return value to locations.
216
454
  SmallVector<CCValAssign, 16> RVLocs;
217
454
218
454
  // CCState - Info about the registers and stack slot.
219
454
  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
220
454
                 *DAG.getContext());
221
454
222
454
  // Analyze return values.
223
454
  CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32);
224
454
225
454
  SDValue Flag;
226
454
  SmallVector<SDValue, 4> RetOps(1, Chain);
227
454
  // Make room for the return address offset.
228
454
  RetOps.push_back(SDValue());
229
454
230
454
  // Copy the result values into the output registers.
231
454
  for (unsigned i = 0, realRVLocIdx = 0;
232
757
       i != RVLocs.size();
233
454
       
++i, ++realRVLocIdx303
) {
234
303
    CCValAssign &VA = RVLocs[i];
235
303
    assert(VA.isRegLoc() && "Can only return in registers!");
236
303
237
303
    SDValue Arg = OutVals[realRVLocIdx];
238
303
239
303
    if (VA.needsCustom()) {
240
4
      assert(VA.getLocVT() == MVT::v2i32);
241
4
      // Legalize ret v2i32 -> ret 2 x i32 (Basically: do what would
242
4
      // happen by default if this wasn't a legal type)
243
4
244
4
      SDValue Part0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32,
245
4
                                  Arg,
246
4
                                  DAG.getConstant(0, DL, getVectorIdxTy(DAG.getDataLayout())));
247
4
      SDValue Part1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32,
248
4
                                  Arg,
249
4
                                  DAG.getConstant(1, DL, getVectorIdxTy(DAG.getDataLayout())));
250
4
251
4
      Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Part0, Flag);
252
4
      Flag = Chain.getValue(1);
253
4
      RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
254
4
      VA = RVLocs[++i]; // skip ahead to next loc
255
4
      Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Part1,
256
4
                               Flag);
257
4
    } else
258
299
      Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag);
259
303
260
303
    // Guarantee that all emitted copies are stuck together with flags.
261
303
    Flag = Chain.getValue(1);
262
303
    RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
263
303
  }
264
454
265
454
  unsigned RetAddrOffset = 8; // Call Inst + Delay Slot
266
454
  // If the function returns a struct, copy the SRetReturnReg to I0
267
454
  if (MF.getFunction().hasStructRetAttr()) {
268
30
    SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>();
269
30
    unsigned Reg = SFI->getSRetReturnReg();
270
30
    if (!Reg)
271
30
      
llvm_unreachable0
("sret virtual register not created in the entry block");
272
30
    auto PtrVT = getPointerTy(DAG.getDataLayout());
273
30
    SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, PtrVT);
274
30
    Chain = DAG.getCopyToReg(Chain, DL, SP::I0, Val, Flag);
275
30
    Flag = Chain.getValue(1);
276
30
    RetOps.push_back(DAG.getRegister(SP::I0, PtrVT));
277
30
    RetAddrOffset = 12; // CallInst + Delay Slot + Unimp
278
30
  }
279
454
280
454
  RetOps[0] = Chain;  // Update chain.
281
454
  RetOps[1] = DAG.getConstant(RetAddrOffset, DL, MVT::i32);
282
454
283
454
  // Add the flag if we have it.
284
454
  if (Flag.getNode())
285
304
    RetOps.push_back(Flag);
286
454
287
454
  return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other, RetOps);
288
454
}
289
290
// Lower return values for the 64-bit ABI.
291
// Return values are passed the exactly the same way as function arguments.
292
SDValue
293
SparcTargetLowering::LowerReturn_64(SDValue Chain, CallingConv::ID CallConv,
294
                                    bool IsVarArg,
295
                                    const SmallVectorImpl<ISD::OutputArg> &Outs,
296
                                    const SmallVectorImpl<SDValue> &OutVals,
297
252
                                    const SDLoc &DL, SelectionDAG &DAG) const {
298
252
  // CCValAssign - represent the assignment of the return value to locations.
299
252
  SmallVector<CCValAssign, 16> RVLocs;
300
252
301
252
  // CCState - Info about the registers and stack slot.
302
252
  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
303
252
                 *DAG.getContext());
304
252
305
252
  // Analyze return values.
306
252
  CCInfo.AnalyzeReturn(Outs, RetCC_Sparc64);
307
252
308
252
  SDValue Flag;
309
252
  SmallVector<SDValue, 4> RetOps(1, Chain);
310
252
311
252
  // The second operand on the return instruction is the return address offset.
312
252
  // The return address is always %i7+8 with the 64-bit ABI.
313
252
  RetOps.push_back(DAG.getConstant(8, DL, MVT::i32));
314
252
315
252
  // Copy the result values into the output registers.
316
450
  for (unsigned i = 0; i != RVLocs.size(); 
++i198
) {
317
198
    CCValAssign &VA = RVLocs[i];
318
198
    assert(VA.isRegLoc() && "Can only return in registers!");
319
198
    SDValue OutVal = OutVals[i];
320
198
321
198
    // Integer return values must be sign or zero extended by the callee.
322
198
    switch (VA.getLocInfo()) {
323
198
    
case CCValAssign::Full: break115
;
324
198
    case CCValAssign::SExt:
325
7
      OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal);
326
7
      break;
327
198
    case CCValAssign::ZExt:
328
14
      OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal);
329
14
      break;
330
198
    case CCValAssign::AExt:
331
62
      OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal);
332
62
      break;
333
198
    default:
334
0
      llvm_unreachable("Unknown loc info!");
335
198
    }
336
198
337
198
    // The custom bit on an i32 return value indicates that it should be passed
338
198
    // in the high bits of the register.
339
198
    if (VA.getValVT() == MVT::i32 && 
VA.needsCustom()83
) {
340
5
      OutVal = DAG.getNode(ISD::SHL, DL, MVT::i64, OutVal,
341
5
                           DAG.getConstant(32, DL, MVT::i32));
342
5
343
5
      // The next value may go in the low bits of the same register.
344
5
      // Handle both at once.
345
5
      if (i+1 < RVLocs.size() && 
RVLocs[i+1].getLocReg() == VA.getLocReg()4
) {
346
3
        SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, OutVals[i+1]);
347
3
        OutVal = DAG.getNode(ISD::OR, DL, MVT::i64, OutVal, NV);
348
3
        // Skip the next value, it's already done.
349
3
        ++i;
350
3
      }
351
5
    }
352
198
353
198
    Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVal, Flag);
354
198
355
198
    // Guarantee that all emitted copies are stuck together with flags.
356
198
    Flag = Chain.getValue(1);
357
198
    RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
358
198
  }
359
252
360
252
  RetOps[0] = Chain;  // Update chain.
361
252
362
252
  // Add the flag if we have it.
363
252
  if (Flag.getNode())
364
189
    RetOps.push_back(Flag);
365
252
366
252
  return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other, RetOps);
367
252
}
368
369
SDValue SparcTargetLowering::LowerFormalArguments(
370
    SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
371
    const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
372
694
    SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
373
694
  if (Subtarget->is64Bit())
374
250
    return LowerFormalArguments_64(Chain, CallConv, IsVarArg, Ins,
375
250
                                   DL, DAG, InVals);
376
444
  return LowerFormalArguments_32(Chain, CallConv, IsVarArg, Ins,
377
444
                                 DL, DAG, InVals);
378
444
}
379
380
/// LowerFormalArguments32 - V8 uses a very simple ABI, where all values are
381
/// passed in either one or two GPRs, including FP values.  TODO: we should
382
/// pass FP values in FP registers for fastcc functions.
383
SDValue SparcTargetLowering::LowerFormalArguments_32(
384
    SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
385
    const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
386
444
    SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
387
444
  MachineFunction &MF = DAG.getMachineFunction();
388
444
  MachineRegisterInfo &RegInfo = MF.getRegInfo();
389
444
  SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
390
444
391
444
  // Assign locations to all of the incoming arguments.
392
444
  SmallVector<CCValAssign, 16> ArgLocs;
393
444
  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
394
444
                 *DAG.getContext());
395
444
  CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc32);
396
444
397
444
  const unsigned StackOffset = 92;
398
444
  bool IsLittleEndian = DAG.getDataLayout().isLittleEndian();
399
444
400
444
  unsigned InIdx = 0;
401
1.31k
  for (unsigned i = 0, e = ArgLocs.size(); i != e; 
++i, ++InIdx875
) {
402
876
    CCValAssign &VA = ArgLocs[i];
403
876
404
876
    if (Ins[InIdx].Flags.isSRet()) {
405
31
      if (InIdx != 0)
406
1
        report_fatal_error("sparc only supports sret on the first parameter");
407
30
      // Get SRet from [%fp+64].
408
30
      int FrameIdx = MF.getFrameInfo().CreateFixedObject(4, 64, true);
409
30
      SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
410
30
      SDValue Arg =
411
30
          DAG.getLoad(MVT::i32, dl, Chain, FIPtr, MachinePointerInfo());
412
30
      InVals.push_back(Arg);
413
30
      continue;
414
30
    }
415
845
416
845
    if (VA.isRegLoc()) {
417
783
      if (VA.needsCustom()) {
418
37
        assert(VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2i32);
419
37
420
37
        unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
421
37
        MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi);
422
37
        SDValue HiVal = DAG.getCopyFromReg(Chain, dl, VRegHi, MVT::i32);
423
37
424
37
        assert(i+1 < e);
425
37
        CCValAssign &NextVA = ArgLocs[++i];
426
37
427
37
        SDValue LoVal;
428
37
        if (NextVA.isMemLoc()) {
429
2
          int FrameIdx = MF.getFrameInfo().
430
2
            CreateFixedObject(4, StackOffset+NextVA.getLocMemOffset(),true);
431
2
          SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
432
2
          LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, MachinePointerInfo());
433
35
        } else {
434
35
          unsigned loReg = MF.addLiveIn(NextVA.getLocReg(),
435
35
                                        &SP::IntRegsRegClass);
436
35
          LoVal = DAG.getCopyFromReg(Chain, dl, loReg, MVT::i32);
437
35
        }
438
37
439
37
        if (IsLittleEndian)
440
6
          std::swap(LoVal, HiVal);
441
37
442
37
        SDValue WholeValue =
443
37
          DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
444
37
        WholeValue = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), WholeValue);
445
37
        InVals.push_back(WholeValue);
446
37
        continue;
447
37
      }
448
746
      unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
449
746
      MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg);
450
746
      SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
451
746
      if (VA.getLocVT() == MVT::f32)
452
39
        Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Arg);
453
707
      else if (VA.getLocVT() != MVT::i32) {
454
0
        Arg = DAG.getNode(ISD::AssertSext, dl, MVT::i32, Arg,
455
0
                          DAG.getValueType(VA.getLocVT()));
456
0
        Arg = DAG.getNode(ISD::TRUNCATE, dl, VA.getLocVT(), Arg);
457
0
      }
458
746
      InVals.push_back(Arg);
459
746
      continue;
460
746
    }
461
62
462
62
    assert(VA.isMemLoc());
463
62
464
62
    unsigned Offset = VA.getLocMemOffset()+StackOffset;
465
62
    auto PtrVT = getPointerTy(DAG.getDataLayout());
466
62
467
62
    if (VA.needsCustom()) {
468
3
      assert(VA.getValVT() == MVT::f64 || VA.getValVT() == MVT::v2i32);
469
3
      // If it is double-word aligned, just load.
470
3
      if (Offset % 8 == 0) {
471
2
        int FI = MF.getFrameInfo().CreateFixedObject(8,
472
2
                                                     Offset,
473
2
                                                     true);
474
2
        SDValue FIPtr = DAG.getFrameIndex(FI, PtrVT);
475
2
        SDValue Load =
476
2
            DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr, MachinePointerInfo());
477
2
        InVals.push_back(Load);
478
2
        continue;
479
2
      }
480
1
481
1
      int FI = MF.getFrameInfo().CreateFixedObject(4,
482
1
                                                   Offset,
483
1
                                                   true);
484
1
      SDValue FIPtr = DAG.getFrameIndex(FI, PtrVT);
485
1
      SDValue HiVal =
486
1
          DAG.getLoad(MVT::i32, dl, Chain, FIPtr, MachinePointerInfo());
487
1
      int FI2 = MF.getFrameInfo().CreateFixedObject(4,
488
1
                                                    Offset+4,
489
1
                                                    true);
490
1
      SDValue FIPtr2 = DAG.getFrameIndex(FI2, PtrVT);
491
1
492
1
      SDValue LoVal =
493
1
          DAG.getLoad(MVT::i32, dl, Chain, FIPtr2, MachinePointerInfo());
494
1
495
1
      if (IsLittleEndian)
496
0
        std::swap(LoVal, HiVal);
497
1
498
1
      SDValue WholeValue =
499
1
        DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
500
1
      WholeValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), WholeValue);
501
1
      InVals.push_back(WholeValue);
502
1
      continue;
503
1
    }
504
59
505
59
    int FI = MF.getFrameInfo().CreateFixedObject(4,
506
59
                                                 Offset,
507
59
                                                 true);
508
59
    SDValue FIPtr = DAG.getFrameIndex(FI, PtrVT);
509
59
    SDValue Load ;
510
59
    if (VA.getValVT() == MVT::i32 || 
VA.getValVT() == MVT::f322
) {
511
59
      Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr, MachinePointerInfo());
512
59
    } else 
if (0
VA.getValVT() == MVT::f1280
) {
513
0
      report_fatal_error("SPARCv8 does not handle f128 in calls; "
514
0
                         "pass indirectly");
515
0
    } else {
516
0
      // We shouldn't see any other value types here.
517
0
      llvm_unreachable("Unexpected ValVT encountered in frame lowering.");
518
0
    }
519
59
    InVals.push_back(Load);
520
59
  }
521
444
522
444
  
if (443
MF.getFunction().hasStructRetAttr()443
) {
523
30
    // Copy the SRet Argument to SRetReturnReg.
524
30
    SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>();
525
30
    unsigned Reg = SFI->getSRetReturnReg();
526
30
    if (!Reg) {
527
30
      Reg = MF.getRegInfo().createVirtualRegister(&SP::IntRegsRegClass);
528
30
      SFI->setSRetReturnReg(Reg);
529
30
    }
530
30
    SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
531
30
    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
532
30
  }
533
443
534
443
  // Store remaining ArgRegs to the stack if this is a varargs function.
535
443
  if (isVarArg) {
536
0
    static const MCPhysReg ArgRegs[] = {
537
0
      SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
538
0
    };
539
0
    unsigned NumAllocated = CCInfo.getFirstUnallocated(ArgRegs);
540
0
    const MCPhysReg *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6;
541
0
    unsigned ArgOffset = CCInfo.getNextStackOffset();
542
0
    if (NumAllocated == 6)
543
0
      ArgOffset += StackOffset;
544
0
    else {
545
0
      assert(!ArgOffset);
546
0
      ArgOffset = 68+4*NumAllocated;
547
0
    }
548
0
549
0
    // Remember the vararg offset for the va_start implementation.
550
0
    FuncInfo->setVarArgsFrameOffset(ArgOffset);
551
0
552
0
    std::vector<SDValue> OutChains;
553
0
554
0
    for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
555
0
      unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
556
0
      MF.getRegInfo().addLiveIn(*CurArgReg, VReg);
557
0
      SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32);
558
0
559
0
      int FrameIdx = MF.getFrameInfo().CreateFixedObject(4, ArgOffset,
560
0
                                                         true);
561
0
      SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
562
0
563
0
      OutChains.push_back(
564
0
          DAG.getStore(DAG.getRoot(), dl, Arg, FIPtr, MachinePointerInfo()));
565
0
      ArgOffset += 4;
566
0
    }
567
0
568
0
    if (!OutChains.empty()) {
569
0
      OutChains.push_back(Chain);
570
0
      Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
571
0
    }
572
0
  }
573
443
574
443
  return Chain;
575
444
}
576
577
// Lower formal arguments for the 64 bit ABI.
578
SDValue SparcTargetLowering::LowerFormalArguments_64(
579
    SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
580
    const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
581
250
    SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
582
250
  MachineFunction &MF = DAG.getMachineFunction();
583
250
584
250
  // Analyze arguments according to CC_Sparc64.
585
250
  SmallVector<CCValAssign, 16> ArgLocs;
586
250
  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
587
250
                 *DAG.getContext());
588
250
  CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc64);
589
250
590
250
  // The argument array begins at %fp+BIAS+128, after the register save area.
591
250
  const unsigned ArgArea = 128;
592
250
593
723
  for (unsigned i = 0, e = ArgLocs.size(); i != e; 
++i473
) {
594
473
    CCValAssign &VA = ArgLocs[i];
595
473
    if (VA.isRegLoc()) {
596
447
      // This argument is passed in a register.
597
447
      // All integer register arguments are promoted by the caller to i64.
598
447
599
447
      // Create a virtual register for the promoted live-in value.
600
447
      unsigned VReg = MF.addLiveIn(VA.getLocReg(),
601
447
                                   getRegClassFor(VA.getLocVT()));
602
447
      SDValue Arg = DAG.getCopyFromReg(Chain, DL, VReg, VA.getLocVT());
603
447
604
447
      // Get the high bits for i32 struct elements.
605
447
      if (VA.getValVT() == MVT::i32 && 
VA.needsCustom()125
)
606
6
        Arg = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), Arg,
607
6
                          DAG.getConstant(32, DL, MVT::i32));
608
447
609
447
      // The caller promoted the argument, so insert an Assert?ext SDNode so we
610
447
      // won't promote the value again in this function.
611
447
      switch (VA.getLocInfo()) {
612
447
      case CCValAssign::SExt:
613
4
        Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg,
614
4
                          DAG.getValueType(VA.getValVT()));
615
4
        break;
616
447
      case CCValAssign::ZExt:
617
7
        Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg,
618
7
                          DAG.getValueType(VA.getValVT()));
619
7
        break;
620
447
      default:
621
436
        break;
622
447
      }
623
447
624
447
      // Truncate the register down to the argument type.
625
447
      if (VA.isExtInLoc())
626
125
        Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);
627
447
628
447
      InVals.push_back(Arg);
629
447
      continue;
630
447
    }
631
26
632
26
    // The registers are exhausted. This argument was passed on the stack.
633
26
    assert(VA.isMemLoc());
634
26
    // The CC_Sparc64_Full/Half functions compute stack offsets relative to the
635
26
    // beginning of the arguments area at %fp+BIAS+128.
636
26
    unsigned Offset = VA.getLocMemOffset() + ArgArea;
637
26
    unsigned ValSize = VA.getValVT().getSizeInBits() / 8;
638
26
    // Adjust offset for extended arguments, SPARC is big-endian.
639
26
    // The caller will have written the full slot with extended bytes, but we
640
26
    // prefer our own extending loads.
641
26
    if (VA.isExtInLoc())
642
14
      Offset += 8 - ValSize;
643
26
    int FI = MF.getFrameInfo().CreateFixedObject(ValSize, Offset, true);
644
26
    InVals.push_back(
645
26
        DAG.getLoad(VA.getValVT(), DL, Chain,
646
26
                    DAG.getFrameIndex(FI, getPointerTy(MF.getDataLayout())),
647
26
                    MachinePointerInfo::getFixedStack(MF, FI)));
648
26
  }
649
250
650
250
  if (!IsVarArg)
651
248
    return Chain;
652
2
653
2
  // This function takes variable arguments, some of which may have been passed
654
2
  // in registers %i0-%i5. Variable floating point arguments are never passed
655
2
  // in floating point registers. They go on %i0-%i5 or on the stack like
656
2
  // integer arguments.
657
2
  //
658
2
  // The va_start intrinsic needs to know the offset to the first variable
659
2
  // argument.
660
2
  unsigned ArgOffset = CCInfo.getNextStackOffset();
661
2
  SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
662
2
  // Skip the 128 bytes of register save area.
663
2
  FuncInfo->setVarArgsFrameOffset(ArgOffset + ArgArea +
664
2
                                  Subtarget->getStackPointerBias());
665
2
666
2
  // Save the variable arguments that were passed in registers.
667
2
  // The caller is required to reserve stack space for 6 arguments regardless
668
2
  // of how many arguments were actually passed.
669
2
  SmallVector<SDValue, 8> OutChains;
670
10
  for (; ArgOffset < 6*8; 
ArgOffset += 88
) {
671
8
    unsigned VReg = MF.addLiveIn(SP::I0 + ArgOffset/8, &SP::I64RegsRegClass);
672
8
    SDValue VArg = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
673
8
    int FI = MF.getFrameInfo().CreateFixedObject(8, ArgOffset + ArgArea, true);
674
8
    auto PtrVT = getPointerTy(MF.getDataLayout());
675
8
    OutChains.push_back(
676
8
        DAG.getStore(Chain, DL, VArg, DAG.getFrameIndex(FI, PtrVT),
677
8
                     MachinePointerInfo::getFixedStack(MF, FI)));
678
8
  }
679
2
680
2
  if (!OutChains.empty())
681
2
    Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);
682
2
683
2
  return Chain;
684
2
}
685
686
SDValue
687
SparcTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
688
359
                               SmallVectorImpl<SDValue> &InVals) const {
689
359
  if (Subtarget->is64Bit())
690
103
    return LowerCall_64(CLI, InVals);
691
256
  return LowerCall_32(CLI, InVals);
692
256
}
693
694
static bool hasReturnsTwiceAttr(SelectionDAG &DAG, SDValue Callee,
695
359
                                ImmutableCallSite CS) {
696
359
  if (CS)
697
194
    return CS.hasFnAttr(Attribute::ReturnsTwice);
698
165
699
165
  const Function *CalleeFn = nullptr;
700
165
  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
701
0
    CalleeFn = dyn_cast<Function>(G->getGlobal());
702
165
  } else if (ExternalSymbolSDNode *E =
703
165
             dyn_cast<ExternalSymbolSDNode>(Callee)) {
704
165
    const Function &Fn = DAG.getMachineFunction().getFunction();
705
165
    const Module *M = Fn.getParent();
706
165
    const char *CalleeName = E->getSymbol();
707
165
    CalleeFn = M->getFunction(CalleeName);
708
165
  }
709
165
710
165
  if (!CalleeFn)
711
161
    return false;
712
4
  return CalleeFn->hasFnAttribute(Attribute::ReturnsTwice);
713
4
}
714
715
// Lower a call for the 32-bit ABI.
716
SDValue
717
SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
718
256
                                  SmallVectorImpl<SDValue> &InVals) const {
719
256
  SelectionDAG &DAG                     = CLI.DAG;
720
256
  SDLoc &dl                             = CLI.DL;
721
256
  SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
722
256
  SmallVectorImpl<SDValue> &OutVals     = CLI.OutVals;
723
256
  SmallVectorImpl<ISD::InputArg> &Ins   = CLI.Ins;
724
256
  SDValue Chain                         = CLI.Chain;
725
256
  SDValue Callee                        = CLI.Callee;
726
256
  bool &isTailCall                      = CLI.IsTailCall;
727
256
  CallingConv::ID CallConv              = CLI.CallConv;
728
256
  bool isVarArg                         = CLI.IsVarArg;
729
256
730
256
  // Sparc target does not yet support tail call optimization.
731
256
  isTailCall = false;
732
256
733
256
  // Analyze operands of the call, assigning locations to each operand.
734
256
  SmallVector<CCValAssign, 16> ArgLocs;
735
256
  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
736
256
                 *DAG.getContext());
737
256
  CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32);
738
256
739
256
  // Get the size of the outgoing arguments stack space requirement.
740
256
  unsigned ArgsSize = CCInfo.getNextStackOffset();
741
256
742
256
  // Keep stack frames 8-byte aligned.
743
256
  ArgsSize = (ArgsSize+7) & ~7;
744
256
745
256
  MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
746
256
747
256
  // Create local copies for byval args.
748
256
  SmallVector<SDValue, 8> ByValArgs;
749
794
  for (unsigned i = 0,  e = Outs.size(); i != e; 
++i538
) {
750
538
    ISD::ArgFlagsTy Flags = Outs[i].Flags;
751
538
    if (!Flags.isByVal())
752
534
      continue;
753
4
754
4
    SDValue Arg = OutVals[i];
755
4
    unsigned Size = Flags.getByValSize();
756
4
    unsigned Align = Flags.getByValAlign();
757
4
758
4
    if (Size > 0U) {
759
1
      int FI = MFI.CreateStackObject(Size, Align, false);
760
1
      SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
761
1
      SDValue SizeNode = DAG.getConstant(Size, dl, MVT::i32);
762
1
763
1
      Chain = DAG.getMemcpy(Chain, dl, FIPtr, Arg, SizeNode, Align,
764
1
                            false,        // isVolatile,
765
1
                            (Size <= 32), // AlwaysInline if size <= 32,
766
1
                            false,        // isTailCall
767
1
                            MachinePointerInfo(), MachinePointerInfo());
768
1
      ByValArgs.push_back(FIPtr);
769
1
    }
770
3
    else {
771
3
      SDValue nullVal;
772
3
      ByValArgs.push_back(nullVal);
773
3
    }
774
4
  }
775
256
776
256
  Chain = DAG.getCALLSEQ_START(Chain, ArgsSize, 0, dl);
777
256
778
256
  SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
779
256
  SmallVector<SDValue, 8> MemOpChains;
780
256
781
256
  const unsigned StackOffset = 92;
782
256
  bool hasStructRetAttr = false;
783
256
  unsigned SRetArgSize = 0;
784
256
  // Walk the register/memloc assignments, inserting copies/loads.
785
256
  for (unsigned i = 0, realArgIdx = 0, byvalArgIdx = 0, e = ArgLocs.size();
786
794
       i != e;
787
538
       ++i, ++realArgIdx) {
788
538
    CCValAssign &VA = ArgLocs[i];
789
538
    SDValue Arg = OutVals[realArgIdx];
790
538
791
538
    ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
792
538
793
538
    // Use local copy if it is a byval arg.
794
538
    if (Flags.isByVal()) {
795
4
      Arg = ByValArgs[byvalArgIdx++];
796
4
      if (!Arg) {
797
3
        continue;
798
3
      }
799
535
    }
800
535
801
535
    // Promote the value if needed.
802
535
    switch (VA.getLocInfo()) {
803
535
    
default: 0
llvm_unreachable0
("Unknown loc info!");
804
535
    case CCValAssign::Full: break;
805
535
    case CCValAssign::SExt:
806
0
      Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
807
0
      break;
808
535
    case CCValAssign::ZExt:
809
0
      Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
810
0
      break;
811
535
    case CCValAssign::AExt:
812
0
      Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
813
0
      break;
814
535
    case CCValAssign::BCvt:
815
0
      Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
816
0
      break;
817
535
    }
818
535
819
535
    if (Flags.isSRet()) {
820
29
      assert(VA.needsCustom());
821
29
      // store SRet argument in %sp+64
822
29
      SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
823
29
      SDValue PtrOff = DAG.getIntPtrConstant(64, dl);
824
29
      PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
825
29
      MemOpChains.push_back(
826
29
          DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo()));
827
29
      hasStructRetAttr = true;
828
29
      // sret only allowed on first argument
829
29
      assert(Outs[realArgIdx].OrigArgIndex == 0);
830
29
      PointerType *Ty = cast<PointerType>(CLI.getArgs()[0].Ty);
831
29
      Type *ElementTy = Ty->getElementType();
832
29
      SRetArgSize = DAG.getDataLayout().getTypeAllocSize(ElementTy);
833
29
      continue;
834
29
    }
835
506
836
506
    if (VA.needsCustom()) {
837
28
      assert(VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2i32);
838
28
839
28
      if (VA.isMemLoc()) {
840
3
        unsigned Offset = VA.getLocMemOffset() + StackOffset;
841
3
        // if it is double-word aligned, just store.
842
3
        if (Offset % 8 == 0) {
843
2
          SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
844
2
          SDValue PtrOff = DAG.getIntPtrConstant(Offset, dl);
845
2
          PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
846
2
          MemOpChains.push_back(
847
2
              DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo()));
848
2
          continue;
849
2
        }
850
26
      }
851
26
852
26
      if (VA.getLocVT() == MVT::f64) {
853
26
        // Move from the float value from float registers into the
854
26
        // integer registers.
855
26
        if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Arg))
856
6
          Arg = bitcastConstantFPToInt(C, dl, DAG);
857
20
        else
858
20
          Arg = DAG.getNode(ISD::BITCAST, dl, MVT::v2i32, Arg);
859
26
      }
860
26
861
26
      SDValue Part0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
862
26
                                  Arg,
863
26
                                  DAG.getConstant(0, dl, getVectorIdxTy(DAG.getDataLayout())));
864
26
      SDValue Part1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
865
26
                                  Arg,
866
26
                                  DAG.getConstant(1, dl, getVectorIdxTy(DAG.getDataLayout())));
867
26
868
26
      if (VA.isRegLoc()) {
869
25
        RegsToPass.push_back(std::make_pair(VA.getLocReg(), Part0));
870
25
        assert(i+1 != e);
871
25
        CCValAssign &NextVA = ArgLocs[++i];
872
25
        if (NextVA.isRegLoc()) {
873
23
          RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Part1));
874
23
        } else {
875
2
          // Store the second part in stack.
876
2
          unsigned Offset = NextVA.getLocMemOffset() + StackOffset;
877
2
          SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
878
2
          SDValue PtrOff = DAG.getIntPtrConstant(Offset, dl);
879
2
          PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
880
2
          MemOpChains.push_back(
881
2
              DAG.getStore(Chain, dl, Part1, PtrOff, MachinePointerInfo()));
882
2
        }
883
25
      } else {
884
1
        unsigned Offset = VA.getLocMemOffset() + StackOffset;
885
1
        // Store the first part.
886
1
        SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
887
1
        SDValue PtrOff = DAG.getIntPtrConstant(Offset, dl);
888
1
        PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
889
1
        MemOpChains.push_back(
890
1
            DAG.getStore(Chain, dl, Part0, PtrOff, MachinePointerInfo()));
891
1
        // Store the second part.
892
1
        PtrOff = DAG.getIntPtrConstant(Offset + 4, dl);
893
1
        PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
894
1
        MemOpChains.push_back(
895
1
            DAG.getStore(Chain, dl, Part1, PtrOff, MachinePointerInfo()));
896
1
      }
897
26
      continue;
898
26
    }
899
478
900
478
    // Arguments that can be passed on register must be kept at
901
478
    // RegsToPass vector
902
478
    if (VA.isRegLoc()) {
903
426
      if (VA.getLocVT() != MVT::f32) {
904
413
        RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
905
413
        continue;
906
413
      }
907
13
      Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
908
13
      RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
909
13
      continue;
910
13
    }
911
52
912
52
    assert(VA.isMemLoc());
913
52
914
52
    // Create a store off the stack pointer for this argument.
915
52
    SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
916
52
    SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset() + StackOffset,
917
52
                                           dl);
918
52
    PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
919
52
    MemOpChains.push_back(
920
52
        DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo()));
921
52
  }
922
256
923
256
924
256
  // Emit all stores, make sure the occur before any copies into physregs.
925
256
  if (!MemOpChains.empty())
926
51
    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
927
256
928
256
  // Build a sequence of copy-to-reg nodes chained together with token
929
256
  // chain and flag operands which copy the outgoing args into registers.
930
256
  // The InFlag in necessary since all emitted instructions must be
931
256
  // stuck together.
932
256
  SDValue InFlag;
933
730
  for (unsigned i = 0, e = RegsToPass.size(); i != e; 
++i474
) {
934
474
    unsigned Reg = toCallerWindow(RegsToPass[i].first);
935
474
    Chain = DAG.getCopyToReg(Chain, dl, Reg, RegsToPass[i].second, InFlag);
936
474
    InFlag = Chain.getValue(1);
937
474
  }
938
256
939
256
  bool hasReturnsTwice = hasReturnsTwiceAttr(DAG, Callee, CLI.CS);
940
256
941
256
  // If the callee is a GlobalAddress node (quite common, every direct call is)
942
256
  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
943
256
  // Likewise ExternalSymbol -> TargetExternalSymbol.
944
256
  unsigned TF = isPositionIndependent() ? 
SparcMCExpr::VK_Sparc_WPLT3011
:
0245
;
945
256
  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
946
114
    Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32, 0, TF);
947
142
  else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
948
138
    Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32, TF);
949
256
950
256
  // Returns a chain & a flag for retval copy to use
951
256
  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
952
256
  SmallVector<SDValue, 8> Ops;
953
256
  Ops.push_back(Chain);
954
256
  Ops.push_back(Callee);
955
256
  if (hasStructRetAttr)
956
29
    Ops.push_back(DAG.getTargetConstant(SRetArgSize, dl, MVT::i32));
957
730
  for (unsigned i = 0, e = RegsToPass.size(); i != e; 
++i474
)
958
474
    Ops.push_back(DAG.getRegister(toCallerWindow(RegsToPass[i].first),
959
474
                                  RegsToPass[i].second.getValueType()));
960
256
961
256
  // Add a register mask operand representing the call-preserved registers.
962
256
  const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo();
963
256
  const uint32_t *Mask =
964
256
      ((hasReturnsTwice)
965
256
           ? 
TRI->getRTCallPreservedMask(CallConv)1
966
256
           : 
TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv)255
);
967
256
  assert(Mask && "Missing call preserved mask for calling convention");
968
256
  Ops.push_back(DAG.getRegisterMask(Mask));
969
256
970
256
  if (InFlag.getNode())
971
209
    Ops.push_back(InFlag);
972
256
973
256
  Chain = DAG.getNode(SPISD::CALL, dl, NodeTys, Ops);
974
256
  InFlag = Chain.getValue(1);
975
256
976
256
  Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, dl, true),
977
256
                             DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
978
256
  InFlag = Chain.getValue(1);
979
256
980
256
  // Assign locations to each value returned by this call.
981
256
  SmallVector<CCValAssign, 16> RVLocs;
982
256
  CCState RVInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
983
256
                 *DAG.getContext());
984
256
985
256
  RVInfo.AnalyzeCallResult(Ins, RetCC_Sparc32);
986
256
987
256
  // Copy all of the result registers out of their specified physreg.
988
503
  for (unsigned i = 0; i != RVLocs.size(); 
++i247
) {
989
247
    if (RVLocs[i].getLocVT() == MVT::v2i32) {
990
4
      SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2i32);
991
4
      SDValue Lo = DAG.getCopyFromReg(
992
4
          Chain, dl, toCallerWindow(RVLocs[i++].getLocReg()), MVT::i32, InFlag);
993
4
      Chain = Lo.getValue(1);
994
4
      InFlag = Lo.getValue(2);
995
4
      Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2i32, Vec, Lo,
996
4
                        DAG.getConstant(0, dl, MVT::i32));
997
4
      SDValue Hi = DAG.getCopyFromReg(
998
4
          Chain, dl, toCallerWindow(RVLocs[i].getLocReg()), MVT::i32, InFlag);
999
4
      Chain = Hi.getValue(1);
1000
4
      InFlag = Hi.getValue(2);
1001
4
      Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2i32, Vec, Hi,
1002
4
                        DAG.getConstant(1, dl, MVT::i32));
1003
4
      InVals.push_back(Vec);
1004
243
    } else {
1005
243
      Chain =
1006
243
          DAG.getCopyFromReg(Chain, dl, toCallerWindow(RVLocs[i].getLocReg()),
1007
243
                             RVLocs[i].getValVT(), InFlag)
1008
243
              .getValue(1);
1009
243
      InFlag = Chain.getValue(2);
1010
243
      InVals.push_back(Chain.getValue(0));
1011
243
    }
1012
247
  }
1013
256
1014
256
  return Chain;
1015
256
}
1016
1017
// FIXME? Maybe this could be a TableGen attribute on some registers and
1018
// this table could be generated automatically from RegInfo.
1019
unsigned SparcTargetLowering::getRegisterByName(const char* RegName, EVT VT,
1020
0
                                               SelectionDAG &DAG) const {
1021
0
  unsigned Reg = StringSwitch<unsigned>(RegName)
1022
0
    .Case("i0", SP::I0).Case("i1", SP::I1).Case("i2", SP::I2).Case("i3", SP::I3)
1023
0
    .Case("i4", SP::I4).Case("i5", SP::I5).Case("i6", SP::I6).Case("i7", SP::I7)
1024
0
    .Case("o0", SP::O0).Case("o1", SP::O1).Case("o2", SP::O2).Case("o3", SP::O3)
1025
0
    .Case("o4", SP::O4).Case("o5", SP::O5).Case("o6", SP::O6).Case("o7", SP::O7)
1026
0
    .Case("l0", SP::L0).Case("l1", SP::L1).Case("l2", SP::L2).Case("l3", SP::L3)
1027
0
    .Case("l4", SP::L4).Case("l5", SP::L5).Case("l6", SP::L6).Case("l7", SP::L7)
1028
0
    .Case("g0", SP::G0).Case("g1", SP::G1).Case("g2", SP::G2).Case("g3", SP::G3)
1029
0
    .Case("g4", SP::G4).Case("g5", SP::G5).Case("g6", SP::G6).Case("g7", SP::G7)
1030
0
    .Default(0);
1031
0
1032
0
  if (Reg)
1033
0
    return Reg;
1034
0
1035
0
  report_fatal_error("Invalid register name global variable");
1036
0
}
1037
1038
// Fixup floating point arguments in the ... part of a varargs call.
1039
//
1040
// The SPARC v9 ABI requires that floating point arguments are treated the same
1041
// as integers when calling a varargs function. This does not apply to the
1042
// fixed arguments that are part of the function's prototype.
1043
//
1044
// This function post-processes a CCValAssign array created by
1045
// AnalyzeCallOperands().
1046
static void fixupVariableFloatArgs(SmallVectorImpl<CCValAssign> &ArgLocs,
1047
11
                                   ArrayRef<ISD::OutputArg> Outs) {
1048
29
  for (unsigned i = 0, e = ArgLocs.size(); i != e; 
++i18
) {
1049
18
    const CCValAssign &VA = ArgLocs[i];
1050
18
    MVT ValTy = VA.getLocVT();
1051
18
    // FIXME: What about f32 arguments? C promotes them to f64 when calling
1052
18
    // varargs functions.
1053
18
    if (!VA.isRegLoc() || (ValTy != MVT::f64 && 
ValTy != MVT::f12814
))
1054
13
      continue;
1055
5
    // The fixed arguments to a varargs function still go in FP registers.
1056
5
    if (Outs[VA.getValNo()].IsFixed)
1057
2
      continue;
1058
3
1059
3
    // This floating point argument should be reassigned.
1060
3
    CCValAssign NewVA;
1061
3
1062
3
    // Determine the offset into the argument array.
1063
3
    unsigned firstReg = (ValTy == MVT::f64) ? 
SP::D02
:
SP::Q01
;
1064
3
    unsigned argSize  = (ValTy == MVT::f64) ? 
82
:
161
;
1065
3
    unsigned Offset = argSize * (VA.getLocReg() - firstReg);
1066
3
    assert(Offset < 16*8 && "Offset out of range, bad register enum?");
1067
3
1068
3
    if (Offset < 6*8) {
1069
3
      // This argument should go in %i0-%i5.
1070
3
      unsigned IReg = SP::I0 + Offset/8;
1071
3
      if (ValTy == MVT::f64)
1072
2
        // Full register, just bitconvert into i64.
1073
2
        NewVA = CCValAssign::getReg(VA.getValNo(), VA.getValVT(),
1074
2
                                    IReg, MVT::i64, CCValAssign::BCvt);
1075
1
      else {
1076
1
        assert(ValTy == MVT::f128 && "Unexpected type!");
1077
1
        // Full register, just bitconvert into i128 -- We will lower this into
1078
1
        // two i64s in LowerCall_64.
1079
1
        NewVA = CCValAssign::getCustomReg(VA.getValNo(), VA.getValVT(),
1080
1
                                          IReg, MVT::i128, CCValAssign::BCvt);
1081
1
      }
1082
3
    } else {
1083
0
      // This needs to go to memory, we're out of integer registers.
1084
0
      NewVA = CCValAssign::getMem(VA.getValNo(), VA.getValVT(),
1085
0
                                  Offset, VA.getLocVT(), VA.getLocInfo());
1086
0
    }
1087
3
    ArgLocs[i] = NewVA;
1088
3
  }
1089
11
}
1090
1091
// Lower a call for the 64-bit ABI.
1092
SDValue
1093
SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI,
1094
103
                                  SmallVectorImpl<SDValue> &InVals) const {
1095
103
  SelectionDAG &DAG = CLI.DAG;
1096
103
  SDLoc DL = CLI.DL;
1097
103
  SDValue Chain = CLI.Chain;
1098
103
  auto PtrVT = getPointerTy(DAG.getDataLayout());
1099
103
1100
103
  // Sparc target does not yet support tail call optimization.
1101
103
  CLI.IsTailCall = false;
1102
103
1103
103
  // Analyze operands of the call, assigning locations to each operand.
1104
103
  SmallVector<CCValAssign, 16> ArgLocs;
1105
103
  CCState CCInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), ArgLocs,
1106
103
                 *DAG.getContext());
1107
103
  CCInfo.AnalyzeCallOperands(CLI.Outs, CC_Sparc64);
1108
103
1109
103
  // Get the size of the outgoing arguments stack space requirement.
1110
103
  // The stack offset computed by CC_Sparc64 includes all arguments.
1111
103
  // Called functions expect 6 argument words to exist in the stack frame, used
1112
103
  // or not.
1113
103
  unsigned ArgsSize = std::max(6*8u, CCInfo.getNextStackOffset());
1114
103
1115
103
  // Keep stack frames 16-byte aligned.
1116
103
  ArgsSize = alignTo(ArgsSize, 16);
1117
103
1118
103
  // Varargs calls require special treatment.
1119
103
  if (CLI.IsVarArg)
1120
11
    fixupVariableFloatArgs(ArgLocs, CLI.Outs);
1121
103
1122
103
  // Adjust the stack pointer to make room for the arguments.
1123
103
  // FIXME: Use hasReservedCallFrame to avoid %sp adjustments around all calls
1124
103
  // with more than 6 arguments.
1125
103
  Chain = DAG.getCALLSEQ_START(Chain, ArgsSize, 0, DL);
1126
103
1127
103
  // Collect the set of registers to pass to the function and their values.
1128
103
  // This will be emitted as a sequence of CopyToReg nodes glued to the call
1129
103
  // instruction.
1130
103
  SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1131
103
1132
103
  // Collect chains from all the memory opeations that copy arguments to the
1133
103
  // stack. They must follow the stack pointer adjustment above and precede the
1134
103
  // call instruction itself.
1135
103
  SmallVector<SDValue, 8> MemOpChains;
1136
103
1137
346
  for (unsigned i = 0, e = ArgLocs.size(); i != e; 
++i243
) {
1138
243
    const CCValAssign &VA = ArgLocs[i];
1139
243
    SDValue Arg = CLI.OutVals[i];
1140
243
1141
243
    // Promote the value if needed.
1142
243
    switch (VA.getLocInfo()) {
1143
243
    default:
1144
0
      llvm_unreachable("Unknown location info!");
1145
243
    case CCValAssign::Full:
1146
162
      break;
1147
243
    case CCValAssign::SExt:
1148
2
      Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
1149
2
      break;
1150
243
    case CCValAssign::ZExt:
1151
14
      Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
1152
14
      break;
1153
243
    case CCValAssign::AExt:
1154
62
      Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
1155
62
      break;
1156
243
    case CCValAssign::BCvt:
1157
3
      // fixupVariableFloatArgs() may create bitcasts from f128 to i128. But
1158
3
      // SPARC does not support i128 natively. Lower it into two i64, see below.
1159
3
      if (!VA.needsCustom() || 
VA.getValVT() != MVT::f1281
1160
3
          || 
VA.getLocVT() != MVT::i1281
)
1161
2
        Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
1162
3
      break;
1163
243
    }
1164
243
1165
243
    if (VA.isRegLoc()) {
1166
214
      if (VA.needsCustom() && 
VA.getValVT() == MVT::f1287
1167
214
          && 
VA.getLocVT() == MVT::i1281
) {
1168
1
        // Store and reload into the integer register reg and reg+1.
1169
1
        unsigned Offset = 8 * (VA.getLocReg() - SP::I0);
1170
1
        unsigned StackOffset = Offset + Subtarget->getStackPointerBias() + 128;
1171
1
        SDValue StackPtr = DAG.getRegister(SP::O6, PtrVT);
1172
1
        SDValue HiPtrOff = DAG.getIntPtrConstant(StackOffset, DL);
1173
1
        HiPtrOff = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, HiPtrOff);
1174
1
        SDValue LoPtrOff = DAG.getIntPtrConstant(StackOffset + 8, DL);
1175
1
        LoPtrOff = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, LoPtrOff);
1176
1
1177
1
        // Store to %sp+BIAS+128+Offset
1178
1
        SDValue Store =
1179
1
            DAG.getStore(Chain, DL, Arg, HiPtrOff, MachinePointerInfo());
1180
1
        // Load into Reg and Reg+1
1181
1
        SDValue Hi64 =
1182
1
            DAG.getLoad(MVT::i64, DL, Store, HiPtrOff, MachinePointerInfo());
1183
1
        SDValue Lo64 =
1184
1
            DAG.getLoad(MVT::i64, DL, Store, LoPtrOff, MachinePointerInfo());
1185
1
        RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()),
1186
1
                                            Hi64));
1187
1
        RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()+1),
1188
1
                                            Lo64));
1189
1
        continue;
1190
1
      }
1191
213
1192
213
      // The custom bit on an i32 return value indicates that it should be
1193
213
      // passed in the high bits of the register.
1194
213
      if (VA.getValVT() == MVT::i32 && 
VA.needsCustom()65
) {
1195
6
        Arg = DAG.getNode(ISD::SHL, DL, MVT::i64, Arg,
1196
6
                          DAG.getConstant(32, DL, MVT::i32));
1197
6
1198
6
        // The next value may go in the low bits of the same register.
1199
6
        // Handle both at once.
1200
6
        if (i+1 < ArgLocs.size() && ArgLocs[i+1].isRegLoc() &&
1201
6
            ArgLocs[i+1].getLocReg() == VA.getLocReg()) {
1202
5
          SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64,
1203
5
                                   CLI.OutVals[i+1]);
1204
5
          Arg = DAG.getNode(ISD::OR, DL, MVT::i64, Arg, NV);
1205
5
          // Skip the next value, it's already done.
1206
5
          ++i;
1207
5
        }
1208
6
      }
1209
213
      RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()), Arg));
1210
213
      continue;
1211
213
    }
1212
29
1213
29
    assert(VA.isMemLoc());
1214
29
1215
29
    // Create a store off the stack pointer for this argument.
1216
29
    SDValue StackPtr = DAG.getRegister(SP::O6, PtrVT);
1217
29
    // The argument area starts at %fp+BIAS+128 in the callee frame,
1218
29
    // %sp+BIAS+128 in ours.
1219
29
    SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset() +
1220
29
                                           Subtarget->getStackPointerBias() +
1221
29
                                           128, DL);
1222
29
    PtrOff = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, PtrOff);
1223
29
    MemOpChains.push_back(
1224
29
        DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo()));
1225
29
  }
1226
103
1227
103
  // Emit all stores, make sure they occur before the call.
1228
103
  if (!MemOpChains.empty())
1229
7
    Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
1230
103
1231
103
  // Build a sequence of CopyToReg nodes glued together with token chain and
1232
103
  // glue operands which copy the outgoing args into registers. The InGlue is
1233
103
  // necessary since all emitted instructions must be stuck together in order
1234
103
  // to pass the live physical registers.
1235
103
  SDValue InGlue;
1236
318
  for (unsigned i = 0, e = RegsToPass.size(); i != e; 
++i215
) {
1237
215
    Chain = DAG.getCopyToReg(Chain, DL,
1238
215
                             RegsToPass[i].first, RegsToPass[i].second, InGlue);
1239
215
    InGlue = Chain.getValue(1);
1240
215
  }
1241
103
1242
103
  // If the callee is a GlobalAddress node (quite common, every direct call is)
1243
103
  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1244
103
  // Likewise ExternalSymbol -> TargetExternalSymbol.
1245
103
  SDValue Callee = CLI.Callee;
1246
103
  bool hasReturnsTwice = hasReturnsTwiceAttr(DAG, Callee, CLI.CS);
1247
103
  unsigned TF = isPositionIndependent() ? 
SparcMCExpr::VK_Sparc_WPLT3012
:
091
;
1248
103
  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1249
72
    Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, PtrVT, 0, TF);
1250
31
  else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
1251
27
    Callee = DAG.getTargetExternalSymbol(E->getSymbol(), PtrVT, TF);
1252
103
1253
103
  // Build the operands for the call instruction itself.
1254
103
  SmallVector<SDValue, 8> Ops;
1255
103
  Ops.push_back(Chain);
1256
103
  Ops.push_back(Callee);
1257
318
  for (unsigned i = 0, e = RegsToPass.size(); i != e; 
++i215
)
1258
215
    Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1259
215
                                  RegsToPass[i].second.getValueType()));
1260
103
1261
103
  // Add a register mask operand representing the call-preserved registers.
1262
103
  const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo();
1263
103
  const uint32_t *Mask =
1264
103
      ((hasReturnsTwice) ? 
TRI->getRTCallPreservedMask(CLI.CallConv)1
1265
103
                         : TRI->getCallPreservedMask(DAG.getMachineFunction(),
1266
102
                                                     CLI.CallConv));
1267
103
  assert(Mask && "Missing call preserved mask for calling convention");
1268
103
  Ops.push_back(DAG.getRegisterMask(Mask));
1269
103
1270
103
  // Make sure the CopyToReg nodes are glued to the call instruction which
1271
103
  // consumes the registers.
1272
103
  if (InGlue.getNode())
1273
86
    Ops.push_back(InGlue);
1274
103
1275
103
  // Now the call itself.
1276
103
  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1277
103
  Chain = DAG.getNode(SPISD::CALL, DL, NodeTys, Ops);
1278
103
  InGlue = Chain.getValue(1);
1279
103
1280
103
  // Revert the stack pointer immediately after the call.
1281
103
  Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, DL, true),
1282
103
                             DAG.getIntPtrConstant(0, DL, true), InGlue, DL);
1283
103
  InGlue = Chain.getValue(1);
1284
103
1285
103
  // Now extract the return values. This is more or less the same as
1286
103
  // LowerFormalArguments_64.
1287
103
1288
103
  // Assign locations to each value returned by this call.
1289
103
  SmallVector<CCValAssign, 16> RVLocs;
1290
103
  CCState RVInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), RVLocs,
1291
103
                 *DAG.getContext());
1292
103
1293
103
  // Set inreg flag manually for codegen generated library calls that
1294
103
  // return float.
1295
103
  if (CLI.Ins.size() == 1 && 
CLI.Ins[0].VT == MVT::f3263
&&
!CLI.CS3
)
1296
2
    CLI.Ins[0].Flags.setInReg();
1297
103
1298
103
  RVInfo.AnalyzeCallResult(CLI.Ins, RetCC_Sparc64);
1299
103
1300
103
  // Copy all of the result registers out of their specified physreg.
1301
194
  for (unsigned i = 0; i != RVLocs.size(); 
++i91
) {
1302
91
    CCValAssign &VA = RVLocs[i];
1303
91
    unsigned Reg = toCallerWindow(VA.getLocReg());
1304
91
1305
91
    // When returning 'inreg {i32, i32 }', two consecutive i32 arguments can
1306
91
    // reside in the same register in the high and low bits. Reuse the
1307
91
    // CopyFromReg previous node to avoid duplicate copies.
1308
91
    SDValue RV;
1309
91
    if (RegisterSDNode *SrcReg = dyn_cast<RegisterSDNode>(Chain.getOperand(1)))
1310
14
      if (SrcReg->getReg() == Reg && 
Chain->getOpcode() == ISD::CopyFromReg3
)
1311
3
        RV = Chain.getValue(0);
1312
91
1313
91
    // But usually we'll create a new CopyFromReg for a different register.
1314
91
    if (!RV.getNode()) {
1315
88
      RV = DAG.getCopyFromReg(Chain, DL, Reg, RVLocs[i].getLocVT(), InGlue);
1316
88
      Chain = RV.getValue(1);
1317
88
      InGlue = Chain.getValue(2);
1318
88
    }
1319
91
1320
91
    // Get the high bits for i32 struct elements.
1321
91
    if (VA.getValVT() == MVT::i32 && 
VA.needsCustom()37
)
1322
4
      RV = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), RV,
1323
4
                       DAG.getConstant(32, DL, MVT::i32));
1324
91
1325
91
    // The callee promoted the return value, so insert an Assert?ext SDNode so
1326
91
    // we won't promote the value again in this function.
1327
91
    switch (VA.getLocInfo()) {
1328
91
    case CCValAssign::SExt:
1329
1
      RV = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), RV,
1330
1
                       DAG.getValueType(VA.getValVT()));
1331
1
      break;
1332
91
    case CCValAssign::ZExt:
1333
7
      RV = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), RV,
1334
7
                       DAG.getValueType(VA.getValVT()));
1335
7
      break;
1336
91
    default:
1337
83
      break;
1338
91
    }
1339
91
1340
91
    // Truncate the register down to the return value type.
1341
91
    if (VA.isExtInLoc())
1342
37
      RV = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), RV);
1343
91
1344
91
    InVals.push_back(RV);
1345
91
  }
1346
103
1347
103
  return Chain;
1348
103
}
1349
1350
//===----------------------------------------------------------------------===//
1351
// TargetLowering Implementation
1352
//===----------------------------------------------------------------------===//
1353
1354
18
TargetLowering::AtomicExpansionKind SparcTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
1355
18
  if (AI->getOperation() == AtomicRMWInst::Xchg &&
1356
18
      
AI->getType()->getPrimitiveSizeInBits() == 324
)
1357
1
    return AtomicExpansionKind::None; // Uses xchg instruction
1358
17
1359
17
  return AtomicExpansionKind::CmpXChg;
1360
17
}
1361
1362
/// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC
1363
/// condition.
1364
159
static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
1365
159
  switch (CC) {
1366
159
  
default: 0
llvm_unreachable0
("Unknown integer condition code!");
1367
159
  
case ISD::SETEQ: return SPCC::ICC_E48
;
1368
159
  
case ISD::SETNE: return SPCC::ICC_NE70
;
1369
159
  
case ISD::SETLT: return SPCC::ICC_L11
;
1370
159
  
case ISD::SETGT: return SPCC::ICC_G16
;
1371
159
  
case ISD::SETLE: return SPCC::ICC_LE0
;
1372
159
  
case ISD::SETGE: return SPCC::ICC_GE0
;
1373
159
  
case ISD::SETULT: return SPCC::ICC_CS7
;
1374
159
  
case ISD::SETULE: return SPCC::ICC_LEU1
;
1375
159
  
case ISD::SETUGT: return SPCC::ICC_GU6
;
1376
159
  
case ISD::SETUGE: return SPCC::ICC_CC0
;
1377
159
  }
1378
159
}
1379
1380
/// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC
1381
/// FCC condition.
1382
40
static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
1383
40
  switch (CC) {
1384
40
  
default: 0
llvm_unreachable0
("Unknown fp condition code!");
1385
40
  case ISD::SETEQ:
1386
0
  case ISD::SETOEQ: return SPCC::FCC_E;
1387
9
  case ISD::SETNE:
1388
9
  case ISD::SETUNE: return SPCC::FCC_NE;
1389
19
  case ISD::SETLT:
1390
19
  case ISD::SETOLT: return SPCC::FCC_L;
1391
19
  case ISD::SETGT:
1392
3
  case ISD::SETOGT: return SPCC::FCC_G;
1393
3
  case ISD::SETLE:
1394
0
  case ISD::SETOLE: return SPCC::FCC_LE;
1395
0
  case ISD::SETGE:
1396
0
  case ISD::SETOGE: return SPCC::FCC_GE;
1397
5
  case ISD::SETULT: return SPCC::FCC_UL;
1398
4
  case ISD::SETULE: return SPCC::FCC_ULE;
1399
0
  case ISD::SETUGT: return SPCC::FCC_UG;
1400
0
  case ISD::SETUGE: return SPCC::FCC_UGE;
1401
0
  case ISD::SETUO:  return SPCC::FCC_U;
1402
0
  case ISD::SETO:   return SPCC::FCC_O;
1403
0
  case ISD::SETONE: return SPCC::FCC_LG;
1404
0
  case ISD::SETUEQ: return SPCC::FCC_UE;
1405
40
  }
1406
40
}
1407
1408
SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
1409
                                         const SparcSubtarget &STI)
1410
425
    : TargetLowering(TM), Subtarget(&STI) {
1411
425
  MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize(0));
1412
425
1413
425
  // Instructions which use registers as conditionals examine all the
1414
425
  // bits (as does the pseudo SELECT_CC expansion). I don't think it
1415
425
  // matters much whether it's ZeroOrOneBooleanContent, or
1416
425
  // ZeroOrNegativeOneBooleanContent, so, arbitrarily choose the
1417
425
  // former.
1418
425
  setBooleanContents(ZeroOrOneBooleanContent);
1419
425
  setBooleanVectorContents(ZeroOrOneBooleanContent);
1420
425
1421
425
  // Set up the register classes.
1422
425
  addRegisterClass(MVT::i32, &SP::IntRegsRegClass);
1423
425
  if (!Subtarget->useSoftFloat()) {
1424
418
    addRegisterClass(MVT::f32, &SP::FPRegsRegClass);
1425
418
    addRegisterClass(MVT::f64, &SP::DFPRegsRegClass);
1426
418
    addRegisterClass(MVT::f128, &SP::QFPRegsRegClass);
1427
418
  }
1428
425
  if (Subtarget->is64Bit()) {
1429
131
    addRegisterClass(MVT::i64, &SP::I64RegsRegClass);
1430
294
  } else {
1431
294
    // On 32bit sparc, we define a double-register 32bit register
1432
294
    // class, as well. This is modeled in LLVM as a 2-vector of i32.
1433
294
    addRegisterClass(MVT::v2i32, &SP::IntPairRegClass);
1434
294
1435
294
    // ...but almost all operations must be expanded, so set that as
1436
294
    // the default.
1437
84.3k
    for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; 
++Op84.0k
) {
1438
84.0k
      setOperationAction(Op, MVT::v2i32, Expand);
1439
84.0k
    }
1440
294
    // Truncating/extending stores/loads are also not supported.
1441
22.9k
    for (MVT VT : MVT::integer_vector_valuetypes()) {
1442
22.9k
      setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Expand);
1443
22.9k
      setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i32, Expand);
1444
22.9k
      setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Expand);
1445
22.9k
1446
22.9k
      setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, VT, Expand);
1447
22.9k
      setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i32, VT, Expand);
1448
22.9k
      setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, VT, Expand);
1449
22.9k
1450
22.9k
      setTruncStoreAction(VT, MVT::v2i32, Expand);
1451
22.9k
      setTruncStoreAction(MVT::v2i32, VT, Expand);
1452
22.9k
    }
1453
294
    // However, load and store *are* legal.
1454
294
    setOperationAction(ISD::LOAD, MVT::v2i32, Legal);
1455
294
    setOperationAction(ISD::STORE, MVT::v2i32, Legal);
1456
294
    setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i32, Legal);
1457
294
    setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Legal);
1458
294
1459
294
    // And we need to promote i64 loads/stores into vector load/store
1460
294
    setOperationAction(ISD::LOAD, MVT::i64, Custom);
1461
294
    setOperationAction(ISD::STORE, MVT::i64, Custom);
1462
294
1463
294
    // Sadly, this doesn't work:
1464
294
    //    AddPromotedToType(ISD::LOAD, MVT::i64, MVT::v2i32);
1465
294
    //    AddPromotedToType(ISD::STORE, MVT::i64, MVT::v2i32);
1466
294
  }
1467
425
1468
425
  // Turn FP extload into load/fpextend
1469
2.55k
  for (MVT VT : MVT::fp_valuetypes()) {
1470
2.55k
    setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
1471
2.55k
    setLoadExtAction(ISD::EXTLOAD, VT, MVT::f64, Expand);
1472
2.55k
  }
1473
425
1474
425
  // Sparc doesn't have i1 sign extending load
1475
425
  for (MVT VT : MVT::integer_valuetypes())
1476
2.55k
    setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
1477
425
1478
425
  // Turn FP truncstore into trunc + store.
1479
425
  setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1480
425
  setTruncStoreAction(MVT::f128, MVT::f32, Expand);
1481
425
  setTruncStoreAction(MVT::f128, MVT::f64, Expand);
1482
425
1483
425
  // Custom legalize GlobalAddress nodes into LO/HI parts.
1484
425
  setOperationAction(ISD::GlobalAddress, PtrVT, Custom);
1485
425
  setOperationAction(ISD::GlobalTLSAddress, PtrVT, Custom);
1486
425
  setOperationAction(ISD::ConstantPool, PtrVT, Custom);
1487
425
  setOperationAction(ISD::BlockAddress, PtrVT, Custom);
1488
425
1489
425
  // Sparc doesn't have sext_inreg, replace them with shl/sra
1490
425
  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
1491
425
  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
1492
425
  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
1493
425
1494
425
  // Sparc has no REM or DIVREM operations.
1495
425
  setOperationAction(ISD::UREM, MVT::i32, Expand);
1496
425
  setOperationAction(ISD::SREM, MVT::i32, Expand);
1497
425
  setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
1498
425
  setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
1499
425
1500
425
  // ... nor does SparcV9.
1501
425
  if (Subtarget->is64Bit()) {
1502
131
    setOperationAction(ISD::UREM, MVT::i64, Expand);
1503
131
    setOperationAction(ISD::SREM, MVT::i64, Expand);
1504
131
    setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
1505
131
    setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
1506
131
  }
1507
425
1508
425
  // Custom expand fp<->sint
1509
425
  setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
1510
425
  setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
1511
425
  setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
1512
425
  setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
1513
425
1514
425
  // Custom Expand fp<->uint
1515
425
  setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
1516
425
  setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
1517
425
  setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
1518
425
  setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
1519
425
1520
425
  setOperationAction(ISD::BITCAST, MVT::f32, Expand);
1521
425
  setOperationAction(ISD::BITCAST, MVT::i32, Expand);
1522
425
1523
425
  // Sparc has no select or setcc: expand to SELECT_CC.
1524
425
  setOperationAction(ISD::SELECT, MVT::i32, Expand);
1525
425
  setOperationAction(ISD::SELECT, MVT::f32, Expand);
1526
425
  setOperationAction(ISD::SELECT, MVT::f64, Expand);
1527
425
  setOperationAction(ISD::SELECT, MVT::f128, Expand);
1528
425
1529
425
  setOperationAction(ISD::SETCC, MVT::i32, Expand);
1530
425
  setOperationAction(ISD::SETCC, MVT::f32, Expand);
1531
425
  setOperationAction(ISD::SETCC, MVT::f64, Expand);
1532
425
  setOperationAction(ISD::SETCC, MVT::f128, Expand);
1533
425
1534
425
  // Sparc doesn't have BRCOND either, it has BR_CC.
1535
425
  setOperationAction(ISD::BRCOND, MVT::Other, Expand);
1536
425
  setOperationAction(ISD::BRIND, MVT::Other, Expand);
1537
425
  setOperationAction(ISD::BR_JT, MVT::Other, Expand);
1538
425
  setOperationAction(ISD::BR_CC, MVT::i32, Custom);
1539
425
  setOperationAction(ISD::BR_CC, MVT::f32, Custom);
1540
425
  setOperationAction(ISD::BR_CC, MVT::f64, Custom);
1541
425
  setOperationAction(ISD::BR_CC, MVT::f128, Custom);
1542
425
1543
425
  setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
1544
425
  setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
1545
425
  setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
1546
425
  setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
1547
425
1548
425
  setOperationAction(ISD::ADDC, MVT::i32, Custom);
1549
425
  setOperationAction(ISD::ADDE, MVT::i32, Custom);
1550
425
  setOperationAction(ISD::SUBC, MVT::i32, Custom);
1551
425
  setOperationAction(ISD::SUBE, MVT::i32, Custom);
1552
425
1553
425
  if (Subtarget->is64Bit()) {
1554
131
    setOperationAction(ISD::ADDC, MVT::i64, Custom);
1555
131
    setOperationAction(ISD::ADDE, MVT::i64, Custom);
1556
131
    setOperationAction(ISD::SUBC, MVT::i64, Custom);
1557
131
    setOperationAction(ISD::SUBE, MVT::i64, Custom);
1558
131
    setOperationAction(ISD::BITCAST, MVT::f64, Expand);
1559
131
    setOperationAction(ISD::BITCAST, MVT::i64, Expand);
1560
131
    setOperationAction(ISD::SELECT, MVT::i64, Expand);
1561
131
    setOperationAction(ISD::SETCC, MVT::i64, Expand);
1562
131
    setOperationAction(ISD::BR_CC, MVT::i64, Custom);
1563
131
    setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
1564
131
1565
131
    setOperationAction(ISD::CTPOP, MVT::i64,
1566
131
                       Subtarget->usePopc() ? 
Legal6
:
Expand125
);
1567
131
    setOperationAction(ISD::CTTZ , MVT::i64, Expand);
1568
131
    setOperationAction(ISD::CTLZ , MVT::i64, Expand);
1569
131
    setOperationAction(ISD::BSWAP, MVT::i64, Expand);
1570
131
    setOperationAction(ISD::ROTL , MVT::i64, Expand);
1571
131
    setOperationAction(ISD::ROTR , MVT::i64, Expand);
1572
131
    setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom);
1573
131
  }
1574
425
1575
425
  // ATOMICs.
1576
425
  // Atomics are supported on SparcV9. 32-bit atomics are also
1577
425
  // supported by some Leon SparcV8 variants. Otherwise, atomics
1578
425
  // are unsupported.
1579
425
  if (Subtarget->isV9())
1580
155
    setMaxAtomicSizeInBitsSupported(64);
1581
270
  else if (Subtarget->hasLeonCasa())
1582
44
    setMaxAtomicSizeInBitsSupported(32);
1583
226
  else
1584
226
    setMaxAtomicSizeInBitsSupported(0);
1585
425
1586
425
  setMinCmpXchgSizeInBits(32);
1587
425
1588
425
  setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Legal);
1589
425
1590
425
  setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Legal);
1591
425
1592
425
  // Custom Lower Atomic LOAD/STORE
1593
425
  setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
1594
425
  setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
1595
425
1596
425
  if (Subtarget->is64Bit()) {
1597
131
    setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Legal);
1598
131
    setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Legal);
1599
131
    setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
1600
131
    setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Custom);
1601
131
  }
1602
425
1603
425
  if (!Subtarget->is64Bit()) {
1604
294
    // These libcalls are not available in 32-bit.
1605
294
    setLibcallName(RTLIB::SHL_I128, nullptr);
1606
294
    setLibcallName(RTLIB::SRL_I128, nullptr);
1607
294
    setLibcallName(RTLIB::SRA_I128, nullptr);
1608
294
  }
1609
425
1610
425
  if (!Subtarget->isV9()) {
1611
270
    // SparcV8 does not have FNEGD and FABSD.
1612
270
    setOperationAction(ISD::FNEG, MVT::f64, Custom);
1613
270
    setOperationAction(ISD::FABS, MVT::f64, Custom);
1614
270
  }
1615
425
1616
425
  setOperationAction(ISD::FSIN , MVT::f128, Expand);
1617
425
  setOperationAction(ISD::FCOS , MVT::f128, Expand);
1618
425
  setOperationAction(ISD::FSINCOS, MVT::f128, Expand);
1619
425
  setOperationAction(ISD::FREM , MVT::f128, Expand);
1620
425
  setOperationAction(ISD::FMA  , MVT::f128, Expand);
1621
425
  setOperationAction(ISD::FSIN , MVT::f64, Expand);
1622
425
  setOperationAction(ISD::FCOS , MVT::f64, Expand);
1623
425
  setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
1624
425
  setOperationAction(ISD::FREM , MVT::f64, Expand);
1625
425
  setOperationAction(ISD::FMA  , MVT::f64, Expand);
1626
425
  setOperationAction(ISD::FSIN , MVT::f32, Expand);
1627
425
  setOperationAction(ISD::FCOS , MVT::f32, Expand);
1628
425
  setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
1629
425
  setOperationAction(ISD::FREM , MVT::f32, Expand);
1630
425
  setOperationAction(ISD::FMA  , MVT::f32, Expand);
1631
425
  setOperationAction(ISD::CTTZ , MVT::i32, Expand);
1632
425
  setOperationAction(ISD::CTLZ , MVT::i32, Expand);
1633
425
  setOperationAction(ISD::ROTL , MVT::i32, Expand);
1634
425
  setOperationAction(ISD::ROTR , MVT::i32, Expand);
1635
425
  setOperationAction(ISD::BSWAP, MVT::i32, Expand);
1636
425
  setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
1637
425
  setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
1638
425
  setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
1639
425
  setOperationAction(ISD::FPOW , MVT::f128, Expand);
1640
425
  setOperationAction(ISD::FPOW , MVT::f64, Expand);
1641
425
  setOperationAction(ISD::FPOW , MVT::f32, Expand);
1642
425
1643
425
  setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
1644
425
  setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
1645
425
  setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
1646
425
1647
425
  // Expands to [SU]MUL_LOHI.
1648
425
  setOperationAction(ISD::MULHU,     MVT::i32, Expand);
1649
425
  setOperationAction(ISD::MULHS,     MVT::i32, Expand);
1650
425
  setOperationAction(ISD::MUL,       MVT::i32, Expand);
1651
425
1652
425
  if (Subtarget->useSoftMulDiv()) {
1653
2
    // .umul works for both signed and unsigned
1654
2
    setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
1655
2
    setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
1656
2
    setLibcallName(RTLIB::MUL_I32, ".umul");
1657
2
1658
2
    setOperationAction(ISD::SDIV, MVT::i32, Expand);
1659
2
    setLibcallName(RTLIB::SDIV_I32, ".div");
1660
2
1661
2
    setOperationAction(ISD::UDIV, MVT::i32, Expand);
1662
2
    setLibcallName(RTLIB::UDIV_I32, ".udiv");
1663
2
1664
2
    setLibcallName(RTLIB::SREM_I32, ".rem");
1665
2
    setLibcallName(RTLIB::UREM_I32, ".urem");
1666
2
  }
1667
425
1668
425
  if (Subtarget->is64Bit()) {
1669
131
    setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
1670
131
    setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
1671
131
    setOperationAction(ISD::MULHU,     MVT::i64, Expand);
1672
131
    setOperationAction(ISD::MULHS,     MVT::i64, Expand);
1673
131
1674
131
    setOperationAction(ISD::UMULO,     MVT::i64, Custom);
1675
131
    setOperationAction(ISD::SMULO,     MVT::i64, Custom);
1676
131
1677
131
    setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
1678
131
    setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
1679
131
    setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
1680
131
  }
1681
425
1682
425
  // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
1683
425
  setOperationAction(ISD::VASTART           , MVT::Other, Custom);
1684
425
  // VAARG needs to be lowered to not do unaligned accesses for doubles.
1685
425
  setOperationAction(ISD::VAARG             , MVT::Other, Custom);
1686
425
1687
425
  setOperationAction(ISD::TRAP              , MVT::Other, Legal);
1688
425
  setOperationAction(ISD::DEBUGTRAP         , MVT::Other, Legal);
1689
425
1690
425
  // Use the default implementation.
1691
425
  setOperationAction(ISD::VACOPY            , MVT::Other, Expand);
1692
425
  setOperationAction(ISD::VAEND             , MVT::Other, Expand);
1693
425
  setOperationAction(ISD::STACKSAVE         , MVT::Other, Expand);
1694
425
  setOperationAction(ISD::STACKRESTORE      , MVT::Other, Expand);
1695
425
  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32  , Custom);
1696
425
1697
425
  setStackPointerRegisterToSaveRestore(SP::O6);
1698
425
1699
425
  setOperationAction(ISD::CTPOP, MVT::i32,
1700
425
                     Subtarget->usePopc() ? 
Legal14
:
Expand411
);
1701
425
1702
425
  if (Subtarget->isV9() && 
Subtarget->hasHardQuad()155
) {
1703
0
    setOperationAction(ISD::LOAD, MVT::f128, Legal);
1704
0
    setOperationAction(ISD::STORE, MVT::f128, Legal);
1705
425
  } else {
1706
425
    setOperationAction(ISD::LOAD, MVT::f128, Custom);
1707
425
    setOperationAction(ISD::STORE, MVT::f128, Custom);
1708
425
  }
1709
425
1710
425
  if (Subtarget->hasHardQuad()) {
1711
4
    setOperationAction(ISD::FADD,  MVT::f128, Legal);
1712
4
    setOperationAction(ISD::FSUB,  MVT::f128, Legal);
1713
4
    setOperationAction(ISD::FMUL,  MVT::f128, Legal);
1714
4
    setOperationAction(ISD::FDIV,  MVT::f128, Legal);
1715
4
    setOperationAction(ISD::FSQRT, MVT::f128, Legal);
1716
4
    setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal);
1717
4
    setOperationAction(ISD::FP_ROUND,  MVT::f64, Legal);
1718
4
    if (Subtarget->isV9()) {
1719
0
      setOperationAction(ISD::FNEG, MVT::f128, Legal);
1720
0
      setOperationAction(ISD::FABS, MVT::f128, Legal);
1721
4
    } else {
1722
4
      setOperationAction(ISD::FNEG, MVT::f128, Custom);
1723
4
      setOperationAction(ISD::FABS, MVT::f128, Custom);
1724
4
    }
1725
4
1726
4
    if (!Subtarget->is64Bit()) {
1727
4
      setLibcallName(RTLIB::FPTOSINT_F128_I64, "_Q_qtoll");
1728
4
      setLibcallName(RTLIB::FPTOUINT_F128_I64, "_Q_qtoull");
1729
4
      setLibcallName(RTLIB::SINTTOFP_I64_F128, "_Q_lltoq");
1730
4
      setLibcallName(RTLIB::UINTTOFP_I64_F128, "_Q_ulltoq");
1731
4
    }
1732
4
1733
421
  } else {
1734
421
    // Custom legalize f128 operations.
1735
421
1736
421
    setOperationAction(ISD::FADD,  MVT::f128, Custom);
1737
421
    setOperationAction(ISD::FSUB,  MVT::f128, Custom);
1738
421
    setOperationAction(ISD::FMUL,  MVT::f128, Custom);
1739
421
    setOperationAction(ISD::FDIV,  MVT::f128, Custom);
1740
421
    setOperationAction(ISD::FSQRT, MVT::f128, Custom);
1741
421
    setOperationAction(ISD::FNEG,  MVT::f128, Custom);
1742
421
    setOperationAction(ISD::FABS,  MVT::f128, Custom);
1743
421
1744
421
    setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
1745
421
    setOperationAction(ISD::FP_ROUND,  MVT::f64, Custom);
1746
421
    setOperationAction(ISD::FP_ROUND,  MVT::f32, Custom);
1747
421
1748
421
    // Setup Runtime library names.
1749
421
    if (Subtarget->is64Bit() && 
!Subtarget->useSoftFloat()131
) {
1750
129
      setLibcallName(RTLIB::ADD_F128,  "_Qp_add");
1751
129
      setLibcallName(RTLIB::SUB_F128,  "_Qp_sub");
1752
129
      setLibcallName(RTLIB::MUL_F128,  "_Qp_mul");
1753
129
      setLibcallName(RTLIB::DIV_F128,  "_Qp_div");
1754
129
      setLibcallName(RTLIB::SQRT_F128, "_Qp_sqrt");
1755
129
      setLibcallName(RTLIB::FPTOSINT_F128_I32, "_Qp_qtoi");
1756
129
      setLibcallName(RTLIB::FPTOUINT_F128_I32, "_Qp_qtoui");
1757
129
      setLibcallName(RTLIB::SINTTOFP_I32_F128, "_Qp_itoq");
1758
129
      setLibcallName(RTLIB::UINTTOFP_I32_F128, "_Qp_uitoq");
1759
129
      setLibcallName(RTLIB::FPTOSINT_F128_I64, "_Qp_qtox");
1760
129
      setLibcallName(RTLIB::FPTOUINT_F128_I64, "_Qp_qtoux");
1761
129
      setLibcallName(RTLIB::SINTTOFP_I64_F128, "_Qp_xtoq");
1762
129
      setLibcallName(RTLIB::UINTTOFP_I64_F128, "_Qp_uxtoq");
1763
129
      setLibcallName(RTLIB::FPEXT_F32_F128, "_Qp_stoq");
1764
129
      setLibcallName(RTLIB::FPEXT_F64_F128, "_Qp_dtoq");
1765
129
      setLibcallName(RTLIB::FPROUND_F128_F32, "_Qp_qtos");
1766
129
      setLibcallName(RTLIB::FPROUND_F128_F64, "_Qp_qtod");
1767
292
    } else if (!Subtarget->useSoftFloat()) {
1768
285
      setLibcallName(RTLIB::ADD_F128,  "_Q_add");
1769
285
      setLibcallName(RTLIB::SUB_F128,  "_Q_sub");
1770
285
      setLibcallName(RTLIB::MUL_F128,  "_Q_mul");
1771
285
      setLibcallName(RTLIB::DIV_F128,  "_Q_div");
1772
285
      setLibcallName(RTLIB::SQRT_F128, "_Q_sqrt");
1773
285
      setLibcallName(RTLIB::FPTOSINT_F128_I32, "_Q_qtoi");
1774
285
      setLibcallName(RTLIB::FPTOUINT_F128_I32, "_Q_qtou");
1775
285
      setLibcallName(RTLIB::SINTTOFP_I32_F128, "_Q_itoq");
1776
285
      setLibcallName(RTLIB::UINTTOFP_I32_F128, "_Q_utoq");
1777
285
      setLibcallName(RTLIB::FPTOSINT_F128_I64, "_Q_qtoll");
1778
285
      setLibcallName(RTLIB::FPTOUINT_F128_I64, "_Q_qtoull");
1779
285
      setLibcallName(RTLIB::SINTTOFP_I64_F128, "_Q_lltoq");
1780
285
      setLibcallName(RTLIB::UINTTOFP_I64_F128, "_Q_ulltoq");
1781
285
      setLibcallName(RTLIB::FPEXT_F32_F128, "_Q_stoq");
1782
285
      setLibcallName(RTLIB::FPEXT_F64_F128, "_Q_dtoq");
1783
285
      setLibcallName(RTLIB::FPROUND_F128_F32, "_Q_qtos");
1784
285
      setLibcallName(RTLIB::FPROUND_F128_F64, "_Q_qtod");
1785
285
    }
1786
421
  }
1787
425
1788
425
  if (Subtarget->fixAllFDIVSQRT()) {
1789
6
    // Promote FDIVS and FSQRTS to FDIVD and FSQRTD instructions instead as
1790
6
    // the former instructions generate errata on LEON processors.
1791
6
    setOperationAction(ISD::FDIV, MVT::f32, Promote);
1792
6
    setOperationAction(ISD::FSQRT, MVT::f32, Promote);
1793
6
  }
1794
425
1795
425
  if (Subtarget->hasNoFMULS()) {
1796
8
    setOperationAction(ISD::FMUL, MVT::f32, Promote);
1797
8
  }
1798
425
1799
425
  // Custom combine bitcast between f64 and v2i32
1800
425
  if (!Subtarget->is64Bit())
1801
294
    setTargetDAGCombine(ISD::BITCAST);
1802
425
1803
425
  if (Subtarget->hasLeonCycleCounter())
1804
4
    setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
1805
425
1806
425
  setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1807
425
1808
425
  setMinFunctionAlignment(2);
1809
425
1810
425
  computeRegisterProperties(Subtarget->getRegisterInfo());
1811
425
}
1812
1813
89
bool SparcTargetLowering::useSoftFloat() const {
1814
89
  return Subtarget->useSoftFloat();
1815
89
}
1816
1817
0
const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
1818
0
  switch ((SPISD::NodeType)Opcode) {
1819
0
  case SPISD::FIRST_NUMBER:    break;
1820
0
  case SPISD::CMPICC:          return "SPISD::CMPICC";
1821
0
  case SPISD::CMPFCC:          return "SPISD::CMPFCC";
1822
0
  case SPISD::BRICC:           return "SPISD::BRICC";
1823
0
  case SPISD::BRXCC:           return "SPISD::BRXCC";
1824
0
  case SPISD::BRFCC:           return "SPISD::BRFCC";
1825
0
  case SPISD::SELECT_ICC:      return "SPISD::SELECT_ICC";
1826
0
  case SPISD::SELECT_XCC:      return "SPISD::SELECT_XCC";
1827
0
  case SPISD::SELECT_FCC:      return "SPISD::SELECT_FCC";
1828
0
  case SPISD::Hi:              return "SPISD::Hi";
1829
0
  case SPISD::Lo:              return "SPISD::Lo";
1830
0
  case SPISD::FTOI:            return "SPISD::FTOI";
1831
0
  case SPISD::ITOF:            return "SPISD::ITOF";
1832
0
  case SPISD::FTOX:            return "SPISD::FTOX";
1833
0
  case SPISD::XTOF:            return "SPISD::XTOF";
1834
0
  case SPISD::CALL:            return "SPISD::CALL";
1835
0
  case SPISD::RET_FLAG:        return "SPISD::RET_FLAG";
1836
0
  case SPISD::GLOBAL_BASE_REG: return "SPISD::GLOBAL_BASE_REG";
1837
0
  case SPISD::FLUSHW:          return "SPISD::FLUSHW";
1838
0
  case SPISD::TLS_ADD:         return "SPISD::TLS_ADD";
1839
0
  case SPISD::TLS_LD:          return "SPISD::TLS_LD";
1840
0
  case SPISD::TLS_CALL:        return "SPISD::TLS_CALL";
1841
0
  }
1842
0
  return nullptr;
1843
0
}
1844
1845
EVT SparcTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &,
1846
514
                                            EVT VT) const {
1847
514
  if (!VT.isVector())
1848
514
    return MVT::i32;
1849
0
  return VT.changeVectorElementTypeToInteger();
1850
0
}
1851
1852
/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
1853
/// be zero. Op is expected to be a target specific node. Used by DAG
1854
/// combiner.
1855
void SparcTargetLowering::computeKnownBitsForTargetNode
1856
                                (const SDValue Op,
1857
                                 KnownBits &Known,
1858
                                 const APInt &DemandedElts,
1859
                                 const SelectionDAG &DAG,
1860
3.16k
                                 unsigned Depth) const {
1861
3.16k
  KnownBits Known2;
1862
3.16k
  Known.resetAll();
1863
3.16k
1864
3.16k
  switch (Op.getOpcode()) {
1865
3.16k
  
default: break2.92k
;
1866
3.16k
  case SPISD::SELECT_ICC:
1867
240
  case SPISD::SELECT_XCC:
1868
240
  case SPISD::SELECT_FCC:
1869
240
    Known = DAG.computeKnownBits(Op.getOperand(1), Depth + 1);
1870
240
    Known2 = DAG.computeKnownBits(Op.getOperand(0), Depth + 1);
1871
240
1872
240
    // Only known if known in both the LHS and RHS.
1873
240
    Known.One &= Known2.One;
1874
240
    Known.Zero &= Known2.Zero;
1875
240
    break;
1876
3.16k
  }
1877
3.16k
}
1878
1879
// Look at LHS/RHS/CC and see if they are a lowered setcc instruction.  If so
1880
// set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
1881
static void LookThroughSetCC(SDValue &LHS, SDValue &RHS,
1882
199
                             ISD::CondCode CC, unsigned &SPCC) {
1883
199
  if (isNullConstant(RHS) &&
1884
199
      
CC == ISD::SETNE69
&&
1885
199
      
(44
(44
(44
LHS.getOpcode() == SPISD::SELECT_ICC44
||
1886
44
         LHS.getOpcode() == SPISD::SELECT_XCC) &&
1887
44
        
LHS.getOperand(3).getOpcode() == SPISD::CMPICC0
) ||
1888
44
       (LHS.getOpcode() == SPISD::SELECT_FCC &&
1889
44
        
LHS.getOperand(3).getOpcode() == SPISD::CMPFCC0
)) &&
1890
199
      
isOneConstant(LHS.getOperand(0))0
&&
1891
199
      
isNullConstant(LHS.getOperand(1))0
) {
1892
0
    SDValue CMPCC = LHS.getOperand(3);
1893
0
    SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getZExtValue();
1894
0
    LHS = CMPCC.getOperand(0);
1895
0
    RHS = CMPCC.getOperand(1);
1896
0
  }
1897
199
}
1898
1899
// Convert to a target node and set target flags.
1900
SDValue SparcTargetLowering::withTargetFlags(SDValue Op, unsigned TF,
1901
466
                                             SelectionDAG &DAG) const {
1902
466
  if (const GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op))
1903
260
    return DAG.getTargetGlobalAddress(GA->getGlobal(),
1904
260
                                      SDLoc(GA),
1905
260
                                      GA->getValueType(0),
1906
260
                                      GA->getOffset(), TF);
1907
206
1908
206
  if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op))
1909
176
    return DAG.getTargetConstantPool(CP->getConstVal(),
1910
176
                                     CP->getValueType(0),
1911
176
                                     CP->getAlignment(),
1912
176
                                     CP->getOffset(), TF);
1913
30
1914
30
  if (const BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op))
1915
30
    return DAG.getTargetBlockAddress(BA->getBlockAddress(),
1916
30
                                     Op.getValueType(),
1917
30
                                     0,
1918
30
                                     TF);
1919
0
1920
0
  if (const ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op))
1921
0
    return DAG.getTargetExternalSymbol(ES->getSymbol(),
1922
0
                                       ES->getValueType(0), TF);
1923
0
1924
0
  llvm_unreachable("Unhandled address SDNode");
1925
0
}
1926
1927
// Split Op into high and low parts according to HiTF and LoTF.
1928
// Return an ADD node combining the parts.
1929
SDValue SparcTargetLowering::makeHiLoPair(SDValue Op,
1930
                                          unsigned HiTF, unsigned LoTF,
1931
190
                                          SelectionDAG &DAG) const {
1932
190
  SDLoc DL(Op);
1933
190
  EVT VT = Op.getValueType();
1934
190
  SDValue Hi = DAG.getNode(SPISD::Hi, DL, VT, withTargetFlags(Op, HiTF, DAG));
1935
190
  SDValue Lo = DAG.getNode(SPISD::Lo, DL, VT, withTargetFlags(Op, LoTF, DAG));
1936
190
  return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo);
1937
190
}
1938
1939
// Build SDNodes for producing an address from a GlobalAddress, ConstantPool,
1940
// or ExternalSymbol SDNode.
1941
172
SDValue SparcTargetLowering::makeAddress(SDValue Op, SelectionDAG &DAG) const {
1942
172
  SDLoc DL(Op);
1943
172
  EVT VT = getPointerTy(DAG.getDataLayout());
1944
172
1945
172
  // Handle PIC mode first. SPARC needs a got load for every variable!
1946
172
  if (isPositionIndependent()) {
1947
33
    const Module *M = DAG.getMachineFunction().getFunction().getParent();
1948
33
    PICLevel::Level picLevel = M->getPICLevel();
1949
33
    SDValue Idx;
1950
33
1951
33
    if (picLevel == PICLevel::SmallPIC) {
1952
1
      // This is the pic13 code model, the GOT is known to be smaller than 8KiB.
1953
1
      Idx = DAG.getNode(SPISD::Lo, DL, Op.getValueType(),
1954
1
                        withTargetFlags(Op, SparcMCExpr::VK_Sparc_GOT13, DAG));
1955
32
    } else {
1956
32
      // This is the pic32 code model, the GOT is known to be smaller than 4GB.
1957
32
      Idx = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_GOT22,
1958
32
                         SparcMCExpr::VK_Sparc_GOT10, DAG);
1959
32
    }
1960
33
1961
33
    SDValue GlobalBase = DAG.getNode(SPISD::GLOBAL_BASE_REG, DL, VT);
1962
33
    SDValue AbsAddr = DAG.getNode(ISD::ADD, DL, VT, GlobalBase, Idx);
1963
33
    // GLOBAL_BASE_REG codegen'ed with call. Inform MFI that this
1964
33
    // function has calls.
1965
33
    MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
1966
33
    MFI.setHasCalls(true);
1967
33
    return DAG.getLoad(VT, DL, DAG.getEntryNode(), AbsAddr,
1968
33
                       MachinePointerInfo::getGOT(DAG.getMachineFunction()));
1969
33
  }
1970
139
1971
139
  // This is one of the absolute code models.
1972
139
  switch(getTargetMachine().getCodeModel()) {
1973
139
  default:
1974
0
    llvm_unreachable("Unsupported absolute code model");
1975
139
  case CodeModel::Small:
1976
91
    // abs32.
1977
91
    return makeHiLoPair(Op, SparcMCExpr::VK_Sparc_HI,
1978
91
                        SparcMCExpr::VK_Sparc_LO, DAG);
1979
139
  case CodeModel::Medium: {
1980
41
    // abs44.
1981
41
    SDValue H44 = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_H44,
1982
41
                               SparcMCExpr::VK_Sparc_M44, DAG);
1983
41
    H44 = DAG.getNode(ISD::SHL, DL, VT, H44, DAG.getConstant(12, DL, MVT::i32));
1984
41
    SDValue L44 = withTargetFlags(Op, SparcMCExpr::VK_Sparc_L44, DAG);
1985
41
    L44 = DAG.getNode(SPISD::Lo, DL, VT, L44);
1986
41
    return DAG.getNode(ISD::ADD, DL, VT, H44, L44);
1987
139
  }
1988
139
  case CodeModel::Large: {
1989
7
    // abs64.
1990
7
    SDValue Hi = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_HH,
1991
7
                              SparcMCExpr::VK_Sparc_HM, DAG);
1992
7
    Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, DAG.getConstant(32, DL, MVT::i32));
1993
7
    SDValue Lo = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_HI,
1994
7
                              SparcMCExpr::VK_Sparc_LO, DAG);
1995
7
    return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo);
1996
139
  }
1997
139
  }
1998
139
}
1999
2000
SDValue SparcTargetLowering::LowerGlobalAddress(SDValue Op,
2001
84
                                                SelectionDAG &DAG) const {
2002
84
  return makeAddress(Op, DAG);
2003
84
}
2004
2005
SDValue SparcTargetLowering::LowerConstantPool(SDValue Op,
2006
76
                                               SelectionDAG &DAG) const {
2007
76
  return makeAddress(Op, DAG);
2008
76
}
2009
2010
SDValue SparcTargetLowering::LowerBlockAddress(SDValue Op,
2011
12
                                               SelectionDAG &DAG) const {
2012
12
  return makeAddress(Op, DAG);
2013
12
}
2014
2015
SDValue SparcTargetLowering::LowerGlobalTLSAddress(SDValue Op,
2016
16
                                                   SelectionDAG &DAG) const {
2017
16
2018
16
  GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2019
16
  if (DAG.getTarget().useEmulatedTLS())
2020
0
    return LowerToTLSEmulatedModel(GA, DAG);
2021
16
2022
16
  SDLoc DL(GA);
2023
16
  const GlobalValue *GV = GA->getGlobal();
2024
16
  EVT PtrVT = getPointerTy(DAG.getDataLayout());
2025
16
2026
16
  TLSModel::Model model = getTargetMachine().getTLSModel(GV);
2027
16
2028
16
  if (model == TLSModel::GeneralDynamic || 
model == TLSModel::LocalDynamic12
) {
2029
8
    unsigned HiTF = ((model == TLSModel::GeneralDynamic)
2030
8
                     ? 
SparcMCExpr::VK_Sparc_TLS_GD_HI224
2031
8
                     : 
SparcMCExpr::VK_Sparc_TLS_LDM_HI224
);
2032
8
    unsigned LoTF = ((model == TLSModel::GeneralDynamic)
2033
8
                     ? 
SparcMCExpr::VK_Sparc_TLS_GD_LO104
2034
8
                     : 
SparcMCExpr::VK_Sparc_TLS_LDM_LO104
);
2035
8
    unsigned addTF = ((model == TLSModel::GeneralDynamic)
2036
8
                      ? 
SparcMCExpr::VK_Sparc_TLS_GD_ADD4
2037
8
                      : 
SparcMCExpr::VK_Sparc_TLS_LDM_ADD4
);
2038
8
    unsigned callTF = ((model == TLSModel::GeneralDynamic)
2039
8
                       ? 
SparcMCExpr::VK_Sparc_TLS_GD_CALL4
2040
8
                       : 
SparcMCExpr::VK_Sparc_TLS_LDM_CALL4
);
2041
8
2042
8
    SDValue HiLo = makeHiLoPair(Op, HiTF, LoTF, DAG);
2043
8
    SDValue Base = DAG.getNode(SPISD::GLOBAL_BASE_REG, DL, PtrVT);
2044
8
    SDValue Argument = DAG.getNode(SPISD::TLS_ADD, DL, PtrVT, Base, HiLo,
2045
8
                               withTargetFlags(Op, addTF, DAG));
2046
8
2047
8
    SDValue Chain = DAG.getEntryNode();
2048
8
    SDValue InFlag;
2049
8
2050
8
    Chain = DAG.getCALLSEQ_START(Chain, 1, 0, DL);
2051
8
    Chain = DAG.getCopyToReg(Chain, DL, SP::O0, Argument, InFlag);
2052
8
    InFlag = Chain.getValue(1);
2053
8
    SDValue Callee = DAG.getTargetExternalSymbol("__tls_get_addr", PtrVT);
2054
8
    SDValue Symbol = withTargetFlags(Op, callTF, DAG);
2055
8
2056
8
    SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2057
8
    const uint32_t *Mask = Subtarget->getRegisterInfo()->getCallPreservedMask(
2058
8
        DAG.getMachineFunction(), CallingConv::C);
2059
8
    assert(Mask && "Missing call preserved mask for calling convention");
2060
8
    SDValue Ops[] = {Chain,
2061
8
                     Callee,
2062
8
                     Symbol,
2063
8
                     DAG.getRegister(SP::O0, PtrVT),
2064
8
                     DAG.getRegisterMask(Mask),
2065
8
                     InFlag};
2066
8
    Chain = DAG.getNode(SPISD::TLS_CALL, DL, NodeTys, Ops);
2067
8
    InFlag = Chain.getValue(1);
2068
8
    Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(1, DL, true),
2069
8
                               DAG.getIntPtrConstant(0, DL, true), InFlag, DL);
2070
8
    InFlag = Chain.getValue(1);
2071
8
    SDValue Ret = DAG.getCopyFromReg(Chain, DL, SP::O0, PtrVT, InFlag);
2072
8
2073
8
    if (model != TLSModel::LocalDynamic)
2074
4
      return Ret;
2075
4
2076
4
    SDValue Hi = DAG.getNode(SPISD::Hi, DL, PtrVT,
2077
4
                 withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LDO_HIX22, DAG));
2078
4
    SDValue Lo = DAG.getNode(SPISD::Lo, DL, PtrVT,
2079
4
                 withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LDO_LOX10, DAG));
2080
4
    HiLo =  DAG.getNode(ISD::XOR, DL, PtrVT, Hi, Lo);
2081
4
    return DAG.getNode(SPISD::TLS_ADD, DL, PtrVT, Ret, HiLo,
2082
4
                   withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LDO_ADD, DAG));
2083
4
  }
2084
8
2085
8
  if (model == TLSModel::InitialExec) {
2086
4
    unsigned ldTF     = ((PtrVT == MVT::i64)? 
SparcMCExpr::VK_Sparc_TLS_IE_LDX2
2087
4
                         : 
SparcMCExpr::VK_Sparc_TLS_IE_LD2
);
2088
4
2089
4
    SDValue Base = DAG.getNode(SPISD::GLOBAL_BASE_REG, DL, PtrVT);
2090
4
2091
4
    // GLOBAL_BASE_REG codegen'ed with call. Inform MFI that this
2092
4
    // function has calls.
2093
4
    MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2094
4
    MFI.setHasCalls(true);
2095
4
2096
4
    SDValue TGA = makeHiLoPair(Op,
2097
4
                               SparcMCExpr::VK_Sparc_TLS_IE_HI22,
2098
4
                               SparcMCExpr::VK_Sparc_TLS_IE_LO10, DAG);
2099
4
    SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Base, TGA);
2100
4
    SDValue Offset = DAG.getNode(SPISD::TLS_LD,
2101
4
                                 DL, PtrVT, Ptr,
2102
4
                                 withTargetFlags(Op, ldTF, DAG));
2103
4
    return DAG.getNode(SPISD::TLS_ADD, DL, PtrVT,
2104
4
                       DAG.getRegister(SP::G7, PtrVT), Offset,
2105
4
                       withTargetFlags(Op,
2106
4
                                       SparcMCExpr::VK_Sparc_TLS_IE_ADD, DAG));
2107
4
  }
2108
4
2109
4
  assert(model == TLSModel::LocalExec);
2110
4
  SDValue Hi = DAG.getNode(SPISD::Hi, DL, PtrVT,
2111
4
                  withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LE_HIX22, DAG));
2112
4
  SDValue Lo = DAG.getNode(SPISD::Lo, DL, PtrVT,
2113
4
                  withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LE_LOX10, DAG));
2114
4
  SDValue Offset =  DAG.getNode(ISD::XOR, DL, PtrVT, Hi, Lo);
2115
4
2116
4
  return DAG.getNode(ISD::ADD, DL, PtrVT,
2117
4
                     DAG.getRegister(SP::G7, PtrVT), Offset);
2118
4
}
2119
2120
SDValue SparcTargetLowering::LowerF128_LibCallArg(SDValue Chain,
2121
                                                  ArgListTy &Args, SDValue Arg,
2122
                                                  const SDLoc &DL,
2123
62
                                                  SelectionDAG &DAG) const {
2124
62
  MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2125
62
  EVT ArgVT = Arg.getValueType();
2126
62
  Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2127
62
2128
62
  ArgListEntry Entry;
2129
62
  Entry.Node = Arg;
2130
62
  Entry.Ty   = ArgTy;
2131
62
2132
62
  if (ArgTy->isFP128Ty()) {
2133
46
    // Create a stack object and pass the pointer to the library function.
2134
46
    int FI = MFI.CreateStackObject(16, 8, false);
2135
46
    SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2136
46
    Chain = DAG.getStore(Chain, DL, Entry.Node, FIPtr, MachinePointerInfo(),
2137
46
                         /* Alignment = */ 8);
2138
46
2139
46
    Entry.Node = FIPtr;
2140
46
    Entry.Ty   = PointerType::getUnqual(ArgTy);
2141
46
  }
2142
62
  Args.push_back(Entry);
2143
62
  return Chain;
2144
62
}
2145
2146
SDValue
2147
SparcTargetLowering::LowerF128Op(SDValue Op, SelectionDAG &DAG,
2148
                                 const char *LibFuncName,
2149
43
                                 unsigned numArgs) const {
2150
43
2151
43
  ArgListTy Args;
2152
43
2153
43
  MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2154
43
  auto PtrVT = getPointerTy(DAG.getDataLayout());
2155
43
2156
43
  SDValue Callee = DAG.getExternalSymbol(LibFuncName, PtrVT);
2157
43
  Type *RetTy = Op.getValueType().getTypeForEVT(*DAG.getContext());
2158
43
  Type *RetTyABI = RetTy;
2159
43
  SDValue Chain = DAG.getEntryNode();
2160
43
  SDValue RetPtr;
2161
43
2162
43
  if (RetTy->isFP128Ty()) {
2163
27
    // Create a Stack Object to receive the return value of type f128.
2164
27
    ArgListEntry Entry;
2165
27
    int RetFI = MFI.CreateStackObject(16, 8, false);
2166
27
    RetPtr = DAG.getFrameIndex(RetFI, PtrVT);
2167
27
    Entry.Node = RetPtr;
2168
27
    Entry.Ty   = PointerType::getUnqual(RetTy);
2169
27
    if (!Subtarget->is64Bit())
2170
26
      Entry.IsSRet = true;
2171
27
    Entry.IsReturned = false;
2172
27
    Args.push_back(Entry);
2173
27
    RetTyABI = Type::getVoidTy(*DAG.getContext());
2174
27
  }
2175
43
2176
43
  assert(Op->getNumOperands() >= numArgs && "Not enough operands!");
2177
97
  for (unsigned i = 0, e = numArgs; i != e; 
++i54
) {
2178
54
    Chain = LowerF128_LibCallArg(Chain, Args, Op.getOperand(i), SDLoc(Op), DAG);
2179
54
  }
2180
43
  TargetLowering::CallLoweringInfo CLI(DAG);
2181
43
  CLI.setDebugLoc(SDLoc(Op)).setChain(Chain)
2182
43
    .setCallee(CallingConv::C, RetTyABI, Callee, std::move(Args));
2183
43
2184
43
  std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
2185
43
2186
43
  // chain is in second result.
2187
43
  if (RetTyABI == RetTy)
2188
16
    return CallInfo.first;
2189
27
2190
27
  assert (RetTy->isFP128Ty() && "Unexpected return type!");
2191
27
2192
27
  Chain = CallInfo.second;
2193
27
2194
27
  // Load RetPtr to get the return value.
2195
27
  return DAG.getLoad(Op.getValueType(), SDLoc(Op), Chain, RetPtr,
2196
27
                     MachinePointerInfo(), /* Alignment = */ 8);
2197
27
}
2198
2199
SDValue SparcTargetLowering::LowerF128Compare(SDValue LHS, SDValue RHS,
2200
                                              unsigned &SPCC, const SDLoc &DL,
2201
4
                                              SelectionDAG &DAG) const {
2202
4
2203
4
  const char *LibCall = nullptr;
2204
4
  bool is64Bit = Subtarget->is64Bit();
2205
4
  switch(SPCC) {
2206
4
  
default: 0
llvm_unreachable0
("Unhandled conditional code!");
2207
4
  
case SPCC::FCC_E : LibCall = is64Bit0
?
"_Qp_feq"0
:
"_Q_feq"0
; break;
2208
4
  
case SPCC::FCC_NE : LibCall = is64Bit0
?
"_Qp_fne"0
:
"_Q_fne"0
; break;
2209
4
  
case SPCC::FCC_L : LibCall = is64Bit0
?
"_Qp_flt"0
:
"_Q_flt"0
; break;
2210
4
  
case SPCC::FCC_G : LibCall = is64Bit0
?
"_Qp_fgt"0
:
"_Q_fgt"0
; break;
2211
4
  
case SPCC::FCC_LE : LibCall = is64Bit0
?
"_Qp_fle"0
:
"_Q_fle"0
; break;
2212
4
  
case SPCC::FCC_GE : LibCall = is64Bit0
?
"_Qp_fge"0
:
"_Q_fge"0
; break;
2213
4
  case SPCC::FCC_UL :
2214
4
  case SPCC::FCC_ULE:
2215
4
  case SPCC::FCC_UG :
2216
4
  case SPCC::FCC_UGE:
2217
4
  case SPCC::FCC_U  :
2218
4
  case SPCC::FCC_O  :
2219
4
  case SPCC::FCC_LG :
2220
4
  case SPCC::FCC_UE : LibCall = is64Bit? 
"_Qp_cmp"0
: "_Q_cmp"; break;
2221
4
  }
2222
4
2223
4
  auto PtrVT = getPointerTy(DAG.getDataLayout());
2224
4
  SDValue Callee = DAG.getExternalSymbol(LibCall, PtrVT);
2225
4
  Type *RetTy = Type::getInt32Ty(*DAG.getContext());
2226
4
  ArgListTy Args;
2227
4
  SDValue Chain = DAG.getEntryNode();
2228
4
  Chain = LowerF128_LibCallArg(Chain, Args, LHS, DL, DAG);
2229
4
  Chain = LowerF128_LibCallArg(Chain, Args, RHS, DL, DAG);
2230
4
2231
4
  TargetLowering::CallLoweringInfo CLI(DAG);
2232
4
  CLI.setDebugLoc(DL).setChain(Chain)
2233
4
    .setCallee(CallingConv::C, RetTy, Callee, std::move(Args));
2234
4
2235
4
  std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
2236
4
2237
4
  // result is in first, and chain is in second result.
2238
4
  SDValue Result =  CallInfo.first;
2239
4
2240
4
  switch(SPCC) {
2241
4
  default: {
2242
0
    SDValue RHS = DAG.getTargetConstant(0, DL, Result.getValueType());
2243
0
    SPCC = SPCC::ICC_NE;
2244
0
    return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2245
4
  }
2246
4
  case SPCC::FCC_UL : {
2247
2
    SDValue Mask   = DAG.getTargetConstant(1, DL, Result.getValueType());
2248
2
    Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
2249
2
    SDValue RHS    = DAG.getTargetConstant(0, DL, Result.getValueType());
2250
2
    SPCC = SPCC::ICC_NE;
2251
2
    return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2252
4
  }
2253
4
  case SPCC::FCC_ULE: {
2254
2
    SDValue RHS = DAG.getTargetConstant(2, DL, Result.getValueType());
2255
2
    SPCC = SPCC::ICC_NE;
2256
2
    return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2257
4
  }
2258
4
  case SPCC::FCC_UG :  {
2259
0
    SDValue RHS = DAG.getTargetConstant(1, DL, Result.getValueType());
2260
0
    SPCC = SPCC::ICC_G;
2261
0
    return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2262
4
  }
2263
4
  case SPCC::FCC_UGE: {
2264
0
    SDValue RHS = DAG.getTargetConstant(1, DL, Result.getValueType());
2265
0
    SPCC = SPCC::ICC_NE;
2266
0
    return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2267
4
  }
2268
4
2269
4
  case SPCC::FCC_U  :  {
2270
0
    SDValue RHS = DAG.getTargetConstant(3, DL, Result.getValueType());
2271
0
    SPCC = SPCC::ICC_E;
2272
0
    return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2273
4
  }
2274
4
  case SPCC::FCC_O  :  {
2275
0
    SDValue RHS = DAG.getTargetConstant(3, DL, Result.getValueType());
2276
0
    SPCC = SPCC::ICC_NE;
2277
0
    return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2278
4
  }
2279
4
  case SPCC::FCC_LG :  {
2280
0
    SDValue Mask   = DAG.getTargetConstant(3, DL, Result.getValueType());
2281
0
    Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
2282
0
    SDValue RHS    = DAG.getTargetConstant(0, DL, Result.getValueType());
2283
0
    SPCC = SPCC::ICC_NE;
2284
0
    return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2285
4
  }
2286
4
  case SPCC::FCC_UE : {
2287
0
    SDValue Mask   = DAG.getTargetConstant(3, DL, Result.getValueType());
2288
0
    Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
2289
0
    SDValue RHS    = DAG.getTargetConstant(0, DL, Result.getValueType());
2290
0
    SPCC = SPCC::ICC_E;
2291
0
    return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2292
4
  }
2293
4
  }
2294
4
}
2295
2296
static SDValue
2297
LowerF128_FPEXTEND(SDValue Op, SelectionDAG &DAG,
2298
0
                   const SparcTargetLowering &TLI) {
2299
0
2300
0
  if (Op.getOperand(0).getValueType() == MVT::f64)
2301
0
    return TLI.LowerF128Op(Op, DAG,
2302
0
                           TLI.getLibcallName(RTLIB::FPEXT_F64_F128), 1);
2303
0
2304
0
  if (Op.getOperand(0).getValueType() == MVT::f32)
2305
0
    return TLI.LowerF128Op(Op, DAG,
2306
0
                           TLI.getLibcallName(RTLIB::FPEXT_F32_F128), 1);
2307
0
2308
0
  llvm_unreachable("fpextend with non-float operand!");
2309
0
  return SDValue();
2310
0
}
2311
2312
static SDValue
2313
LowerF128_FPROUND(SDValue Op, SelectionDAG &DAG,
2314
14
                  const SparcTargetLowering &TLI) {
2315
14
  // FP_ROUND on f64 and f32 are legal.
2316
14
  if (Op.getOperand(0).getValueType() != MVT::f128)
2317
14
    return Op;
2318
0
2319
0
  if (Op.getValueType() == MVT::f64)
2320
0
    return TLI.LowerF128Op(Op, DAG,
2321
0
                           TLI.getLibcallName(RTLIB::FPROUND_F128_F64), 1);
2322
0
  if (Op.getValueType() == MVT::f32)
2323
0
    return TLI.LowerF128Op(Op, DAG,
2324
0
                           TLI.getLibcallName(RTLIB::FPROUND_F128_F32), 1);
2325
0
2326
0
  llvm_unreachable("fpround to non-float!");
2327
0
  return SDValue();
2328
0
}
2329
2330
static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG,
2331
                               const SparcTargetLowering &TLI,
2332
54
                               bool hasHardQuad) {
2333
54
  SDLoc dl(Op);
2334
54
  EVT VT = Op.getValueType();
2335
54
  assert(VT == MVT::i32 || VT == MVT::i64);
2336
54
2337
54
  // Expand f128 operations to fp128 abi calls.
2338
54
  if (Op.getOperand(0).getValueType() == MVT::f128
2339
54
      && 
(16
!hasHardQuad16
||
!TLI.isTypeLegal(VT)12
)) {
2340
4
    const char *libName = TLI.getLibcallName(VT == MVT::i32
2341
4
                                             ? RTLIB::FPTOSINT_F128_I32
2342
4
                                             : 
RTLIB::FPTOSINT_F128_I640
);
2343
4
    return TLI.LowerF128Op(Op, DAG, libName, 1);
2344
4
  }
2345
50
2346
50
  // Expand if the resulting type is illegal.
2347
50
  if (!TLI.isTypeLegal(VT))
2348
0
    return SDValue();
2349
50
2350
50
  // Otherwise, Convert the fp value to integer in an FP register.
2351
50
  if (VT == MVT::i32)
2352
44
    Op = DAG.getNode(SPISD::FTOI, dl, MVT::f32, Op.getOperand(0));
2353
6
  else
2354
6
    Op = DAG.getNode(SPISD::FTOX, dl, MVT::f64, Op.getOperand(0));
2355
50
2356
50
  return DAG.getNode(ISD::BITCAST, dl, VT, Op);
2357
50
}
2358
2359
static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG,
2360
                               const SparcTargetLowering &TLI,
2361
36
                               bool hasHardQuad) {
2362
36
  SDLoc dl(Op);
2363
36
  EVT OpVT = Op.getOperand(0).getValueType();
2364
36
  assert(OpVT == MVT::i32 || (OpVT == MVT::i64));
2365
36
2366
36
  EVT floatVT = (OpVT == MVT::i32) ? 
MVT::f3220
:
MVT::f6416
;
2367
36
2368
36
  // Expand f128 operations to fp128 ABI calls.
2369
36
  if (Op.getValueType() == MVT::f128
2370
36
      && 
(12
!hasHardQuad12
||
!TLI.isTypeLegal(OpVT)6
)) {
2371
8
    const char *libName = TLI.getLibcallName(OpVT == MVT::i32
2372
8
                                             ? 
RTLIB::SINTTOFP_I32_F1284
2373
8
                                             : 
RTLIB::SINTTOFP_I64_F1284
);
2374
8
    return TLI.LowerF128Op(Op, DAG, libName, 1);
2375
8
  }
2376
28
2377
28
  // Expand if the operand type is illegal.
2378
28
  if (!TLI.isTypeLegal(OpVT))
2379
8
    return SDValue();
2380
20
2381
20
  // Otherwise, Convert the int value to FP in an FP register.
2382
20
  SDValue Tmp = DAG.getNode(ISD::BITCAST, dl, floatVT, Op.getOperand(0));
2383
20
  unsigned opcode = (OpVT == MVT::i32)? 
SPISD::ITOF16
:
SPISD::XTOF4
;
2384
20
  return DAG.getNode(opcode, dl, Op.getValueType(), Tmp);
2385
20
}
2386
2387
static SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG,
2388
                               const SparcTargetLowering &TLI,
2389
20
                               bool hasHardQuad) {
2390
20
  SDLoc dl(Op);
2391
20
  EVT VT = Op.getValueType();
2392
20
2393
20
  // Expand if it does not involve f128 or the target has support for
2394
20
  // quad floating point instructions and the resulting type is legal.
2395
20
  if (Op.getOperand(0).getValueType() != MVT::f128 ||
2396
20
      
(8
hasHardQuad8
&&
TLI.isTypeLegal(VT)4
))
2397
16
    return SDValue();
2398
4
2399
4
  assert(VT == MVT::i32 || VT == MVT::i64);
2400
4
2401
4
  return TLI.LowerF128Op(Op, DAG,
2402
4
                         TLI.getLibcallName(VT == MVT::i32
2403
4
                                            ? RTLIB::FPTOUINT_F128_I32
2404
4
                                            : 
RTLIB::FPTOUINT_F128_I640
),
2405
4
                         1);
2406
4
}
2407
2408
static SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG,
2409
                               const SparcTargetLowering &TLI,
2410
32
                               bool hasHardQuad) {
2411
32
  SDLoc dl(Op);
2412
32
  EVT OpVT = Op.getOperand(0).getValueType();
2413
32
  assert(OpVT == MVT::i32 || OpVT == MVT::i64);
2414
32
2415
32
  // Expand if it does not involve f128 or the target has support for
2416
32
  // quad floating point instructions and the operand type is legal.
2417
32
  if (Op.getValueType() != MVT::f128 || 
(12
hasHardQuad12
&&
TLI.isTypeLegal(OpVT)6
))
2418
24
    return SDValue();
2419
8
2420
8
  return TLI.LowerF128Op(Op, DAG,
2421
8
                         TLI.getLibcallName(OpVT == MVT::i32
2422
8
                                            ? 
RTLIB::UINTTOFP_I32_F1284
2423
8
                                            : 
RTLIB::UINTTOFP_I64_F1284
),
2424
8
                         1);
2425
8
}
2426
2427
static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG,
2428
                          const SparcTargetLowering &TLI,
2429
73
                          bool hasHardQuad) {
2430
73
  SDValue Chain = Op.getOperand(0);
2431
73
  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2432
73
  SDValue LHS = Op.getOperand(2);
2433
73
  SDValue RHS = Op.getOperand(3);
2434
73
  SDValue Dest = Op.getOperand(4);
2435
73
  SDLoc dl(Op);
2436
73
  unsigned Opc, SPCC = ~0U;
2437
73
2438
73
  // If this is a br_cc of a "setcc", and if the setcc got lowered into
2439
73
  // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
2440
73
  LookThroughSetCC(LHS, RHS, CC, SPCC);
2441
73
2442
73
  // Get the condition flag.
2443
73
  SDValue CompareFlag;
2444
73
  if (LHS.getValueType().isInteger()) {
2445
63
    CompareFlag = DAG.getNode(SPISD::CMPICC, dl, MVT::Glue, LHS, RHS);
2446
63
    if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
2447
63
    // 32-bit compares use the icc flags, 64-bit uses the xcc flags.
2448
63
    Opc = LHS.getValueType() == MVT::i32 ? 
SPISD::BRICC58
:
SPISD::BRXCC5
;
2449
63
  } else {
2450
10
    if (!hasHardQuad && 
LHS.getValueType() == MVT::f1288
) {
2451
2
      if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2452
2
      CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, dl, DAG);
2453
2
      Opc = SPISD::BRICC;
2454
8
    } else {
2455
8
      CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS);
2456
8
      if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2457
8
      Opc = SPISD::BRFCC;
2458
8
    }
2459
10
  }
2460
73
  return DAG.getNode(Opc, dl, MVT::Other, Chain, Dest,
2461
73
                     DAG.getConstant(SPCC, dl, MVT::i32), CompareFlag);
2462
73
}
2463
2464
static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG,
2465
                              const SparcTargetLowering &TLI,
2466
126
                              bool hasHardQuad) {
2467
126
  SDValue LHS = Op.getOperand(0);
2468
126
  SDValue RHS = Op.getOperand(1);
2469
126
  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2470
126
  SDValue TrueVal = Op.getOperand(2);
2471
126
  SDValue FalseVal = Op.getOperand(3);
2472
126
  SDLoc dl(Op);
2473
126
  unsigned Opc, SPCC = ~0U;
2474
126
2475
126
  // If this is a select_cc of a "setcc", and if the setcc got lowered into
2476
126
  // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
2477
126
  LookThroughSetCC(LHS, RHS, CC, SPCC);
2478
126
2479
126
  SDValue CompareFlag;
2480
126
  if (LHS.getValueType().isInteger()) {
2481
96
    CompareFlag = DAG.getNode(SPISD::CMPICC, dl, MVT::Glue, LHS, RHS);
2482
96
    Opc = LHS.getValueType() == MVT::i32 ?
2483
74
          SPISD::SELECT_ICC : 
SPISD::SELECT_XCC22
;
2484
96
    if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
2485
96
  } else {
2486
30
    if (!hasHardQuad && 
LHS.getValueType() == MVT::f12824
) {
2487
2
      if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2488
2
      CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, dl, DAG);
2489
2
      Opc = SPISD::SELECT_ICC;
2490
28
    } else {
2491
28
      CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS);
2492
28
      Opc = SPISD::SELECT_FCC;
2493
28
      if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2494
28
    }
2495
30
  }
2496
126
  return DAG.getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal,
2497
126
                     DAG.getConstant(SPCC, dl, MVT::i32), CompareFlag);
2498
126
}
2499
2500
static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
2501
2
                            const SparcTargetLowering &TLI) {
2502
2
  MachineFunction &MF = DAG.getMachineFunction();
2503
2
  SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
2504
2
  auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
2505
2
2506
2
  // Need frame address to find the address of VarArgsFrameIndex.
2507
2
  MF.getFrameInfo().setFrameAddressIsTaken(true);
2508
2
2509
2
  // vastart just stores the address of the VarArgsFrameIndex slot into the
2510
2
  // memory location argument.
2511
2
  SDLoc DL(Op);
2512
2
  SDValue Offset =
2513
2
      DAG.getNode(ISD::ADD, DL, PtrVT, DAG.getRegister(SP::I6, PtrVT),
2514
2
                  DAG.getIntPtrConstant(FuncInfo->getVarArgsFrameOffset(), DL));
2515
2
  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2516
2
  return DAG.getStore(Op.getOperand(0), DL, Offset, Op.getOperand(1),
2517
2
                      MachinePointerInfo(SV));
2518
2
}
2519
2520
7
static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) {
2521
7
  SDNode *Node = Op.getNode();
2522
7
  EVT VT = Node->getValueType(0);
2523
7
  SDValue InChain = Node->getOperand(0);
2524
7
  SDValue VAListPtr = Node->getOperand(1);
2525
7
  EVT PtrVT = VAListPtr.getValueType();
2526
7
  const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2527
7
  SDLoc DL(Node);
2528
7
  SDValue VAList =
2529
7
      DAG.getLoad(PtrVT, DL, InChain, VAListPtr, MachinePointerInfo(SV));
2530
7
  // Increment the pointer, VAList, to the next vaarg.
2531
7
  SDValue NextPtr = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
2532
7
                                DAG.getIntPtrConstant(VT.getSizeInBits()/8,
2533
7
                                                      DL));
2534
7
  // Store the incremented VAList to the legalized pointer.
2535
7
  InChain = DAG.getStore(VAList.getValue(1), DL, NextPtr, VAListPtr,
2536
7
                         MachinePointerInfo(SV));
2537
7
  // Load the actual argument out of the pointer VAList.
2538
7
  // We can't count on greater alignment than the word size.
2539
7
  return DAG.getLoad(VT, DL, InChain, VAList, MachinePointerInfo(),
2540
7
                     std::min(PtrVT.getSizeInBits(), VT.getSizeInBits()) / 8);
2541
7
}
2542
2543
static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG,
2544
4
                                       const SparcSubtarget *Subtarget) {
2545
4
  SDValue Chain = Op.getOperand(0);  // Legalize the chain.
2546
4
  SDValue Size  = Op.getOperand(1);  // Legalize the size.
2547
4
  unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
2548
4
  unsigned StackAlign = Subtarget->getFrameLowering()->getStackAlignment();
2549
4
  EVT VT = Size->getValueType(0);
2550
4
  SDLoc dl(Op);
2551
4
2552
4
  // TODO: implement over-aligned alloca. (Note: also implies
2553
4
  // supporting support for overaligned function frames + dynamic
2554
4
  // allocations, at all, which currently isn't supported)
2555
4
  if (Align > StackAlign) {
2556
0
    const MachineFunction &MF = DAG.getMachineFunction();
2557
0
    report_fatal_error("Function \"" + Twine(MF.getName()) + "\": "
2558
0
                       "over-aligned dynamic alloca not supported.");
2559
0
  }
2560
4
2561
4
  // The resultant pointer needs to be above the register spill area
2562
4
  // at the bottom of the stack.
2563
4
  unsigned regSpillArea;
2564
4
  if (Subtarget->is64Bit()) {
2565
2
    regSpillArea = 128;
2566
2
  } else {
2567
2
    // On Sparc32, the size of the spill area is 92. Unfortunately,
2568
2
    // that's only 4-byte aligned, not 8-byte aligned (the stack
2569
2
    // pointer is 8-byte aligned). So, if the user asked for an 8-byte
2570
2
    // aligned dynamic allocation, we actually need to add 96 to the
2571
2
    // bottom of the stack, instead of 92, to ensure 8-byte alignment.
2572
2
2573
2
    // That also means adding 4 to the size of the allocation --
2574
2
    // before applying the 8-byte rounding. Unfortunately, we the
2575
2
    // value we get here has already had rounding applied. So, we need
2576
2
    // to add 8, instead, wasting a bit more memory.
2577
2
2578
2
    // Further, this only actually needs to be done if the required
2579
2
    // alignment is > 4, but, we've lost that info by this point, too,
2580
2
    // so we always apply it.
2581
2
2582
2
    // (An alternative approach would be to always reserve 96 bytes
2583
2
    // instead of the required 92, but then we'd waste 4 extra bytes
2584
2
    // in every frame, not just those with dynamic stack allocations)
2585
2
2586
2
    // TODO: modify code in SelectionDAGBuilder to make this less sad.
2587
2
2588
2
    Size = DAG.getNode(ISD::ADD, dl, VT, Size,
2589
2
                       DAG.getConstant(8, dl, VT));
2590
2
    regSpillArea = 96;
2591
2
  }
2592
4
2593
4
  unsigned SPReg = SP::O6;
2594
4
  SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
2595
4
  SDValue NewSP = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
2596
4
  Chain = DAG.getCopyToReg(SP.getValue(1), dl, SPReg, NewSP);    // Output chain
2597
4
2598
4
  regSpillArea += Subtarget->getStackPointerBias();
2599
4
2600
4
  SDValue NewVal = DAG.getNode(ISD::ADD, dl, VT, NewSP,
2601
4
                               DAG.getConstant(regSpillArea, dl, VT));
2602
4
  SDValue Ops[2] = { NewVal, Chain };
2603
4
  return DAG.getMergeValues(Ops, dl);
2604
4
}
2605
2606
2607
15
static SDValue getFLUSHW(SDValue Op, SelectionDAG &DAG) {
2608
15
  SDLoc dl(Op);
2609
15
  SDValue Chain = DAG.getNode(SPISD::FLUSHW,
2610
15
                              dl, MVT::Other, DAG.getEntryNode());
2611
15
  return Chain;
2612
15
}
2613
2614
static SDValue getFRAMEADDR(uint64_t depth, SDValue Op, SelectionDAG &DAG,
2615
                            const SparcSubtarget *Subtarget,
2616
20
                            bool AlwaysFlush = false) {
2617
20
  MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2618
20
  MFI.setFrameAddressIsTaken(true);
2619
20
2620
20
  EVT VT = Op.getValueType();
2621
20
  SDLoc dl(Op);
2622
20
  unsigned FrameReg = SP::I6;
2623
20
  unsigned stackBias = Subtarget->getStackPointerBias();
2624
20
2625
20
  SDValue FrameAddr;
2626
20
  SDValue Chain;
2627
20
2628
20
  // flush first to make sure the windowed registers' values are in stack
2629
20
  Chain = (depth || 
AlwaysFlush10
) ?
getFLUSHW(Op, DAG)15
:
DAG.getEntryNode()5
;
2630
20
2631
20
  FrameAddr = DAG.getCopyFromReg(Chain, dl, FrameReg, VT);
2632
20
2633
20
  unsigned Offset = (Subtarget->is64Bit()) ? 
(stackBias + 112)4
:
5616
;
2634
20
2635
45
  while (depth--) {
2636
25
    SDValue Ptr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr,
2637
25
                              DAG.getIntPtrConstant(Offset, dl));
2638
25
    FrameAddr = DAG.getLoad(VT, dl, Chain, Ptr, MachinePointerInfo());
2639
25
  }
2640
20
  if (Subtarget->is64Bit())
2641
4
    FrameAddr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr,
2642
4
                            DAG.getIntPtrConstant(stackBias, dl));
2643
20
  return FrameAddr;
2644
20
}
2645
2646
2647
static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG,
2648
10
                              const SparcSubtarget *Subtarget) {
2649
10
2650
10
  uint64_t depth = Op.getConstantOperandVal(0);
2651
10
2652
10
  return getFRAMEADDR(depth, Op, DAG, Subtarget);
2653
10
2654
10
}
2655
2656
static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG,
2657
                               const SparcTargetLowering &TLI,
2658
15
                               const SparcSubtarget *Subtarget) {
2659
15
  MachineFunction &MF = DAG.getMachineFunction();
2660
15
  MachineFrameInfo &MFI = MF.getFrameInfo();
2661
15
  MFI.setReturnAddressIsTaken(true);
2662
15
2663
15
  if (TLI.verifyReturnAddressArgumentIsConstant(Op, DAG))
2664
0
    return SDValue();
2665
15
2666
15
  EVT VT = Op.getValueType();
2667
15
  SDLoc dl(Op);
2668
15
  uint64_t depth = Op.getConstantOperandVal(0);
2669
15
2670
15
  SDValue RetAddr;
2671
15
  if (depth == 0) {
2672
5
    auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
2673
5
    unsigned RetReg = MF.addLiveIn(SP::I7, TLI.getRegClassFor(PtrVT));
2674
5
    RetAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, RetReg, VT);
2675
5
    return RetAddr;
2676
5
  }
2677
10
2678
10
  // Need frame address to find return address of the caller.
2679
10
  SDValue FrameAddr = getFRAMEADDR(depth - 1, Op, DAG, Subtarget, true);
2680
10
2681
10
  unsigned Offset = (Subtarget->is64Bit()) ? 
1202
:
608
;
2682
10
  SDValue Ptr = DAG.getNode(ISD::ADD,
2683
10
                            dl, VT,
2684
10
                            FrameAddr,
2685
10
                            DAG.getIntPtrConstant(Offset, dl));
2686
10
  RetAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), Ptr, MachinePointerInfo());
2687
10
2688
10
  return RetAddr;
2689
10
}
2690
2691
static SDValue LowerF64Op(SDValue SrcReg64, const SDLoc &dl, SelectionDAG &DAG,
2692
14
                          unsigned opcode) {
2693
14
  assert(SrcReg64.getValueType() == MVT::f64 && "LowerF64Op called on non-double!");
2694
14
  assert(opcode == ISD::FNEG || opcode == ISD::FABS);
2695
14
2696
14
  // Lower fneg/fabs on f64 to fneg/fabs on f32.
2697
14
  // fneg f64 => fneg f32:sub_even, fmov f32:sub_odd.
2698
14
  // fabs f64 => fabs f32:sub_even, fmov f32:sub_odd.
2699
14
2700
14
  // Note: in little-endian, the floating-point value is stored in the
2701
14
  // registers are in the opposite order, so the subreg with the sign
2702
14
  // bit is the highest-numbered (odd), rather than the
2703
14
  // lowest-numbered (even).
2704
14
2705
14
  SDValue Hi32 = DAG.getTargetExtractSubreg(SP::sub_even, dl, MVT::f32,
2706
14
                                            SrcReg64);
2707
14
  SDValue Lo32 = DAG.getTargetExtractSubreg(SP::sub_odd, dl, MVT::f32,
2708
14
                                            SrcReg64);
2709
14
2710
14
  if (DAG.getDataLayout().isLittleEndian())
2711
6
    Lo32 = DAG.getNode(opcode, dl, MVT::f32, Lo32);
2712
8
  else
2713
8
    Hi32 = DAG.getNode(opcode, dl, MVT::f32, Hi32);
2714
14
2715
14
  SDValue DstReg64 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
2716
14
                                                dl, MVT::f64), 0);
2717
14
  DstReg64 = DAG.getTargetInsertSubreg(SP::sub_even, dl, MVT::f64,
2718
14
                                       DstReg64, Hi32);
2719
14
  DstReg64 = DAG.getTargetInsertSubreg(SP::sub_odd, dl, MVT::f64,
2720
14
                                       DstReg64, Lo32);
2721
14
  return DstReg64;
2722
14
}
2723
2724
// Lower a f128 load into two f64 loads.
2725
static SDValue LowerF128Load(SDValue Op, SelectionDAG &DAG)
2726
1.11k
{
2727
1.11k
  SDLoc dl(Op);
2728
1.11k
  LoadSDNode *LdNode = dyn_cast<LoadSDNode>(Op.getNode());
2729
1.11k
  assert(LdNode && LdNode->getOffset().isUndef()
2730
1.11k
         && "Unexpected node type");
2731
1.11k
2732
1.11k
  unsigned alignment = LdNode->getAlignment();
2733
1.11k
  if (alignment > 8)
2734
1
    alignment = 8;
2735
1.11k
2736
1.11k
  SDValue Hi64 =
2737
1.11k
      DAG.getLoad(MVT::f64, dl, LdNode->getChain(), LdNode->getBasePtr(),
2738
1.11k
                  LdNode->getPointerInfo(), alignment);
2739
1.11k
  EVT addrVT = LdNode->getBasePtr().getValueType();
2740
1.11k
  SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT,
2741
1.11k
                              LdNode->getBasePtr(),
2742
1.11k
                              DAG.getConstant(8, dl, addrVT));
2743
1.11k
  SDValue Lo64 = DAG.getLoad(MVT::f64, dl, LdNode->getChain(), LoPtr,
2744
1.11k
                             LdNode->getPointerInfo(), alignment);
2745
1.11k
2746
1.11k
  SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, dl, MVT::i32);
2747
1.11k
  SDValue SubRegOdd  = DAG.getTargetConstant(SP::sub_odd64, dl, MVT::i32);
2748
1.11k
2749
1.11k
  SDNode *InFP128 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
2750
1.11k
                                       dl, MVT::f128);
2751
1.11k
  InFP128 = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl,
2752
1.11k
                               MVT::f128,
2753
1.11k
                               SDValue(InFP128, 0),
2754
1.11k
                               Hi64,
2755
1.11k
                               SubRegEven);
2756
1.11k
  InFP128 = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl,
2757
1.11k
                               MVT::f128,
2758
1.11k
                               SDValue(InFP128, 0),
2759
1.11k
                               Lo64,
2760
1.11k
                               SubRegOdd);
2761
1.11k
  SDValue OutChains[2] = { SDValue(Hi64.getNode(), 1),
2762
1.11k
                           SDValue(Lo64.getNode(), 1) };
2763
1.11k
  SDValue OutChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
2764
1.11k
  SDValue Ops[2] = {SDValue(InFP128,0), OutChain};
2765
1.11k
  return DAG.getMergeValues(Ops, dl);
2766
1.11k
}
2767
2768
static SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG)
2769
1.11k
{
2770
1.11k
  LoadSDNode *LdNode = cast<LoadSDNode>(Op.getNode());
2771
1.11k
2772
1.11k
  EVT MemVT = LdNode->getMemoryVT();
2773
1.11k
  if (MemVT == MVT::f128)
2774
1.11k
    return LowerF128Load(Op, DAG);
2775
0
2776
0
  return Op;
2777
0
}
2778
2779
// Lower a f128 store into two f64 stores.
2780
1.09k
static SDValue LowerF128Store(SDValue Op, SelectionDAG &DAG) {
2781
1.09k
  SDLoc dl(Op);
2782
1.09k
  StoreSDNode *StNode = dyn_cast<StoreSDNode>(Op.getNode());
2783
1.09k
  assert(StNode && StNode->getOffset().isUndef()
2784
1.09k
         && "Unexpected node type");
2785
1.09k
  SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, dl, MVT::i32);
2786
1.09k
  SDValue SubRegOdd  = DAG.getTargetConstant(SP::sub_odd64, dl, MVT::i32);
2787
1.09k
2788
1.09k
  SDNode *Hi64 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG,
2789
1.09k
                                    dl,
2790
1.09k
                                    MVT::f64,
2791
1.09k
                                    StNode->getValue(),
2792
1.09k
                                    SubRegEven);
2793
1.09k
  SDNode *Lo64 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG,
2794
1.09k
                                    dl,
2795
1.09k
                                    MVT::f64,
2796
1.09k
                                    StNode->getValue(),
2797
1.09k
                                    SubRegOdd);
2798
1.09k
2799
1.09k
  unsigned alignment = StNode->getAlignment();
2800
1.09k
  if (alignment > 8)
2801
1
    alignment = 8;
2802
1.09k
2803
1.09k
  SDValue OutChains[2];
2804
1.09k
  OutChains[0] =
2805
1.09k
      DAG.getStore(StNode->getChain(), dl, SDValue(Hi64, 0),
2806
1.09k
                   StNode->getBasePtr(), MachinePointerInfo(), alignment);
2807
1.09k
  EVT addrVT = StNode->getBasePtr().getValueType();
2808
1.09k
  SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT,
2809
1.09k
                              StNode->getBasePtr(),
2810
1.09k
                              DAG.getConstant(8, dl, addrVT));
2811
1.09k
  OutChains[1] = DAG.getStore(StNode->getChain(), dl, SDValue(Lo64, 0), LoPtr,
2812
1.09k
                              MachinePointerInfo(), alignment);
2813
1.09k
  return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
2814
1.09k
}
2815
2816
static SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG)
2817
1.18k
{
2818
1.18k
  SDLoc dl(Op);
2819
1.18k
  StoreSDNode *St = cast<StoreSDNode>(Op.getNode());
2820
1.18k
2821
1.18k
  EVT MemVT = St->getMemoryVT();
2822
1.18k
  if (MemVT == MVT::f128)
2823
1.09k
    return LowerF128Store(Op, DAG);
2824
87
2825
87
  if (MemVT == MVT::i64) {
2826
87
    // Custom handling for i64 stores: turn it into a bitcast and a
2827
87
    // v2i32 store.
2828
87
    SDValue Val = DAG.getNode(ISD::BITCAST, dl, MVT::v2i32, St->getValue());
2829
87
    SDValue Chain = DAG.getStore(
2830
87
        St->getChain(), dl, Val, St->getBasePtr(), St->getPointerInfo(),
2831
87
        St->getAlignment(), St->getMemOperand()->getFlags(), St->getAAInfo());
2832
87
    return Chain;
2833
87
  }
2834
0
2835
0
  return SDValue();
2836
0
}
2837
2838
14
static SDValue LowerFNEGorFABS(SDValue Op, SelectionDAG &DAG, bool isV9) {
2839
14
  assert((Op.getOpcode() == ISD::FNEG || Op.getOpcode() == ISD::FABS)
2840
14
         && "invalid opcode");
2841
14
2842
14
  SDLoc dl(Op);
2843
14
2844
14
  if (Op.getValueType() == MVT::f64)
2845
6
    return LowerF64Op(Op.getOperand(0), dl, DAG, Op.getOpcode());
2846
8
  if (Op.getValueType() != MVT::f128)
2847
0
    return Op;
2848
8
2849
8
  // Lower fabs/fneg on f128 to fabs/fneg on f64
2850
8
  // fabs/fneg f128 => fabs/fneg f64:sub_even64, fmov f64:sub_odd64
2851
8
  // (As with LowerF64Op, on little-endian, we need to negate the odd
2852
8
  // subreg)
2853
8
2854
8
  SDValue SrcReg128 = Op.getOperand(0);
2855
8
  SDValue Hi64 = DAG.getTargetExtractSubreg(SP::sub_even64, dl, MVT::f64,
2856
8
                                            SrcReg128);
2857
8
  SDValue Lo64 = DAG.getTargetExtractSubreg(SP::sub_odd64, dl, MVT::f64,
2858
8
                                            SrcReg128);
2859
8
2860
8
  if (DAG.getDataLayout().isLittleEndian()) {
2861
4
    if (isV9)
2862
0
      Lo64 = DAG.getNode(Op.getOpcode(), dl, MVT::f64, Lo64);
2863
4
    else
2864
4
      Lo64 = LowerF64Op(Lo64, dl, DAG, Op.getOpcode());
2865
4
  } else {
2866
4
    if (isV9)
2867
0
      Hi64 = DAG.getNode(Op.getOpcode(), dl, MVT::f64, Hi64);
2868
4
    else
2869
4
      Hi64 = LowerF64Op(Hi64, dl, DAG, Op.getOpcode());
2870
4
  }
2871
8
2872
8
  SDValue DstReg128 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
2873
8
                                                 dl, MVT::f128), 0);
2874
8
  DstReg128 = DAG.getTargetInsertSubreg(SP::sub_even64, dl, MVT::f128,
2875
8
                                        DstReg128, Hi64);
2876
8
  DstReg128 = DAG.getTargetInsertSubreg(SP::sub_odd64, dl, MVT::f128,
2877
8
                                        DstReg128, Lo64);
2878
8
  return DstReg128;
2879
8
}
2880
2881
132
static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
2882
132
2883
132
  if (Op.getValueType() != MVT::i64)
2884
128
    return Op;
2885
4
2886
4
  SDLoc dl(Op);
2887
4
  SDValue Src1 = Op.getOperand(0);
2888
4
  SDValue Src1Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1);
2889
4
  SDValue Src1Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src1,
2890
4
                               DAG.getConstant(32, dl, MVT::i64));
2891
4
  Src1Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1Hi);
2892
4
2893
4
  SDValue Src2 = Op.getOperand(1);
2894
4
  SDValue Src2Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2);
2895
4
  SDValue Src2Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src2,
2896
4
                               DAG.getConstant(32, dl, MVT::i64));
2897
4
  Src2Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2Hi);
2898
4
2899
4
2900
4
  bool hasChain = false;
2901
4
  unsigned hiOpc = Op.getOpcode();
2902
4
  switch (Op.getOpcode()) {
2903
4
  
default: 0
llvm_unreachable0
("Invalid opcode");
2904
4
  
case ISD::ADDC: hiOpc = ISD::ADDE; break1
;
2905
4
  
case ISD::ADDE: hasChain = true; break1
;
2906
4
  
case ISD::SUBC: hiOpc = ISD::SUBE; break1
;
2907
4
  
case ISD::SUBE: hasChain = true; break1
;
2908
4
  }
2909
4
  SDValue Lo;
2910
4
  SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Glue);
2911
4
  if (hasChain) {
2912
2
    Lo = DAG.getNode(Op.getOpcode(), dl, VTs, Src1Lo, Src2Lo,
2913
2
                     Op.getOperand(2));
2914
2
  } else {
2915
2
    Lo = DAG.getNode(Op.getOpcode(), dl, VTs, Src1Lo, Src2Lo);
2916
2
  }
2917
4
  SDValue Hi = DAG.getNode(hiOpc, dl, VTs, Src1Hi, Src2Hi, Lo.getValue(1));
2918
4
  SDValue Carry = Hi.getValue(1);
2919
4
2920
4
  Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Lo);
2921
4
  Hi = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Hi);
2922
4
  Hi = DAG.getNode(ISD::SHL, dl, MVT::i64, Hi,
2923
4
                   DAG.getConstant(32, dl, MVT::i64));
2924
4
2925
4
  SDValue Dst = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, Lo);
2926
4
  SDValue Ops[2] = { Dst, Carry };
2927
4
  return DAG.getMergeValues(Ops, dl);
2928
4
}
2929
2930
// Custom lower UMULO/SMULO for SPARC. This code is similar to ExpandNode()
2931
// in LegalizeDAG.cpp except the order of arguments to the library function.
2932
static SDValue LowerUMULO_SMULO(SDValue Op, SelectionDAG &DAG,
2933
                                const SparcTargetLowering &TLI)
2934
3
{
2935
3
  unsigned opcode = Op.getOpcode();
2936
3
  assert((opcode == ISD::UMULO || opcode == ISD::SMULO) && "Invalid Opcode.");
2937
3
2938
3
  bool isSigned = (opcode == ISD::SMULO);
2939
3
  EVT VT = MVT::i64;
2940
3
  EVT WideVT = MVT::i128;
2941
3
  SDLoc dl(Op);
2942
3
  SDValue LHS = Op.getOperand(0);
2943
3
2944
3
  if (LHS.getValueType() != VT)
2945
0
    return Op;
2946
3
2947
3
  SDValue ShiftAmt = DAG.getConstant(63, dl, VT);
2948
3
2949
3
  SDValue RHS = Op.getOperand(1);
2950
3
  SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, LHS, ShiftAmt);
2951
3
  SDValue HiRHS = DAG.getNode(ISD::SRA, dl, MVT::i64, RHS, ShiftAmt);
2952
3
  SDValue Args[] = { HiLHS, LHS, HiRHS, RHS };
2953
3
2954
3
  SDValue MulResult = TLI.makeLibCall(DAG,
2955
3
                                      RTLIB::MUL_I128, WideVT,
2956
3
                                      Args, isSigned, dl).first;
2957
3
  SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT,
2958
3
                                   MulResult, DAG.getIntPtrConstant(0, dl));
2959
3
  SDValue TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT,
2960
3
                                MulResult, DAG.getIntPtrConstant(1, dl));
2961
3
  if (isSigned) {
2962
0
    SDValue Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, ShiftAmt);
2963
0
    TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, Tmp1, ISD::SETNE);
2964
3
  } else {
2965
3
    TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, DAG.getConstant(0, dl, VT),
2966
3
                           ISD::SETNE);
2967
3
  }
2968
3
  // MulResult is a node with an illegal type. Because such things are not
2969
3
  // generally permitted during this phase of legalization, ensure that
2970
3
  // nothing is left using the node. The above EXTRACT_ELEMENT nodes should have
2971
3
  // been folded.
2972
3
  assert(MulResult->use_empty() && "Illegally typed node still in use!");
2973
3
2974
3
  SDValue Ops[2] = { BottomHalf, TopHalf } ;
2975
3
  return DAG.getMergeValues(Ops, dl);
2976
3
}
2977
2978
24
static SDValue LowerATOMIC_LOAD_STORE(SDValue Op, SelectionDAG &DAG) {
2979
24
  if (isStrongerThanMonotonic(cast<AtomicSDNode>(Op)->getOrdering()))
2980
0
  // Expand with a fence.
2981
0
  return SDValue();
2982
24
2983
24
  // Monotonic load/stores are legal.
2984
24
  return Op;
2985
24
}
2986
2987
SDValue SparcTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
2988
2
                                                     SelectionDAG &DAG) const {
2989
2
  unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2990
2
  SDLoc dl(Op);
2991
2
  switch (IntNo) {
2992
2
  
default: return SDValue()0
; // Don't custom lower most intrinsics.
2993
2
  case Intrinsic::thread_pointer: {
2994
2
    EVT PtrVT = getPointerTy(DAG.getDataLayout());
2995
2
    return DAG.getRegister(SP::G7, PtrVT);
2996
2
  }
2997
2
  }
2998
2
}
2999
3000
SDValue SparcTargetLowering::
3001
3.06k
LowerOperation(SDValue Op, SelectionDAG &DAG) const {
3002
3.06k
3003
3.06k
  bool hasHardQuad = Subtarget->hasHardQuad();
3004
3.06k
  bool isV9        = Subtarget->isV9();
3005
3.06k
3006
3.06k
  switch (Op.getOpcode()) {
3007
3.06k
  
default: 0
llvm_unreachable0
("Should not custom lower this!");
3008
3.06k
3009
3.06k
  case ISD::RETURNADDR:         return LowerRETURNADDR(Op, DAG, *this,
3010
15
                                                       Subtarget);
3011
3.06k
  case ISD::FRAMEADDR:          return LowerFRAMEADDR(Op, DAG,
3012
10
                                                      Subtarget);
3013
3.06k
  
case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG)16
;
3014
3.06k
  
case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG)84
;
3015
3.06k
  
case ISD::BlockAddress: return LowerBlockAddress(Op, DAG)12
;
3016
3.06k
  
case ISD::ConstantPool: return LowerConstantPool(Op, DAG)76
;
3017
3.06k
  case ISD::FP_TO_SINT:         return LowerFP_TO_SINT(Op, DAG, *this,
3018
54
                                                       hasHardQuad);
3019
3.06k
  case ISD::SINT_TO_FP:         return LowerSINT_TO_FP(Op, DAG, *this,
3020
36
                                                       hasHardQuad);
3021
3.06k
  case ISD::FP_TO_UINT:         return LowerFP_TO_UINT(Op, DAG, *this,
3022
20
                                                       hasHardQuad);
3023
3.06k
  case ISD::UINT_TO_FP:         return LowerUINT_TO_FP(Op, DAG, *this,
3024
32
                                                       hasHardQuad);
3025
3.06k
  case ISD::BR_CC:              return LowerBR_CC(Op, DAG, *this,
3026
73
                                                  hasHardQuad);
3027
3.06k
  case ISD::SELECT_CC:          return LowerSELECT_CC(Op, DAG, *this,
3028
126
                                                      hasHardQuad);
3029
3.06k
  
case ISD::VASTART: return LowerVASTART(Op, DAG, *this)2
;
3030
3.06k
  
case ISD::VAARG: return LowerVAARG(Op, DAG)7
;
3031
3.06k
  case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG,
3032
4
                                                               Subtarget);
3033
3.06k
3034
3.06k
  
case ISD::LOAD: return LowerLOAD(Op, DAG)1.11k
;
3035
3.06k
  
case ISD::STORE: return LowerSTORE(Op, DAG)1.18k
;
3036
3.06k
  case ISD::FADD:               return LowerF128Op(Op, DAG,
3037
5
                                       getLibcallName(RTLIB::ADD_F128), 2);
3038
3.06k
  case ISD::FSUB:               return LowerF128Op(Op, DAG,
3039
2
                                       getLibcallName(RTLIB::SUB_F128), 2);
3040
3.06k
  case ISD::FMUL:               return LowerF128Op(Op, DAG,
3041
2
                                       getLibcallName(RTLIB::MUL_F128), 2);
3042
3.06k
  case ISD::FDIV:               return LowerF128Op(Op, DAG,
3043
2
                                       getLibcallName(RTLIB::DIV_F128), 2);
3044
3.06k
  case ISD::FSQRT:              return LowerF128Op(Op, DAG,
3045
0
                                       getLibcallName(RTLIB::SQRT_F128),1);
3046
3.06k
  case ISD::FABS:
3047
14
  case ISD::FNEG:               return LowerFNEGorFABS(Op, DAG, isV9);
3048
14
  
case ISD::FP_EXTEND: return LowerF128_FPEXTEND(Op, DAG, *this)0
;
3049
14
  case ISD::FP_ROUND:           return LowerF128_FPROUND(Op, DAG, *this);
3050
132
  case ISD::ADDC:
3051
132
  case ISD::ADDE:
3052
132
  case ISD::SUBC:
3053
132
  case ISD::SUBE:               return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
3054
132
  case ISD::UMULO:
3055
3
  case ISD::SMULO:              return LowerUMULO_SMULO(Op, DAG, *this);
3056
24
  case ISD::ATOMIC_LOAD:
3057
24
  case ISD::ATOMIC_STORE:       return LowerATOMIC_LOAD_STORE(Op, DAG);
3058
24
  
case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG)2
;
3059
3.06k
  }
3060
3.06k
}
3061
3062
SDValue SparcTargetLowering::bitcastConstantFPToInt(ConstantFPSDNode *C,
3063
                                                    const SDLoc &DL,
3064
8
                                                    SelectionDAG &DAG) const {
3065
8
  APInt V = C->getValueAPF().bitcastToAPInt();
3066
8
  SDValue Lo = DAG.getConstant(V.zextOrTrunc(32), DL, MVT::i32);
3067
8
  SDValue Hi = DAG.getConstant(V.lshr(32).zextOrTrunc(32), DL, MVT::i32);
3068
8
  if (DAG.getDataLayout().isLittleEndian())
3069
4
    std::swap(Lo, Hi);
3070
8
  return DAG.getBuildVector(MVT::v2i32, DL, {Hi, Lo});
3071
8
}
3072
3073
SDValue SparcTargetLowering::PerformBITCASTCombine(SDNode *N,
3074
180
                                                   DAGCombinerInfo &DCI) const {
3075
180
  SDLoc dl(N);
3076
180
  SDValue Src = N->getOperand(0);
3077
180
3078
180
  if (isa<ConstantFPSDNode>(Src) && 
N->getSimpleValueType(0) == MVT::v2i322
&&
3079
180
      
Src.getSimpleValueType() == MVT::f642
)
3080
2
    return bitcastConstantFPToInt(cast<ConstantFPSDNode>(Src), dl, DCI.DAG);
3081
178
3082
178
  return SDValue();
3083
178
}
3084
3085
SDValue SparcTargetLowering::PerformDAGCombine(SDNode *N,
3086
8.03k
                                               DAGCombinerInfo &DCI) const {
3087
8.03k
  switch (N->getOpcode()) {
3088
8.03k
  default:
3089
7.85k
    break;
3090
8.03k
  case ISD::BITCAST:
3091
180
    return PerformBITCASTCombine(N, DCI);
3092
7.85k
  }
3093
7.85k
  return SDValue();
3094
7.85k
}
3095
3096
MachineBasicBlock *
3097
SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
3098
69
                                                 MachineBasicBlock *BB) const {
3099
69
  switch (MI.getOpcode()) {
3100
69
  
default: 0
llvm_unreachable0
("Unknown SELECT_CC!");
3101
69
  case SP::SELECT_CC_Int_ICC:
3102
54
  case SP::SELECT_CC_FP_ICC:
3103
54
  case SP::SELECT_CC_DFP_ICC:
3104
54
  case SP::SELECT_CC_QFP_ICC:
3105
54
    return expandSelectCC(MI, BB, SP::BCOND);
3106
54
  case SP::SELECT_CC_Int_FCC:
3107
15
  case SP::SELECT_CC_FP_FCC:
3108
15
  case SP::SELECT_CC_DFP_FCC:
3109
15
  case SP::SELECT_CC_QFP_FCC:
3110
15
    return expandSelectCC(MI, BB, SP::FBCOND);
3111
69
  }
3112
69
}
3113
3114
MachineBasicBlock *
3115
SparcTargetLowering::expandSelectCC(MachineInstr &MI, MachineBasicBlock *BB,
3116
69
                                    unsigned BROpcode) const {
3117
69
  const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
3118
69
  DebugLoc dl = MI.getDebugLoc();
3119
69
  unsigned CC = (SPCC::CondCodes)MI.getOperand(3).getImm();
3120
69
3121
69
  // To "insert" a SELECT_CC instruction, we actually have to insert the
3122
69
  // triangle control-flow pattern. The incoming instruction knows the
3123
69
  // destination vreg to set, the condition code register to branch on, the
3124
69
  // true/false values to select between, and the condition code for the branch.
3125
69
  //
3126
69
  // We produce the following control flow:
3127
69
  //     ThisMBB
3128
69
  //     |  \
3129
69
  //     |  IfFalseMBB
3130
69
  //     | /
3131
69
  //    SinkMBB
3132
69
  const BasicBlock *LLVM_BB = BB->getBasicBlock();
3133
69
  MachineFunction::iterator It = ++BB->getIterator();
3134
69
3135
69
  MachineBasicBlock *ThisMBB = BB;
3136
69
  MachineFunction *F = BB->getParent();
3137
69
  MachineBasicBlock *IfFalseMBB = F->CreateMachineBasicBlock(LLVM_BB);
3138
69
  MachineBasicBlock *SinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
3139
69
  F->insert(It, IfFalseMBB);
3140
69
  F->insert(It, SinkMBB);
3141
69
3142
69
  // Transfer the remainder of ThisMBB and its successor edges to SinkMBB.
3143
69
  SinkMBB->splice(SinkMBB->begin(), ThisMBB,
3144
69
                  std::next(MachineBasicBlock::iterator(MI)), ThisMBB->end());
3145
69
  SinkMBB->transferSuccessorsAndUpdatePHIs(ThisMBB);
3146
69
3147
69
  // Set the new successors for ThisMBB.
3148
69
  ThisMBB->addSuccessor(IfFalseMBB);
3149
69
  ThisMBB->addSuccessor(SinkMBB);
3150
69
3151
69
  BuildMI(ThisMBB, dl, TII.get(BROpcode))
3152
69
    .addMBB(SinkMBB)
3153
69
    .addImm(CC);
3154
69
3155
69
  // IfFalseMBB just falls through to SinkMBB.
3156
69
  IfFalseMBB->addSuccessor(SinkMBB);
3157
69
3158
69
  // %Result = phi [ %TrueValue, ThisMBB ], [ %FalseValue, IfFalseMBB ]
3159
69
  BuildMI(*SinkMBB, SinkMBB->begin(), dl, TII.get(SP::PHI),
3160
69
          MI.getOperand(0).getReg())
3161
69
      .addReg(MI.getOperand(1).getReg())
3162
69
      .addMBB(ThisMBB)
3163
69
      .addReg(MI.getOperand(2).getReg())
3164
69
      .addMBB(IfFalseMBB);
3165
69
3166
69
  MI.eraseFromParent(); // The pseudo instruction is gone now.
3167
69
  return SinkMBB;
3168
69
}
3169
3170
//===----------------------------------------------------------------------===//
3171
//                         Sparc Inline Assembly Support
3172
//===----------------------------------------------------------------------===//
3173
3174
/// getConstraintType - Given a constraint letter, return the type of
3175
/// constraint it is for this target.
3176
SparcTargetLowering::ConstraintType
3177
4.66k
SparcTargetLowering::getConstraintType(StringRef Constraint) const {
3178
4.66k
  if (Constraint.size() == 1) {
3179
695
    switch (Constraint[0]) {
3180
695
    
default: break209
;
3181
695
    case 'r':
3182
465
    case 'f':
3183
465
    case 'e':
3184
465
      return C_RegisterClass;
3185
465
    case 'I': // SIMM13
3186
21
      return C_Other;
3187
4.17k
    }
3188
4.17k
  }
3189
4.17k
3190
4.17k
  return TargetLowering::getConstraintType(Constraint);
3191
4.17k
}
3192
3193
TargetLowering::ConstraintWeight SparcTargetLowering::
3194
getSingleConstraintMatchWeight(AsmOperandInfo &info,
3195
219
                               const char *constraint) const {
3196
219
  ConstraintWeight weight = CW_Invalid;
3197
219
  Value *CallOperandVal = info.CallOperandVal;
3198
219
  // If we don't have a value, we can't do a match,
3199
219
  // but allow it at the lowest weight.
3200
219
  if (!CallOperandVal)
3201
90
    return CW_Default;
3202
129
3203
129
  // Look at the constraint type.
3204
129
  switch (*constraint) {
3205
129
  default:
3206
129
    weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
3207
129
    break;
3208
129
  case 'I': // SIMM13
3209
0
    if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
3210
0
      if (isInt<13>(C->getSExtValue()))
3211
0
        weight = CW_Constant;
3212
0
    }
3213
0
    break;
3214
129
  }
3215
129
  return weight;
3216
129
}
3217
3218
/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3219
/// vector.  If it is invalid, don't add anything to Ops.
3220
void SparcTargetLowering::
3221
LowerAsmOperandForConstraint(SDValue Op,
3222
                             std::string &Constraint,
3223
                             std::vector<SDValue> &Ops,
3224
43
                             SelectionDAG &DAG) const {
3225
43
  SDValue Result(nullptr, 0);
3226
43
3227
43
  // Only support length 1 constraints for now.
3228
43
  if (Constraint.length() > 1)
3229
0
    return;
3230
43
3231
43
  char ConstraintLetter = Constraint[0];
3232
43
  switch (ConstraintLetter) {
3233
43
  
default: break32
;
3234
43
  case 'I':
3235
11
    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3236
5
      if (isInt<13>(C->getSExtValue())) {
3237
4
        Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
3238
4
                                       Op.getValueType());
3239
4
        break;
3240
4
      }
3241
1
      return;
3242
1
    }
3243
42
  }
3244
42
3245
42
  if (Result.getNode()) {
3246
4
    Ops.push_back(Result);
3247
4
    return;
3248
4
  }
3249
38
  TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
3250
38
}
3251
3252
std::pair<unsigned, const TargetRegisterClass *>
3253
SparcTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
3254
                                                  StringRef Constraint,
3255
2.14k
                                                  MVT VT) const {
3256
2.14k
  if (Constraint.size() == 1) {
3257
159
    switch (Constraint[0]) {
3258
159
    case 'r':
3259
120
      if (VT == MVT::v2i32)
3260
0
        return std::make_pair(0U, &SP::IntPairRegClass);
3261
120
      else if (Subtarget->is64Bit())
3262
25
        return std::make_pair(0U, &SP::I64RegsRegClass);
3263
95
      else
3264
95
        return std::make_pair(0U, &SP::IntRegsRegClass);
3265
14
    case 'f':
3266
14
      if (VT == MVT::f32 || 
VT == MVT::i3211
)
3267
4
        return std::make_pair(0U, &SP::FPRegsRegClass);
3268
10
      else if (VT == MVT::f64 || 
VT == MVT::i643
)
3269
8
        return std::make_pair(0U, &SP::LowDFPRegsRegClass);
3270
2
      else if (VT == MVT::f128)
3271
2
        return std::make_pair(0U, &SP::LowQFPRegsRegClass);
3272
0
      // This will generate an error message
3273
0
      return std::make_pair(0U, nullptr);
3274
7
    case 'e':
3275
7
      if (VT == MVT::f32 || 
VT == MVT::i326
)
3276
2
        return std::make_pair(0U, &SP::FPRegsRegClass);
3277
5
      else if (VT == MVT::f64 || 
VT == MVT::i642
)
3278
4
        return std::make_pair(0U, &SP::DFPRegsRegClass);
3279
1
      else if (VT == MVT::f128)
3280
1
        return std::make_pair(0U, &SP::QFPRegsRegClass);
3281
0
      // This will generate an error message
3282
0
      return std::make_pair(0U, nullptr);
3283
1.98k
    }
3284
1.98k
  } else if (!Constraint.empty() && Constraint.size() <= 5
3285
1.98k
              && 
Constraint[0] == '{'1.97k
&&
*(Constraint.end()-1) == '}'1.97k
) {
3286
1.97k
    // constraint = '{r<d>}'
3287
1.97k
    // Remove the braces from around the name.
3288
1.97k
    StringRef name(Constraint.data()+1, Constraint.size()-2);
3289
1.97k
    // Handle register aliases:
3290
1.97k
    //       r0-r7   -> g0-g7
3291
1.97k
    //       r8-r15  -> o0-o7
3292
1.97k
    //       r16-r23 -> l0-l7
3293
1.97k
    //       r24-r31 -> i0-i7
3294
1.97k
    uint64_t intVal = 0;
3295
1.97k
    if (name.substr(0, 1).equals("r")
3296
1.97k
        && 
!name.substr(1).getAsInteger(10, intVal)4
&&
intVal <= 314
) {
3297
4
      const char regTypes[] = { 'g', 'o', 'l', 'i' };
3298
4
      char regType = regTypes[intVal/8];
3299
4
      char regIdx = '0' + (intVal % 8);
3300
4
      char tmp[] = { '{', regType, regIdx, '}', 0 };
3301
4
      std::string newConstraint = std::string(tmp);
3302
4
      return TargetLowering::getRegForInlineAsmConstraint(TRI, newConstraint,
3303
4
                                                          VT);
3304
4
    }
3305
1.97k
    if (name.substr(0, 1).equals("f") &&
3306
1.97k
        
!name.substr(1).getAsInteger(10, intVal)843
&&
intVal <= 63843
) {
3307
843
      std::string newConstraint;
3308
843
3309
843
      if (VT == MVT::f32 || 
VT == MVT::Other835
) {
3310
830
        newConstraint = "{f" + utostr(intVal) + "}";
3311
830
      } else 
if (13
VT == MVT::f6413
&&
(intVal % 2 == 0)8
) {
3312
6
        newConstraint = "{d" + utostr(intVal / 2) + "}";
3313
7
      } else if (VT == MVT::f128 && 
(intVal % 4 == 0)5
) {
3314
3
        newConstraint = "{q" + utostr(intVal / 4) + "}";
3315
4
      } else {
3316
4
        return std::make_pair(0U, nullptr);
3317
4
      }
3318
839
      return TargetLowering::getRegForInlineAsmConstraint(TRI, newConstraint,
3319
839
                                                          VT);
3320
839
    }
3321
1.97k
  }
3322
1.15k
3323
1.15k
  return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
3324
1.15k
}
3325
3326
bool
3327
121
SparcTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
3328
121
  // The Sparc target isn't yet aware of offsets.
3329
121
  return false;
3330
121
}
3331
3332
void SparcTargetLowering::ReplaceNodeResults(SDNode *N,
3333
                                             SmallVectorImpl<SDValue>& Results,
3334
57
                                             SelectionDAG &DAG) const {
3335
57
3336
57
  SDLoc dl(N);
3337
57
3338
57
  RTLIB::Libcall libCall = RTLIB::UNKNOWN_LIBCALL;
3339
57
3340
57
  switch (N->getOpcode()) {
3341
57
  default:
3342
0
    llvm_unreachable("Do not know how to custom type legalize this operation!");
3343
57
3344
57
  case ISD::FP_TO_SINT:
3345
24
  case ISD::FP_TO_UINT:
3346
24
    // Custom lower only if it involves f128 or i64.
3347
24
    if (N->getOperand(0).getValueType() != MVT::f128
3348
24
        || 
N->getValueType(0) != MVT::i648
)
3349
16
      return;
3350
8
    libCall = ((N->getOpcode() == ISD::FP_TO_SINT)
3351
8
               ? 
RTLIB::FPTOSINT_F128_I644
3352
8
               : 
RTLIB::FPTOUINT_F128_I644
);
3353
8
3354
8
    Results.push_back(LowerF128Op(SDValue(N, 0),
3355
8
                                  DAG,
3356
8
                                  getLibcallName(libCall),
3357
8
                                  1));
3358
8
    return;
3359
8
  case ISD::READCYCLECOUNTER: {
3360
1
    assert(Subtarget->hasLeonCycleCounter());
3361
1
    SDValue Lo = DAG.getCopyFromReg(N->getOperand(0), dl, SP::ASR23, MVT::i32);
3362
1
    SDValue Hi = DAG.getCopyFromReg(Lo, dl, SP::G0, MVT::i32);
3363
1
    SDValue Ops[] = { Lo, Hi };
3364
1
    SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops);
3365
1
    Results.push_back(Pair);
3366
1
    Results.push_back(N->getOperand(0));
3367
1
    return;
3368
8
  }
3369
8
  case ISD::SINT_TO_FP:
3370
0
  case ISD::UINT_TO_FP:
3371
0
    // Custom lower only if it involves f128 or i64.
3372
0
    if (N->getValueType(0) != MVT::f128
3373
0
        || N->getOperand(0).getValueType() != MVT::i64)
3374
0
      return;
3375
0
3376
0
    libCall = ((N->getOpcode() == ISD::SINT_TO_FP)
3377
0
               ? RTLIB::SINTTOFP_I64_F128
3378
0
               : RTLIB::UINTTOFP_I64_F128);
3379
0
3380
0
    Results.push_back(LowerF128Op(SDValue(N, 0),
3381
0
                                  DAG,
3382
0
                                  getLibcallName(libCall),
3383
0
                                  1));
3384
0
    return;
3385
32
  case ISD::LOAD: {
3386
32
    LoadSDNode *Ld = cast<LoadSDNode>(N);
3387
32
    // Custom handling only for i64: turn i64 load into a v2i32 load,
3388
32
    // and a bitcast.
3389
32
    if (Ld->getValueType(0) != MVT::i64 || Ld->getMemoryVT() != MVT::i64)
3390
3
      return;
3391
29
3392
29
    SDLoc dl(N);
3393
29
    SDValue LoadRes = DAG.getExtLoad(
3394
29
        Ld->getExtensionType(), dl, MVT::v2i32, Ld->getChain(),
3395
29
        Ld->getBasePtr(), Ld->getPointerInfo(), MVT::v2i32, Ld->getAlignment(),
3396
29
        Ld->getMemOperand()->getFlags(), Ld->getAAInfo());
3397
29
3398
29
    SDValue Res = DAG.getNode(ISD::BITCAST, dl, MVT::i64, LoadRes);
3399
29
    Results.push_back(Res);
3400
29
    Results.push_back(LoadRes.getValue(1));
3401
29
    return;
3402
29
  }
3403
57
  }
3404
57
}
3405
3406
// Override to enable LOAD_STACK_GUARD lowering on Linux.
3407
12
bool SparcTargetLowering::useLoadStackGuardNode() const {
3408
12
  if (!Subtarget->isTargetLinux())
3409
6
    return TargetLowering::useLoadStackGuardNode();
3410
6
  return true;
3411
6
}
3412
3413
// Override to disable global variable loading on Linux.
3414
4
void SparcTargetLowering::insertSSPDeclarations(Module &M) const {
3415
4
  if (!Subtarget->isTargetLinux())
3416
2
    return TargetLowering::insertSSPDeclarations(M);
3417
4
}