Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/Sparc/SparcISelLowering.h
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//===-- SparcISelLowering.h - Sparc DAG Lowering Interface ------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that Sparc uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_SPARC_SPARCISELLOWERING_H
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#define LLVM_LIB_TARGET_SPARC_SPARCISELLOWERING_H
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#include "Sparc.h"
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#include "llvm/CodeGen/TargetLowering.h"
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namespace llvm {
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  class SparcSubtarget;
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  namespace SPISD {
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    enum NodeType : unsigned {
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      FIRST_NUMBER = ISD::BUILTIN_OP_END,
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      CMPICC,      // Compare two GPR operands, set icc+xcc.
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      CMPFCC,      // Compare two FP operands, set fcc.
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      BRICC,       // Branch to dest on icc condition
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      BRXCC,       // Branch to dest on xcc condition (64-bit only).
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      BRFCC,       // Branch to dest on fcc condition
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      SELECT_ICC,  // Select between two values using the current ICC flags.
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      SELECT_XCC,  // Select between two values using the current XCC flags.
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      SELECT_FCC,  // Select between two values using the current FCC flags.
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      Hi, Lo,      // Hi/Lo operations, typically on a global address.
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      FTOI,        // FP to Int within a FP register.
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      ITOF,        // Int to FP within a FP register.
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      FTOX,        // FP to Int64 within a FP register.
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      XTOF,        // Int64 to FP within a FP register.
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      CALL,        // A call instruction.
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      RET_FLAG,    // Return with a flag operand.
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      GLOBAL_BASE_REG, // Global base reg for PIC.
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      FLUSHW,      // FLUSH register windows to stack.
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      TLS_ADD,     // For Thread Local Storage (TLS).
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      TLS_LD,
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      TLS_CALL
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    };
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  }
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  class SparcTargetLowering : public TargetLowering {
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    const SparcSubtarget *Subtarget;
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  public:
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    SparcTargetLowering(const TargetMachine &TM, const SparcSubtarget &STI);
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    SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
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    bool useSoftFloat() const override;
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    /// computeKnownBitsForTargetNode - Determine which of the bits specified
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    /// in Mask are known to be either zero or one and return them in the
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    /// KnownZero/KnownOne bitsets.
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    void computeKnownBitsForTargetNode(const SDValue Op,
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                                       KnownBits &Known,
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                                       const APInt &DemandedElts,
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                                       const SelectionDAG &DAG,
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                                       unsigned Depth = 0) const override;
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    MachineBasicBlock *
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    EmitInstrWithCustomInserter(MachineInstr &MI,
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                                MachineBasicBlock *MBB) const override;
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    const char *getTargetNodeName(unsigned Opcode) const override;
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    ConstraintType getConstraintType(StringRef Constraint) const override;
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    ConstraintWeight
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    getSingleConstraintMatchWeight(AsmOperandInfo &info,
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                                   const char *constraint) const override;
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    void LowerAsmOperandForConstraint(SDValue Op,
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                                      std::string &Constraint,
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                                      std::vector<SDValue> &Ops,
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                                      SelectionDAG &DAG) const override;
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    unsigned
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    getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
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      if (ConstraintCode == "o")
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        return InlineAsm::Constraint_o;
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      return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
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    }
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    std::pair<unsigned, const TargetRegisterClass *>
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    getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
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                                 StringRef Constraint, MVT VT) const override;
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    bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
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    MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
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      return MVT::i32;
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    }
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    unsigned getRegisterByName(const char* RegName, EVT VT,
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                               SelectionDAG &DAG) const override;
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    /// If a physical register, this returns the register that receives the
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    /// exception address on entry to an EH pad.
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    unsigned
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    getExceptionPointerRegister(const Constant *PersonalityFn) const override {
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      return SP::I0;
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    }
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    /// If a physical register, this returns the register that receives the
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    /// exception typeid on entry to a landing pad.
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    unsigned
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    getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
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      return SP::I1;
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    }
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    /// Override to support customized stack guard loading.
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    bool useLoadStackGuardNode() const override;
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    void insertSSPDeclarations(Module &M) const override;
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    /// getSetCCResultType - Return the ISD::SETCC ValueType
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    EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
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                           EVT VT) const override;
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    SDValue
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    LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
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                         const SmallVectorImpl<ISD::InputArg> &Ins,
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                         const SDLoc &dl, SelectionDAG &DAG,
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                         SmallVectorImpl<SDValue> &InVals) const override;
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    SDValue LowerFormalArguments_32(SDValue Chain, CallingConv::ID CallConv,
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                                    bool isVarArg,
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                                    const SmallVectorImpl<ISD::InputArg> &Ins,
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                                    const SDLoc &dl, SelectionDAG &DAG,
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                                    SmallVectorImpl<SDValue> &InVals) const;
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    SDValue LowerFormalArguments_64(SDValue Chain, CallingConv::ID CallConv,
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                                    bool isVarArg,
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                                    const SmallVectorImpl<ISD::InputArg> &Ins,
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                                    const SDLoc &dl, SelectionDAG &DAG,
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                                    SmallVectorImpl<SDValue> &InVals) const;
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    SDValue
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      LowerCall(TargetLowering::CallLoweringInfo &CLI,
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                SmallVectorImpl<SDValue> &InVals) const override;
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    SDValue LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
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                         SmallVectorImpl<SDValue> &InVals) const;
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    SDValue LowerCall_64(TargetLowering::CallLoweringInfo &CLI,
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                         SmallVectorImpl<SDValue> &InVals) const;
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    SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
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                        const SmallVectorImpl<ISD::OutputArg> &Outs,
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                        const SmallVectorImpl<SDValue> &OutVals,
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                        const SDLoc &dl, SelectionDAG &DAG) const override;
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    SDValue LowerReturn_32(SDValue Chain, CallingConv::ID CallConv,
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                           bool IsVarArg,
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                           const SmallVectorImpl<ISD::OutputArg> &Outs,
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                           const SmallVectorImpl<SDValue> &OutVals,
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                           const SDLoc &DL, SelectionDAG &DAG) const;
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    SDValue LowerReturn_64(SDValue Chain, CallingConv::ID CallConv,
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                           bool IsVarArg,
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                           const SmallVectorImpl<ISD::OutputArg> &Outs,
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                           const SmallVectorImpl<SDValue> &OutVals,
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                           const SDLoc &DL, SelectionDAG &DAG) const;
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    SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
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    SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
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    SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
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    SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
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    SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const;
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    SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF,
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                         SelectionDAG &DAG) const;
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    SDValue makeAddress(SDValue Op, SelectionDAG &DAG) const;
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    SDValue LowerF128_LibCallArg(SDValue Chain, ArgListTy &Args, SDValue Arg,
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                                 const SDLoc &DL, SelectionDAG &DAG) const;
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    SDValue LowerF128Op(SDValue Op, SelectionDAG &DAG,
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                        const char *LibFuncName,
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                        unsigned numArgs) const;
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    SDValue LowerF128Compare(SDValue LHS, SDValue RHS, unsigned &SPCC,
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                             const SDLoc &DL, SelectionDAG &DAG) const;
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    SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
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    SDValue PerformBITCASTCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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    SDValue bitcastConstantFPToInt(ConstantFPSDNode *C, const SDLoc &DL,
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                                   SelectionDAG &DAG) const;
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    SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
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    bool ShouldShrinkFPConstant(EVT VT) const override {
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      // Do not shrink FP constpool if VT == MVT::f128.
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      // (ldd, call _Q_fdtoq) is more expensive than two ldds.
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      return VT != MVT::f128;
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    }
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    bool shouldInsertFencesForAtomic(const Instruction *I) const override {
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      // FIXME: We insert fences for each atomics and generate
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      // sub-optimal code for PSO/TSO. (Approximately nobody uses any
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      // mode but TSO, which makes this even more silly)
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      return true;
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    }
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    AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
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    void ReplaceNodeResults(SDNode *N,
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                            SmallVectorImpl<SDValue>& Results,
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                            SelectionDAG &DAG) const override;
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    MachineBasicBlock *expandSelectCC(MachineInstr &MI, MachineBasicBlock *BB,
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                                      unsigned BROpcode) const;
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  };
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} // end namespace llvm
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#endif    // SPARC_ISELLOWERING_H