Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/Sparc/SparcTargetMachine.cpp
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//===-- SparcTargetMachine.cpp - Define TargetMachine for Sparc -----------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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#include "SparcTargetMachine.h"
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#include "LeonPasses.h"
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#include "Sparc.h"
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#include "SparcTargetObjectFile.h"
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#include "TargetInfo/SparcTargetInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/IR/LegacyPassManager.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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extern "C" void LLVMInitializeSparcTarget() {
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  // Register the target.
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  RegisterTargetMachine<SparcV8TargetMachine> X(getTheSparcTarget());
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  RegisterTargetMachine<SparcV9TargetMachine> Y(getTheSparcV9Target());
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  RegisterTargetMachine<SparcelTargetMachine> Z(getTheSparcelTarget());
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}
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static std::string computeDataLayout(const Triple &T, bool is64Bit) {
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  // Sparc is typically big endian, but some are little.
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  std::string Ret = T.getArch() == Triple::sparcel ? 
"e"5
:
"E"225
;
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  Ret += "-m:e";
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  // Some ABIs have 32bit pointers.
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  if (!is64Bit)
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    Ret += "-p:32:32";
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  // Alignments for 64 bit integers.
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  Ret += "-i64:64";
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  // On SparcV9 128 floats are aligned to 128 bits, on others only to 64.
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  // On SparcV9 registers can hold 64 or 32 bits, on others only 32.
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  if (is64Bit)
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    Ret += "-n32:64";
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  else
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    Ret += "-f128:64-n32";
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  if (is64Bit)
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    Ret += "-S128";
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  else
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    Ret += "-S64";
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  return Ret;
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}
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static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
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  if (!RM.hasValue())
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    return Reloc::Static;
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  return *RM;
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}
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// Code models. Some only make sense for 64-bit code.
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//
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// SunCC  Reloc   CodeModel  Constraints
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// abs32  Static  Small      text+data+bss linked below 2^32 bytes
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// abs44  Static  Medium     text+data+bss linked below 2^44 bytes
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// abs64  Static  Large      text smaller than 2^31 bytes
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// pic13  PIC_    Small      GOT < 2^13 bytes
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// pic32  PIC_    Medium     GOT < 2^32 bytes
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//
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// All code models require that the text segment is smaller than 2GB.
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static CodeModel::Model
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getEffectiveSparcCodeModel(Optional<CodeModel::Model> CM, Reloc::Model RM,
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                           bool Is64Bit, bool JIT) {
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  if (CM) {
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    if (*CM == CodeModel::Tiny)
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      report_fatal_error("Target does not support the tiny CodeModel", false);
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    if (*CM == CodeModel::Kernel)
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      report_fatal_error("Target does not support the kernel CodeModel", false);
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    return *CM;
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  }
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  if (Is64Bit) {
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    if (JIT)
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      return CodeModel::Large;
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    return RM == Reloc::PIC_ ? 
CodeModel::Small15
:
CodeModel::Medium41
;
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  }
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  return CodeModel::Small;
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}
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/// Create an ILP32 architecture model
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SparcTargetMachine::SparcTargetMachine(
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    const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
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    const TargetOptions &Options, Optional<Reloc::Model> RM,
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    Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT, bool is64bit)
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    : LLVMTargetMachine(T, computeDataLayout(TT, is64bit), TT, CPU, FS, Options,
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                        getEffectiveRelocModel(RM),
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                        getEffectiveSparcCodeModel(
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                            CM, getEffectiveRelocModel(RM), is64bit, JIT),
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                        OL),
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      TLOF(make_unique<SparcELFTargetObjectFile>()),
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      Subtarget(TT, CPU, FS, *this, is64bit), is64Bit(is64bit) {
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  initAsmInfo();
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}
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SparcTargetMachine::~SparcTargetMachine() {}
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const SparcSubtarget *
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SparcTargetMachine::getSubtargetImpl(const Function &F) const {
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  Attribute CPUAttr = F.getFnAttribute("target-cpu");
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  Attribute FSAttr = F.getFnAttribute("target-features");
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  std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
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                        ? 
CPUAttr.getValueAsString().str()497
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                        : 
TargetCPU8.64k
;
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  std::string FS = !FSAttr.hasAttribute(Attribute::None)
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                       ? 
FSAttr.getValueAsString().str()2.80k
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                       : 
TargetFS6.33k
;
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  // FIXME: This is related to the code below to reset the target options,
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  // we need to know whether or not the soft float flag is set on the
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  // function, so we can enable it as a subtarget feature.
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  bool softFloat =
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      F.hasFnAttribute("use-soft-float") &&
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F.getFnAttribute("use-soft-float").getValueAsString() == "true"14
;
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  if (softFloat)
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    FS += FS.empty() ? "+soft-float" : ",+soft-float";
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  auto &I = SubtargetMap[CPU + FS];
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  if (!I) {
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    // This needs to be done before we create a new subtarget since any
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    // creation will depend on the TM and the code generation flags on the
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    // function that reside in TargetOptions.
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    resetTargetOptions(F);
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    I = llvm::make_unique<SparcSubtarget>(TargetTriple, CPU, FS, *this,
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                                          this->is64Bit);
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  }
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  return I.get();
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}
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namespace {
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/// Sparc Code Generator Pass Configuration Options.
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class SparcPassConfig : public TargetPassConfig {
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public:
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  SparcPassConfig(SparcTargetMachine &TM, PassManagerBase &PM)
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    : TargetPassConfig(TM, PM) {}
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  SparcTargetMachine &getSparcTargetMachine() const {
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    return getTM<SparcTargetMachine>();
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  }
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  void addIRPasses() override;
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  bool addInstSelector() override;
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  void addPreEmitPass() override;
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};
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} // namespace
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TargetPassConfig *SparcTargetMachine::createPassConfig(PassManagerBase &PM) {
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  return new SparcPassConfig(*this, PM);
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}
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void SparcPassConfig::addIRPasses() {
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  addPass(createAtomicExpandPass());
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  TargetPassConfig::addIRPasses();
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}
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bool SparcPassConfig::addInstSelector() {
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  addPass(createSparcISelDag(getSparcTargetMachine()));
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  return false;
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}
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void SparcPassConfig::addPreEmitPass(){
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  addPass(createSparcDelaySlotFillerPass());
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  if (this->getSparcTargetMachine().getSubtargetImpl()->insertNOPLoad())
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  {
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    addPass(new InsertNOPLoad());
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  }
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  if (this->getSparcTargetMachine().getSubtargetImpl()->detectRoundChange()) {
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    addPass(new DetectRoundChange());
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  }
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  if (this->getSparcTargetMachine().getSubtargetImpl()->fixAllFDIVSQRT())
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  {
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    addPass(new FixAllFDIVSQRT());
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  }
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}
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void SparcV8TargetMachine::anchor() { }
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SparcV8TargetMachine::SparcV8TargetMachine(const Target &T, const Triple &TT,
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                                           StringRef CPU, StringRef FS,
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                                           const TargetOptions &Options,
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                                           Optional<Reloc::Model> RM,
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                                           Optional<CodeModel::Model> CM,
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                                           CodeGenOpt::Level OL, bool JIT)
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    : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
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void SparcV9TargetMachine::anchor() { }
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SparcV9TargetMachine::SparcV9TargetMachine(const Target &T, const Triple &TT,
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                                           StringRef CPU, StringRef FS,
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                                           const TargetOptions &Options,
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                                           Optional<Reloc::Model> RM,
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                                           Optional<CodeModel::Model> CM,
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                                           CodeGenOpt::Level OL, bool JIT)
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    : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
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void SparcelTargetMachine::anchor() {}
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SparcelTargetMachine::SparcelTargetMachine(const Target &T, const Triple &TT,
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                                           StringRef CPU, StringRef FS,
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                                           const TargetOptions &Options,
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                                           Optional<Reloc::Model> RM,
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                                           Optional<CodeModel::Model> CM,
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                                           CodeGenOpt::Level OL, bool JIT)
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    : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}