Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
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//===-- SystemZAsmParser.cpp - Parse SystemZ assembly instructions --------===//
2
//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
8
9
#include "MCTargetDesc/SystemZInstPrinter.h"
10
#include "MCTargetDesc/SystemZMCTargetDesc.h"
11
#include "TargetInfo/SystemZTargetInfo.h"
12
#include "llvm/ADT/STLExtras.h"
13
#include "llvm/ADT/SmallVector.h"
14
#include "llvm/ADT/StringRef.h"
15
#include "llvm/MC/MCContext.h"
16
#include "llvm/MC/MCExpr.h"
17
#include "llvm/MC/MCInst.h"
18
#include "llvm/MC/MCInstBuilder.h"
19
#include "llvm/MC/MCParser/MCAsmLexer.h"
20
#include "llvm/MC/MCParser/MCAsmParser.h"
21
#include "llvm/MC/MCParser/MCAsmParserExtension.h"
22
#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
23
#include "llvm/MC/MCParser/MCTargetAsmParser.h"
24
#include "llvm/MC/MCStreamer.h"
25
#include "llvm/MC/MCSubtargetInfo.h"
26
#include "llvm/Support/Casting.h"
27
#include "llvm/Support/ErrorHandling.h"
28
#include "llvm/Support/SMLoc.h"
29
#include "llvm/Support/TargetRegistry.h"
30
#include <algorithm>
31
#include <cassert>
32
#include <cstddef>
33
#include <cstdint>
34
#include <iterator>
35
#include <memory>
36
#include <string>
37
38
using namespace llvm;
39
40
// Return true if Expr is in the range [MinValue, MaxValue].
41
23.9k
static bool inRange(const MCExpr *Expr, int64_t MinValue, int64_t MaxValue) {
42
23.9k
  if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
43
23.8k
    int64_t Value = CE->getValue();
44
23.8k
    return Value >= MinValue && 
Value <= MaxValue21.5k
;
45
23.8k
  }
46
24
  return false;
47
24
}
48
49
namespace {
50
51
enum RegisterKind {
52
  GR32Reg,
53
  GRH32Reg,
54
  GR64Reg,
55
  GR128Reg,
56
  ADDR32Reg,
57
  ADDR64Reg,
58
  FP32Reg,
59
  FP64Reg,
60
  FP128Reg,
61
  VR32Reg,
62
  VR64Reg,
63
  VR128Reg,
64
  AR32Reg,
65
  CR64Reg,
66
};
67
68
enum MemoryKind {
69
  BDMem,
70
  BDXMem,
71
  BDLMem,
72
  BDRMem,
73
  BDVMem
74
};
75
76
class SystemZOperand : public MCParsedAsmOperand {
77
private:
78
  enum OperandKind {
79
    KindInvalid,
80
    KindToken,
81
    KindReg,
82
    KindImm,
83
    KindImmTLS,
84
    KindMem
85
  };
86
87
  OperandKind Kind;
88
  SMLoc StartLoc, EndLoc;
89
90
  // A string of length Length, starting at Data.
91
  struct TokenOp {
92
    const char *Data;
93
    unsigned Length;
94
  };
95
96
  // LLVM register Num, which has kind Kind.  In some ways it might be
97
  // easier for this class to have a register bank (general, floating-point
98
  // or access) and a raw register number (0-15).  This would postpone the
99
  // interpretation of the operand to the add*() methods and avoid the need
100
  // for context-dependent parsing.  However, we do things the current way
101
  // because of the virtual getReg() method, which needs to distinguish
102
  // between (say) %r0 used as a single register and %r0 used as a pair.
103
  // Context-dependent parsing can also give us slightly better error
104
  // messages when invalid pairs like %r1 are used.
105
  struct RegOp {
106
    RegisterKind Kind;
107
    unsigned Num;
108
  };
109
110
  // Base + Disp + Index, where Base and Index are LLVM registers or 0.
111
  // MemKind says what type of memory this is and RegKind says what type
112
  // the base register has (ADDR32Reg or ADDR64Reg).  Length is the operand
113
  // length for D(L,B)-style operands, otherwise it is null.
114
  struct MemOp {
115
    unsigned Base : 12;
116
    unsigned Index : 12;
117
    unsigned MemKind : 4;
118
    unsigned RegKind : 4;
119
    const MCExpr *Disp;
120
    union {
121
      const MCExpr *Imm;
122
      unsigned Reg;
123
    } Length;
124
  };
125
126
  // Imm is an immediate operand, and Sym is an optional TLS symbol
127
  // for use with a __tls_get_offset marker relocation.
128
  struct ImmTLSOp {
129
    const MCExpr *Imm;
130
    const MCExpr *Sym;
131
  };
132
133
  union {
134
    TokenOp Token;
135
    RegOp Reg;
136
    const MCExpr *Imm;
137
    ImmTLSOp ImmTLS;
138
    MemOp Mem;
139
  };
140
141
17.4k
  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
142
17.4k
    // Add as immediates when possible.  Null MCExpr = 0.
143
17.4k
    if (!Expr)
144
0
      Inst.addOperand(MCOperand::createImm(0));
145
17.4k
    else if (auto *CE = dyn_cast<MCConstantExpr>(Expr))
146
16.3k
      Inst.addOperand(MCOperand::createImm(CE->getValue()));
147
1.13k
    else
148
1.13k
      Inst.addOperand(MCOperand::createExpr(Expr));
149
17.4k
  }
150
151
public:
152
  SystemZOperand(OperandKind kind, SMLoc startLoc, SMLoc endLoc)
153
99.8k
      : Kind(kind), StartLoc(startLoc), EndLoc(endLoc) {}
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  // Create particular kinds of operand.
156
  static std::unique_ptr<SystemZOperand> createInvalid(SMLoc StartLoc,
157
151
                                                       SMLoc EndLoc) {
158
151
    return make_unique<SystemZOperand>(KindInvalid, StartLoc, EndLoc);
159
151
  }
160
161
26.8k
  static std::unique_ptr<SystemZOperand> createToken(StringRef Str, SMLoc Loc) {
162
26.8k
    auto Op = make_unique<SystemZOperand>(KindToken, Loc, Loc);
163
26.8k
    Op->Token.Data = Str.data();
164
26.8k
    Op->Token.Length = Str.size();
165
26.8k
    return Op;
166
26.8k
  }
167
168
  static std::unique_ptr<SystemZOperand>
169
46.9k
  createReg(RegisterKind Kind, unsigned Num, SMLoc StartLoc, SMLoc EndLoc) {
170
46.9k
    auto Op = make_unique<SystemZOperand>(KindReg, StartLoc, EndLoc);
171
46.9k
    Op->Reg.Kind = Kind;
172
46.9k
    Op->Reg.Num = Num;
173
46.9k
    return Op;
174
46.9k
  }
175
176
  static std::unique_ptr<SystemZOperand>
177
15.1k
  createImm(const MCExpr *Expr, SMLoc StartLoc, SMLoc EndLoc) {
178
15.1k
    auto Op = make_unique<SystemZOperand>(KindImm, StartLoc, EndLoc);
179
15.1k
    Op->Imm = Expr;
180
15.1k
    return Op;
181
15.1k
  }
182
183
  static std::unique_ptr<SystemZOperand>
184
  createMem(MemoryKind MemKind, RegisterKind RegKind, unsigned Base,
185
            const MCExpr *Disp, unsigned Index, const MCExpr *LengthImm,
186
10.7k
            unsigned LengthReg, SMLoc StartLoc, SMLoc EndLoc) {
187
10.7k
    auto Op = make_unique<SystemZOperand>(KindMem, StartLoc, EndLoc);
188
10.7k
    Op->Mem.MemKind = MemKind;
189
10.7k
    Op->Mem.RegKind = RegKind;
190
10.7k
    Op->Mem.Base = Base;
191
10.7k
    Op->Mem.Index = Index;
192
10.7k
    Op->Mem.Disp = Disp;
193
10.7k
    if (MemKind == BDLMem)
194
1.41k
      Op->Mem.Length.Imm = LengthImm;
195
10.7k
    if (MemKind == BDRMem)
196
81
      Op->Mem.Length.Reg = LengthReg;
197
10.7k
    return Op;
198
10.7k
  }
199
200
  static std::unique_ptr<SystemZOperand>
201
  createImmTLS(const MCExpr *Imm, const MCExpr *Sym,
202
45
               SMLoc StartLoc, SMLoc EndLoc) {
203
45
    auto Op = make_unique<SystemZOperand>(KindImmTLS, StartLoc, EndLoc);
204
45
    Op->ImmTLS.Imm = Imm;
205
45
    Op->ImmTLS.Sym = Sym;
206
45
    return Op;
207
45
  }
208
209
  // Token operands
210
71.7k
  bool isToken() const override {
211
71.7k
    return Kind == KindToken;
212
71.7k
  }
213
24.8k
  StringRef getToken() const {
214
24.8k
    assert(Kind == KindToken && "Not a token");
215
24.8k
    return StringRef(Token.Data, Token.Length);
216
24.8k
  }
217
218
  // Register operands.
219
4.88k
  bool isReg() const override {
220
4.88k
    return Kind == KindReg;
221
4.88k
  }
222
47.6k
  bool isReg(RegisterKind RegKind) const {
223
47.6k
    return Kind == KindReg && 
Reg.Kind == RegKind47.6k
;
224
47.6k
  }
225
34.8k
  unsigned getReg() const override {
226
34.8k
    assert(Kind == KindReg && "Not a register");
227
34.8k
    return Reg.Num;
228
34.8k
  }
229
230
  // Immediate operands.
231
1.13k
  bool isImm() const override {
232
1.13k
    return Kind == KindImm;
233
1.13k
  }
234
12.6k
  bool isImm(int64_t MinValue, int64_t MaxValue) const {
235
12.6k
    return Kind == KindImm && inRange(Imm, MinValue, MaxValue);
236
12.6k
  }
237
9.82k
  const MCExpr *getImm() const {
238
9.82k
    assert(Kind == KindImm && "Not an immediate");
239
9.82k
    return Imm;
240
9.82k
  }
241
242
  // Immediate operands with optional TLS symbol.
243
45
  bool isImmTLS() const {
244
45
    return Kind == KindImmTLS;
245
45
  }
246
247
0
  const ImmTLSOp getImmTLS() const {
248
0
    assert(Kind == KindImmTLS && "Not a TLS immediate");
249
0
    return ImmTLS;
250
0
  }
251
252
  // Memory operands.
253
0
  bool isMem() const override {
254
0
    return Kind == KindMem;
255
0
  }
256
10.3k
  bool isMem(MemoryKind MemKind) const {
257
10.3k
    return (Kind == KindMem &&
258
10.3k
            
(10.2k
Mem.MemKind == MemKind10.2k
||
259
10.2k
             // A BDMem can be treated as a BDXMem in which the index
260
10.2k
             // register field is 0.
261
10.2k
             
(5
Mem.MemKind == BDMem5
&&
MemKind == BDXMem0
)));
262
10.3k
  }
263
10.2k
  bool isMem(MemoryKind MemKind, RegisterKind RegKind) const {
264
10.2k
    return isMem(MemKind) && Mem.RegKind == RegKind;
265
10.2k
  }
266
6.66k
  bool isMemDisp12(MemoryKind MemKind, RegisterKind RegKind) const {
267
6.66k
    return isMem(MemKind, RegKind) && inRange(Mem.Disp, 0, 0xfff);
268
6.66k
  }
269
3.59k
  bool isMemDisp20(MemoryKind MemKind, RegisterKind RegKind) const {
270
3.59k
    return isMem(MemKind, RegKind) && inRange(Mem.Disp, -524288, 524287);
271
3.59k
  }
272
512
  bool isMemDisp12Len4(RegisterKind RegKind) const {
273
512
    return isMemDisp12(BDLMem, RegKind) && 
inRange(Mem.Length.Imm, 1, 0x10)432
;
274
512
  }
275
656
  bool isMemDisp12Len8(RegisterKind RegKind) const {
276
656
    return isMemDisp12(BDLMem, RegKind) && 
inRange(Mem.Length.Imm, 1, 0x100)556
;
277
656
  }
278
279
0
  const MemOp& getMem() const {
280
0
    assert(Kind == KindMem && "Not a Mem operand");
281
0
    return Mem;
282
0
  }
283
284
  // Override MCParsedAsmOperand.
285
4.83k
  SMLoc getStartLoc() const override { return StartLoc; }
286
0
  SMLoc getEndLoc() const override { return EndLoc; }
287
  void print(raw_ostream &OS) const override;
288
289
  /// getLocRange - Get the range between the first and last token of this
290
  /// operand.
291
95
  SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
292
293
  // Used by the TableGen code to add particular types of operand
294
  // to an instruction.
295
34.8k
  void addRegOperands(MCInst &Inst, unsigned N) const {
296
34.8k
    assert(N == 1 && "Invalid number of operands");
297
34.8k
    Inst.addOperand(MCOperand::createReg(getReg()));
298
34.8k
  }
299
9.82k
  void addImmOperands(MCInst &Inst, unsigned N) const {
300
9.82k
    assert(N == 1 && "Invalid number of operands");
301
9.82k
    addExpr(Inst, getImm());
302
9.82k
  }
303
3.25k
  void addBDAddrOperands(MCInst &Inst, unsigned N) const {
304
3.25k
    assert(N == 2 && "Invalid number of operands");
305
3.25k
    assert(isMem(BDMem) && "Invalid operand type");
306
3.25k
    Inst.addOperand(MCOperand::createReg(Mem.Base));
307
3.25k
    addExpr(Inst, Mem.Disp);
308
3.25k
  }
309
2.98k
  void addBDXAddrOperands(MCInst &Inst, unsigned N) const {
310
2.98k
    assert(N == 3 && "Invalid number of operands");
311
2.98k
    assert(isMem(BDXMem) && "Invalid operand type");
312
2.98k
    Inst.addOperand(MCOperand::createReg(Mem.Base));
313
2.98k
    addExpr(Inst, Mem.Disp);
314
2.98k
    Inst.addOperand(MCOperand::createReg(Mem.Index));
315
2.98k
  }
316
620
  void addBDLAddrOperands(MCInst &Inst, unsigned N) const {
317
620
    assert(N == 3 && "Invalid number of operands");
318
620
    assert(isMem(BDLMem) && "Invalid operand type");
319
620
    Inst.addOperand(MCOperand::createReg(Mem.Base));
320
620
    addExpr(Inst, Mem.Disp);
321
620
    addExpr(Inst, Mem.Length.Imm);
322
620
  }
323
39
  void addBDRAddrOperands(MCInst &Inst, unsigned N) const {
324
39
    assert(N == 3 && "Invalid number of operands");
325
39
    assert(isMem(BDRMem) && "Invalid operand type");
326
39
    Inst.addOperand(MCOperand::createReg(Mem.Base));
327
39
    addExpr(Inst, Mem.Disp);
328
39
    Inst.addOperand(MCOperand::createReg(Mem.Length.Reg));
329
39
  }
330
80
  void addBDVAddrOperands(MCInst &Inst, unsigned N) const {
331
80
    assert(N == 3 && "Invalid number of operands");
332
80
    assert(isMem(BDVMem) && "Invalid operand type");
333
80
    Inst.addOperand(MCOperand::createReg(Mem.Base));
334
80
    addExpr(Inst, Mem.Disp);
335
80
    Inst.addOperand(MCOperand::createReg(Mem.Index));
336
80
  }
337
45
  void addImmTLSOperands(MCInst &Inst, unsigned N) const {
338
45
    assert(N == 2 && "Invalid number of operands");
339
45
    assert(Kind == KindImmTLS && "Invalid operand type");
340
45
    addExpr(Inst, ImmTLS.Imm);
341
45
    if (ImmTLS.Sym)
342
8
      addExpr(Inst, ImmTLS.Sym);
343
45
  }
344
345
  // Used by the TableGen code to check for particular operand types.
346
4.84k
  bool isGR32() const { return isReg(GR32Reg); }
347
1.28k
  bool isGRH32() const { return isReg(GRH32Reg); }
348
0
  bool isGRX32() const { return false; }
349
5.75k
  bool isGR64() const { return isReg(GR64Reg); }
350
1.14k
  bool isGR128() const { return isReg(GR128Reg); }
351
0
  bool isADDR32() const { return isReg(ADDR32Reg); }
352
36
  bool isADDR64() const { return isReg(ADDR64Reg); }
353
0
  bool isADDR128() const { return false; }
354
1.04k
  bool isFP32() const { return isReg(FP32Reg); }
355
2.18k
  bool isFP64() const { return isReg(FP64Reg); }
356
1.56k
  bool isFP128() const { return isReg(FP128Reg); }
357
1.56k
  bool isVR32() const { return isReg(VR32Reg); }
358
1.77k
  bool isVR64() const { return isReg(VR64Reg); }
359
0
  bool isVF128() const { return false; }
360
26.1k
  bool isVR128() const { return isReg(VR128Reg); }
361
158
  bool isAR32() const { return isReg(AR32Reg); }
362
144
  bool isCR64() const { return isReg(CR64Reg); }
363
37
  bool isAnyReg() const { return (isReg() || 
isImm(0, 15)3
); }
364
761
  bool isBDAddr32Disp12() const { return isMemDisp12(BDMem, ADDR32Reg); }
365
261
  bool isBDAddr32Disp20() const { return isMemDisp20(BDMem, ADDR32Reg); }
366
2.30k
  bool isBDAddr64Disp12() const { return isMemDisp12(BDMem, ADDR64Reg); }
367
1.29k
  bool isBDAddr64Disp20() const { return isMemDisp20(BDMem, ADDR64Reg); }
368
2.24k
  bool isBDXAddr64Disp12() const { return isMemDisp12(BDXMem, ADDR64Reg); }
369
2.03k
  bool isBDXAddr64Disp20() const { return isMemDisp20(BDXMem, ADDR64Reg); }
370
512
  bool isBDLAddr64Disp12Len4() const { return isMemDisp12Len4(ADDR64Reg); }
371
656
  bool isBDLAddr64Disp12Len8() const { return isMemDisp12Len8(ADDR64Reg); }
372
63
  bool isBDRAddr64Disp12() const { return isMemDisp12(BDRMem, ADDR64Reg); }
373
120
  bool isBDVAddr64Disp12() const { return isMemDisp12(BDVMem, ADDR64Reg); }
374
138
  bool isU1Imm() const { return isImm(0, 1); }
375
138
  bool isU2Imm() const { return isImm(0, 3); }
376
86
  bool isU3Imm() const { return isImm(0, 7); }
377
9.04k
  bool isU4Imm() const { return isImm(0, 15); }
378
104
  bool isU6Imm() const { return isImm(0, 63); }
379
1.40k
  bool isU8Imm() const { return isImm(0, 255); }
380
276
  bool isS8Imm() const { return isImm(-128, 127); }
381
134
  bool isU12Imm() const { return isImm(0, 4095); }
382
436
  bool isU16Imm() const { return isImm(0, 65535); }
383
601
  bool isS16Imm() const { return isImm(-32768, 32767); }
384
135
  bool isU32Imm() const { return isImm(0, (1LL << 32) - 1); }
385
142
  bool isS32Imm() const { return isImm(-(1LL << 31), (1LL << 31) - 1); }
386
19
  bool isU48Imm() const { return isImm(0, (1LL << 48) - 1); }
387
};
388
389
class SystemZAsmParser : public MCTargetAsmParser {
390
#define GET_ASSEMBLER_HEADER
391
#include "SystemZGenAsmMatcher.inc"
392
393
private:
394
  MCAsmParser &Parser;
395
  enum RegisterGroup {
396
    RegGR,
397
    RegFP,
398
    RegV,
399
    RegAR,
400
    RegCR
401
  };
402
  struct Register {
403
    RegisterGroup Group;
404
    unsigned Num;
405
    SMLoc StartLoc, EndLoc;
406
  };
407
408
  bool parseRegister(Register &Reg);
409
410
  bool parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs,
411
                     bool IsAddress = false);
412
413
  OperandMatchResultTy parseRegister(OperandVector &Operands,
414
                                     RegisterGroup Group, const unsigned *Regs,
415
                                     RegisterKind Kind);
416
417
  OperandMatchResultTy parseAnyRegister(OperandVector &Operands);
418
419
  bool parseAddress(bool &HaveReg1, Register &Reg1,
420
                    bool &HaveReg2, Register &Reg2,
421
                    const MCExpr *&Disp, const MCExpr *&Length);
422
  bool parseAddressRegister(Register &Reg);
423
424
  bool ParseDirectiveInsn(SMLoc L);
425
426
  OperandMatchResultTy parseAddress(OperandVector &Operands,
427
                                    MemoryKind MemKind, const unsigned *Regs,
428
                                    RegisterKind RegKind);
429
430
  OperandMatchResultTy parsePCRel(OperandVector &Operands, int64_t MinVal,
431
                                  int64_t MaxVal, bool AllowTLS);
432
433
  bool parseOperand(OperandVector &Operands, StringRef Mnemonic);
434
435
public:
436
  SystemZAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser,
437
                   const MCInstrInfo &MII,
438
                   const MCTargetOptions &Options)
439
47
    : MCTargetAsmParser(Options, sti, MII), Parser(parser) {
440
47
    MCAsmParserExtension::Initialize(Parser);
441
47
442
47
    // Alias the .word directive to .short.
443
47
    parser.addAliasForDirective(".word", ".short");
444
47
445
47
    // Initialize the set of available features.
446
47
    setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
447
47
  }
448
449
  // Override MCTargetAsmParser.
450
  bool ParseDirective(AsmToken DirectiveID) override;
451
  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
452
  bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
453
                        SMLoc NameLoc, OperandVector &Operands) override;
454
  bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
455
                               OperandVector &Operands, MCStreamer &Out,
456
                               uint64_t &ErrorInfo,
457
                               bool MatchingInlineAsm) override;
458
459
  // Used by the TableGen code to parse particular operand types.
460
5.17k
  OperandMatchResultTy parseGR32(OperandVector &Operands) {
461
5.17k
    return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, GR32Reg);
462
5.17k
  }
463
1.30k
  OperandMatchResultTy parseGRH32(OperandVector &Operands) {
464
1.30k
    return parseRegister(Operands, RegGR, SystemZMC::GRH32Regs, GRH32Reg);
465
1.30k
  }
466
0
  OperandMatchResultTy parseGRX32(OperandVector &Operands) {
467
0
    llvm_unreachable("GRX32 should only be used for pseudo instructions");
468
0
  }
469
6.10k
  OperandMatchResultTy parseGR64(OperandVector &Operands) {
470
6.10k
    return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, GR64Reg);
471
6.10k
  }
472
1.34k
  OperandMatchResultTy parseGR128(OperandVector &Operands) {
473
1.34k
    return parseRegister(Operands, RegGR, SystemZMC::GR128Regs, GR128Reg);
474
1.34k
  }
475
0
  OperandMatchResultTy parseADDR32(OperandVector &Operands) {
476
0
    return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, ADDR32Reg);
477
0
  }
478
37
  OperandMatchResultTy parseADDR64(OperandVector &Operands) {
479
37
    return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, ADDR64Reg);
480
37
  }
481
0
  OperandMatchResultTy parseADDR128(OperandVector &Operands) {
482
0
    llvm_unreachable("Shouldn't be used as an operand");
483
0
  }
484
1.08k
  OperandMatchResultTy parseFP32(OperandVector &Operands) {
485
1.08k
    return parseRegister(Operands, RegFP, SystemZMC::FP32Regs, FP32Reg);
486
1.08k
  }
487
2.31k
  OperandMatchResultTy parseFP64(OperandVector &Operands) {
488
2.31k
    return parseRegister(Operands, RegFP, SystemZMC::FP64Regs, FP64Reg);
489
2.31k
  }
490
2.18k
  OperandMatchResultTy parseFP128(OperandVector &Operands) {
491
2.18k
    return parseRegister(Operands, RegFP, SystemZMC::FP128Regs, FP128Reg);
492
2.18k
  }
493
1.56k
  OperandMatchResultTy parseVR32(OperandVector &Operands) {
494
1.56k
    return parseRegister(Operands, RegV, SystemZMC::VR32Regs, VR32Reg);
495
1.56k
  }
496
1.77k
  OperandMatchResultTy parseVR64(OperandVector &Operands) {
497
1.77k
    return parseRegister(Operands, RegV, SystemZMC::VR64Regs, VR64Reg);
498
1.77k
  }
499
0
  OperandMatchResultTy parseVF128(OperandVector &Operands) {
500
0
    llvm_unreachable("Shouldn't be used as an operand");
501
0
  }
502
24.3k
  OperandMatchResultTy parseVR128(OperandVector &Operands) {
503
24.3k
    return parseRegister(Operands, RegV, SystemZMC::VR128Regs, VR128Reg);
504
24.3k
  }
505
177
  OperandMatchResultTy parseAR32(OperandVector &Operands) {
506
177
    return parseRegister(Operands, RegAR, SystemZMC::AR32Regs, AR32Reg);
507
177
  }
508
166
  OperandMatchResultTy parseCR64(OperandVector &Operands) {
509
166
    return parseRegister(Operands, RegCR, SystemZMC::CR64Regs, CR64Reg);
510
166
  }
511
37
  OperandMatchResultTy parseAnyReg(OperandVector &Operands) {
512
37
    return parseAnyRegister(Operands);
513
37
  }
514
1.13k
  OperandMatchResultTy parseBDAddr32(OperandVector &Operands) {
515
1.13k
    return parseAddress(Operands, BDMem, SystemZMC::GR32Regs, ADDR32Reg);
516
1.13k
  }
517
4.22k
  OperandMatchResultTy parseBDAddr64(OperandVector &Operands) {
518
4.22k
    return parseAddress(Operands, BDMem, SystemZMC::GR64Regs, ADDR64Reg);
519
4.22k
  }
520
4.35k
  OperandMatchResultTy parseBDXAddr64(OperandVector &Operands) {
521
4.35k
    return parseAddress(Operands, BDXMem, SystemZMC::GR64Regs, ADDR64Reg);
522
4.35k
  }
523
1.84k
  OperandMatchResultTy parseBDLAddr64(OperandVector &Operands) {
524
1.84k
    return parseAddress(Operands, BDLMem, SystemZMC::GR64Regs, ADDR64Reg);
525
1.84k
  }
526
93
  OperandMatchResultTy parseBDRAddr64(OperandVector &Operands) {
527
93
    return parseAddress(Operands, BDRMem, SystemZMC::GR64Regs, ADDR64Reg);
528
93
  }
529
136
  OperandMatchResultTy parseBDVAddr64(OperandVector &Operands) {
530
136
    return parseAddress(Operands, BDVMem, SystemZMC::GR64Regs, ADDR64Reg);
531
136
  }
532
60
  OperandMatchResultTy parsePCRel12(OperandVector &Operands) {
533
60
    return parsePCRel(Operands, -(1LL << 12), (1LL << 12) - 1, false);
534
60
  }
535
819
  OperandMatchResultTy parsePCRel16(OperandVector &Operands) {
536
819
    return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, false);
537
819
  }
538
52
  OperandMatchResultTy parsePCRel24(OperandVector &Operands) {
539
52
    return parsePCRel(Operands, -(1LL << 24), (1LL << 24) - 1, false);
540
52
  }
541
554
  OperandMatchResultTy parsePCRel32(OperandVector &Operands) {
542
554
    return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, false);
543
554
  }
544
29
  OperandMatchResultTy parsePCRelTLS16(OperandVector &Operands) {
545
29
    return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, true);
546
29
  }
547
32
  OperandMatchResultTy parsePCRelTLS32(OperandVector &Operands) {
548
32
    return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, true);
549
32
  }
550
};
551
552
} // end anonymous namespace
553
554
#define GET_REGISTER_MATCHER
555
#define GET_SUBTARGET_FEATURE_NAME
556
#define GET_MATCHER_IMPLEMENTATION
557
#define GET_MNEMONIC_SPELL_CHECKER
558
#include "SystemZGenAsmMatcher.inc"
559
560
// Used for the .insn directives; contains information needed to parse the
561
// operands in the directive.
562
struct InsnMatchEntry {
563
  StringRef Format;
564
  uint64_t Opcode;
565
  int32_t NumOperands;
566
  MatchClassKind OperandKinds[5];
567
};
568
569
// For equal_range comparison.
570
struct CompareInsn {
571
139
  bool operator() (const InsnMatchEntry &LHS, StringRef RHS) {
572
139
    return LHS.Format < RHS;
573
139
  }
574
105
  bool operator() (StringRef LHS, const InsnMatchEntry &RHS) {
575
105
    return LHS < RHS.Format;
576
105
  }
577
0
  bool operator() (const InsnMatchEntry &LHS, const InsnMatchEntry &RHS) {
578
0
    return LHS.Format < RHS.Format;
579
0
  }
580
};
581
582
// Table initializing information for parsing the .insn directive.
583
static struct InsnMatchEntry InsnMatchTable[] = {
584
  /* Format, Opcode, NumOperands, OperandKinds */
585
  { "e", SystemZ::InsnE, 1,
586
    { MCK_U16Imm } },
587
  { "ri", SystemZ::InsnRI, 3,
588
    { MCK_U32Imm, MCK_AnyReg, MCK_S16Imm } },
589
  { "rie", SystemZ::InsnRIE, 4,
590
    { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } },
591
  { "ril", SystemZ::InsnRIL, 3,
592
    { MCK_U48Imm, MCK_AnyReg, MCK_PCRel32 } },
593
  { "rilu", SystemZ::InsnRILU, 3,
594
    { MCK_U48Imm, MCK_AnyReg, MCK_U32Imm } },
595
  { "ris", SystemZ::InsnRIS, 5,
596
    { MCK_U48Imm, MCK_AnyReg, MCK_S8Imm, MCK_U4Imm, MCK_BDAddr64Disp12 } },
597
  { "rr", SystemZ::InsnRR, 3,
598
    { MCK_U16Imm, MCK_AnyReg, MCK_AnyReg } },
599
  { "rre", SystemZ::InsnRRE, 3,
600
    { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg } },
601
  { "rrf", SystemZ::InsnRRF, 5,
602
    { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm } },
603
  { "rrs", SystemZ::InsnRRS, 5,
604
    { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm, MCK_BDAddr64Disp12 } },
605
  { "rs", SystemZ::InsnRS, 4,
606
    { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } },
607
  { "rse", SystemZ::InsnRSE, 4,
608
    { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } },
609
  { "rsi", SystemZ::InsnRSI, 4,
610
    { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } },
611
  { "rsy", SystemZ::InsnRSY, 4,
612
    { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp20 } },
613
  { "rx", SystemZ::InsnRX, 3,
614
    { MCK_U32Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
615
  { "rxe", SystemZ::InsnRXE, 3,
616
    { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
617
  { "rxf", SystemZ::InsnRXF, 4,
618
    { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
619
  { "rxy", SystemZ::InsnRXY, 3,
620
    { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp20 } },
621
  { "s", SystemZ::InsnS, 2,
622
    { MCK_U32Imm, MCK_BDAddr64Disp12 } },
623
  { "si", SystemZ::InsnSI, 3,
624
    { MCK_U32Imm, MCK_BDAddr64Disp12, MCK_S8Imm } },
625
  { "sil", SystemZ::InsnSIL, 3,
626
    { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_U16Imm } },
627
  { "siy", SystemZ::InsnSIY, 3,
628
    { MCK_U48Imm, MCK_BDAddr64Disp20, MCK_U8Imm } },
629
  { "ss", SystemZ::InsnSS, 4,
630
    { MCK_U48Imm, MCK_BDXAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } },
631
  { "sse", SystemZ::InsnSSE, 3,
632
    { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12 } },
633
  { "ssf", SystemZ::InsnSSF, 4,
634
    { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } }
635
};
636
637
0
static void printMCExpr(const MCExpr *E, raw_ostream &OS) {
638
0
  if (!E)
639
0
    return;
640
0
  if (auto *CE = dyn_cast<MCConstantExpr>(E))
641
0
    OS << *CE;
642
0
  else if (auto *UE = dyn_cast<MCUnaryExpr>(E))
643
0
    OS << *UE;
644
0
  else if (auto *BE = dyn_cast<MCBinaryExpr>(E))
645
0
    OS << *BE;
646
0
  else if (auto *SRE = dyn_cast<MCSymbolRefExpr>(E))
647
0
    OS << *SRE;
648
0
  else
649
0
    OS << *E;
650
0
}
651
652
0
void SystemZOperand::print(raw_ostream &OS) const {
653
0
  switch (Kind) {
654
0
  case KindToken:
655
0
    OS << "Token:" << getToken();
656
0
    break;
657
0
  case KindReg:
658
0
    OS << "Reg:" << SystemZInstPrinter::getRegisterName(getReg());
659
0
    break;
660
0
  case KindImm:
661
0
    OS << "Imm:";
662
0
    printMCExpr(getImm(), OS);
663
0
    break;
664
0
  case KindImmTLS:
665
0
    OS << "ImmTLS:";
666
0
    printMCExpr(getImmTLS().Imm, OS);
667
0
    if (getImmTLS().Sym) {
668
0
      OS << ", ";
669
0
      printMCExpr(getImmTLS().Sym, OS);
670
0
    }
671
0
    break;
672
0
  case KindMem: {
673
0
    const MemOp &Op = getMem();
674
0
    OS << "Mem:" << *cast<MCConstantExpr>(Op.Disp);
675
0
    if (Op.Base) {
676
0
      OS << "(";
677
0
      if (Op.MemKind == BDLMem)
678
0
        OS << *cast<MCConstantExpr>(Op.Length.Imm) << ",";
679
0
      else if (Op.MemKind == BDRMem)
680
0
        OS << SystemZInstPrinter::getRegisterName(Op.Length.Reg) << ",";
681
0
      if (Op.Index)
682
0
        OS << SystemZInstPrinter::getRegisterName(Op.Index) << ",";
683
0
      OS << SystemZInstPrinter::getRegisterName(Op.Base);
684
0
      OS << ")";
685
0
    }
686
0
    break;
687
0
  }
688
0
  case KindInvalid:
689
0
    break;
690
0
  }
691
0
}
692
693
// Parse one register of the form %<prefix><number>.
694
54.8k
bool SystemZAsmParser::parseRegister(Register &Reg) {
695
54.8k
  Reg.StartLoc = Parser.getTok().getLoc();
696
54.8k
697
54.8k
  // Eat the % prefix.
698
54.8k
  if (Parser.getTok().isNot(AsmToken::Percent))
699
2
    return Error(Parser.getTok().getLoc(), "register expected");
700
54.8k
  Parser.Lex();
701
54.8k
702
54.8k
  // Expect a register name.
703
54.8k
  if (Parser.getTok().isNot(AsmToken::Identifier))
704
3
    return Error(Reg.StartLoc, "invalid register");
705
54.8k
706
54.8k
  // Check that there's a prefix.
707
54.8k
  StringRef Name = Parser.getTok().getString();
708
54.8k
  if (Name.size() < 2)
709
5
    return Error(Reg.StartLoc, "invalid register");
710
54.8k
  char Prefix = Name[0];
711
54.8k
712
54.8k
  // Treat the rest of the register name as a register number.
713
54.8k
  if (Name.substr(1).getAsInteger(10, Reg.Num))
714
2
    return Error(Reg.StartLoc, "invalid register");
715
54.8k
716
54.8k
  // Look for valid combinations of prefix and number.
717
54.8k
  if (Prefix == 'r' && 
Reg.Num < 1620.9k
)
718
20.9k
    Reg.Group = RegGR;
719
33.8k
  else if (Prefix == 'f' && 
Reg.Num < 166.03k
)
720
6.03k
    Reg.Group = RegFP;
721
27.8k
  else if (Prefix == 'v' && 
Reg.Num < 3227.4k
)
722
27.4k
    Reg.Group = RegV;
723
402
  else if (Prefix == 'a' && 
Reg.Num < 16206
)
724
204
    Reg.Group = RegAR;
725
198
  else if (Prefix == 'c' && 
Reg.Num < 16191
)
726
190
    Reg.Group = RegCR;
727
8
  else
728
8
    return Error(Reg.StartLoc, "invalid register");
729
54.8k
730
54.8k
  Reg.EndLoc = Parser.getTok().getLoc();
731
54.8k
  Parser.Lex();
732
54.8k
  return false;
733
54.8k
}
734
735
// Parse a register of group Group.  If Regs is nonnull, use it to map
736
// the raw register number to LLVM numbering, with zero entries
737
// indicating an invalid register.  IsAddress says whether the
738
// register appears in an address context. Allow FP Group if expecting
739
// RegV Group, since the f-prefix yields the FP group even while used
740
// with vector instructions.
741
bool SystemZAsmParser::parseRegister(Register &Reg, RegisterGroup Group,
742
47.5k
                                     const unsigned *Regs, bool IsAddress) {
743
47.5k
  if (parseRegister(Reg))
744
0
    return true;
745
47.5k
  if (Reg.Group != Group && 
!(500
Reg.Group == RegFP500
&&
Group == RegV450
))
746
64
    return Error(Reg.StartLoc, "invalid operand for instruction");
747
47.4k
  if (Regs && Regs[Reg.Num] == 0)
748
567
    return Error(Reg.StartLoc, "invalid register pair");
749
46.8k
  if (Reg.Num == 0 && 
IsAddress32.5k
)
750
1
    return Error(Reg.StartLoc, "%r0 used in an address");
751
46.8k
  if (Regs)
752
46.8k
    Reg.Num = Regs[Reg.Num];
753
46.8k
  return false;
754
46.8k
}
755
756
// Parse a register and add it to Operands.  The other arguments are as above.
757
OperandMatchResultTy
758
SystemZAsmParser::parseRegister(OperandVector &Operands, RegisterGroup Group,
759
47.5k
                                const unsigned *Regs, RegisterKind Kind) {
760
47.5k
  if (Parser.getTok().isNot(AsmToken::Percent))
761
22
    return MatchOperand_NoMatch;
762
47.5k
763
47.5k
  Register Reg;
764
47.5k
  bool IsAddress = (Kind == ADDR32Reg || Kind == ADDR64Reg);
765
47.5k
  if (parseRegister(Reg, Group, Regs, IsAddress))
766
632
    return MatchOperand_ParseFail;
767
46.8k
768
46.8k
  Operands.push_back(SystemZOperand::createReg(Kind, Reg.Num,
769
46.8k
                                               Reg.StartLoc, Reg.EndLoc));
770
46.8k
  return MatchOperand_Success;
771
46.8k
}
772
773
// Parse any type of register (including integers) and add it to Operands.
774
OperandMatchResultTy
775
37
SystemZAsmParser::parseAnyRegister(OperandVector &Operands) {
776
37
  // Handle integer values.
777
37
  if (Parser.getTok().is(AsmToken::Integer)) {
778
3
    const MCExpr *Register;
779
3
    SMLoc StartLoc = Parser.getTok().getLoc();
780
3
    if (Parser.parseExpression(Register))
781
0
      return MatchOperand_ParseFail;
782
3
783
3
    if (auto *CE = dyn_cast<MCConstantExpr>(Register)) {
784
3
      int64_t Value = CE->getValue();
785
3
      if (Value < 0 || Value > 15) {
786
0
        Error(StartLoc, "invalid register");
787
0
        return MatchOperand_ParseFail;
788
0
      }
789
3
    }
790
3
791
3
    SMLoc EndLoc =
792
3
      SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
793
3
794
3
    Operands.push_back(SystemZOperand::createImm(Register, StartLoc, EndLoc));
795
3
  }
796
34
  else {
797
34
    Register Reg;
798
34
    if (parseRegister(Reg))
799
0
      return MatchOperand_ParseFail;
800
34
801
34
    // Map to the correct register kind.
802
34
    RegisterKind Kind;
803
34
    unsigned RegNo;
804
34
    if (Reg.Group == RegGR) {
805
27
      Kind = GR64Reg;
806
27
      RegNo = SystemZMC::GR64Regs[Reg.Num];
807
27
    }
808
7
    else if (Reg.Group == RegFP) {
809
7
      Kind = FP64Reg;
810
7
      RegNo = SystemZMC::FP64Regs[Reg.Num];
811
7
    }
812
0
    else if (Reg.Group == RegV) {
813
0
      Kind = VR128Reg;
814
0
      RegNo = SystemZMC::VR128Regs[Reg.Num];
815
0
    }
816
0
    else if (Reg.Group == RegAR) {
817
0
      Kind = AR32Reg;
818
0
      RegNo = SystemZMC::AR32Regs[Reg.Num];
819
0
    }
820
0
    else if (Reg.Group == RegCR) {
821
0
      Kind = CR64Reg;
822
0
      RegNo = SystemZMC::CR64Regs[Reg.Num];
823
0
    }
824
0
    else {
825
0
      return MatchOperand_ParseFail;
826
0
    }
827
34
828
34
    Operands.push_back(SystemZOperand::createReg(Kind, RegNo,
829
34
                                                 Reg.StartLoc, Reg.EndLoc));
830
34
  }
831
37
  return MatchOperand_Success;
832
37
}
833
834
// Parse a memory operand into Reg1, Reg2, Disp, and Length.
835
bool SystemZAsmParser::parseAddress(bool &HaveReg1, Register &Reg1,
836
                                    bool &HaveReg2, Register &Reg2,
837
                                    const MCExpr *&Disp,
838
25.8k
                                    const MCExpr *&Length) {
839
25.8k
  // Parse the displacement, which must always be present.
840
25.8k
  if (getParser().parseExpression(Disp))
841
1
    return true;
842
25.8k
843
25.8k
  // Parse the optional base and index.
844
25.8k
  HaveReg1 = false;
845
25.8k
  HaveReg2 = false;
846
25.8k
  Length = nullptr;
847
25.8k
  if (getLexer().is(AsmToken::LParen)) {
848
6.07k
    Parser.Lex();
849
6.07k
850
6.07k
    if (getLexer().is(AsmToken::Percent)) {
851
4.44k
      // Parse the first register.
852
4.44k
      HaveReg1 = true;
853
4.44k
      if (parseRegister(Reg1))
854
0
        return true;
855
1.63k
    } else {
856
1.63k
      // Parse the length.
857
1.63k
      if (getParser().parseExpression(Length))
858
79
        return true;
859
6.00k
    }
860
6.00k
861
6.00k
    // Check whether there's a second register.
862
6.00k
    if (getLexer().is(AsmToken::Comma)) {
863
2.58k
      Parser.Lex();
864
2.58k
      HaveReg2 = true;
865
2.58k
      if (parseRegister(Reg2))
866
1
        return true;
867
5.99k
    }
868
5.99k
869
5.99k
    // Consume the closing bracket.
870
5.99k
    if (getLexer().isNot(AsmToken::RParen))
871
1
      return Error(Parser.getTok().getLoc(), "unexpected token in address");
872
5.99k
    Parser.Lex();
873
5.99k
  }
874
25.8k
  
return false25.7k
;
875
25.8k
}
876
877
// Verify that Reg is a valid address register (base or index).
878
bool
879
6.12k
SystemZAsmParser::parseAddressRegister(Register &Reg) {
880
6.12k
  if (Reg.Group == RegV) {
881
83
    Error(Reg.StartLoc, "invalid use of vector addressing");
882
83
    return true;
883
6.03k
  } else if (Reg.Group != RegGR) {
884
2
    Error(Reg.StartLoc, "invalid address register");
885
2
    return true;
886
6.03k
  } else if (Reg.Num == 0) {
887
217
    Error(Reg.StartLoc, "%r0 used in an address");
888
217
    return true;
889
217
  }
890
5.81k
  return false;
891
5.81k
}
892
893
// Parse a memory operand and add it to Operands.  The other arguments
894
// are as above.
895
OperandMatchResultTy
896
SystemZAsmParser::parseAddress(OperandVector &Operands, MemoryKind MemKind,
897
11.8k
                               const unsigned *Regs, RegisterKind RegKind) {
898
11.8k
  SMLoc StartLoc = Parser.getTok().getLoc();
899
11.8k
  unsigned Base = 0, Index = 0, LengthReg = 0;
900
11.8k
  Register Reg1, Reg2;
901
11.8k
  bool HaveReg1, HaveReg2;
902
11.8k
  const MCExpr *Disp;
903
11.8k
  const MCExpr *Length;
904
11.8k
  if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Disp, Length))
905
78
    return MatchOperand_ParseFail;
906
11.7k
907
11.7k
  switch (MemKind) {
908
11.7k
  case BDMem:
909
5.36k
    // If we have Reg1, it must be an address register.
910
5.36k
    if (HaveReg1) {
911
2.55k
      if (parseAddressRegister(Reg1))
912
115
        return MatchOperand_ParseFail;
913
2.44k
      Base = Regs[Reg1.Num];
914
2.44k
    }
915
5.36k
    // There must be no Reg2 or length.
916
5.36k
    
if (5.25k
Length5.25k
) {
917
42
      Error(StartLoc, "invalid use of length addressing");
918
42
      return MatchOperand_ParseFail;
919
42
    }
920
5.20k
    if (HaveReg2) {
921
357
      Error(StartLoc, "invalid use of indexed addressing");
922
357
      return MatchOperand_ParseFail;
923
357
    }
924
4.85k
    break;
925
4.85k
  case BDXMem:
926
4.35k
    // If we have Reg1, it must be an address register.
927
4.35k
    if (HaveReg1) {
928
1.46k
      if (parseAddressRegister(Reg1))
929
85
        return MatchOperand_ParseFail;
930
1.37k
      // If the are two registers, the first one is the index and the
931
1.37k
      // second is the base.
932
1.37k
      if (HaveReg2)
933
684
        Index = Regs[Reg1.Num];
934
695
      else
935
695
        Base = Regs[Reg1.Num];
936
1.37k
    }
937
4.35k
    // If we have Reg2, it must be an address register.
938
4.35k
    
if (4.27k
HaveReg24.27k
) {
939
684
      if (parseAddressRegister(Reg2))
940
1
        return MatchOperand_ParseFail;
941
683
      Base = Regs[Reg2.Num];
942
683
    }
943
4.27k
    // There must be no length.
944
4.27k
    
if (4.27k
Length4.27k
) {
945
0
      Error(StartLoc, "invalid use of length addressing");
946
0
      return MatchOperand_ParseFail;
947
0
    }
948
4.27k
    break;
949
4.27k
  case BDLMem:
950
1.77k
    // If we have Reg2, it must be an address register.
951
1.77k
    if (HaveReg2) {
952
1.22k
      if (parseAddressRegister(Reg2))
953
90
        return MatchOperand_ParseFail;
954
1.13k
      Base = Regs[Reg2.Num];
955
1.13k
    }
956
1.77k
    // We cannot support base+index addressing.
957
1.77k
    
if (1.68k
HaveReg11.68k
&&
HaveReg2180
) {
958
90
      Error(StartLoc, "invalid use of indexed addressing");
959
90
      return MatchOperand_ParseFail;
960
90
    }
961
1.59k
    // We must have a length.
962
1.59k
    if (!Length) {
963
180
      Error(StartLoc, "missing length in address");
964
180
      return MatchOperand_ParseFail;
965
180
    }
966
1.41k
    break;
967
1.41k
  case BDRMem:
968
87
    // We must have Reg1, and it must be a GPR.
969
87
    if (!HaveReg1 || Reg1.Group != RegGR) {
970
0
      Error(StartLoc, "invalid operand for instruction");
971
0
      return MatchOperand_ParseFail;
972
0
    }
973
87
    LengthReg = SystemZMC::GR64Regs[Reg1.Num];
974
87
    // If we have Reg2, it must be an address register.
975
87
    if (HaveReg2) {
976
66
      if (parseAddressRegister(Reg2))
977
6
        return MatchOperand_ParseFail;
978
60
      Base = Regs[Reg2.Num];
979
60
    }
980
87
    // There must be no length.
981
87
    
if (81
Length81
) {
982
0
      Error(StartLoc, "invalid use of length addressing");
983
0
      return MatchOperand_ParseFail;
984
0
    }
985
81
    break;
986
136
  case BDVMem:
987
136
    // We must have Reg1, and it must be a vector register.
988
136
    if (!HaveReg1 || Reg1.Group != RegV) {
989
16
      Error(StartLoc, "vector index required in address");
990
16
      return MatchOperand_ParseFail;
991
16
    }
992
120
    Index = SystemZMC::VR128Regs[Reg1.Num];
993
120
    // If we have Reg2, it must be an address register.
994
120
    if (HaveReg2) {
995
112
      if (parseAddressRegister(Reg2))
996
0
        return MatchOperand_ParseFail;
997
112
      Base = Regs[Reg2.Num];
998
112
    }
999
120
    // There must be no length.
1000
120
    if (Length) {
1001
0
      Error(StartLoc, "invalid use of length addressing");
1002
0
      return MatchOperand_ParseFail;
1003
0
    }
1004
120
    break;
1005
10.7k
  }
1006
10.7k
1007
10.7k
  SMLoc EndLoc =
1008
10.7k
    SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1009
10.7k
  Operands.push_back(SystemZOperand::createMem(MemKind, RegKind, Base, Disp,
1010
10.7k
                                               Index, Length, LengthReg,
1011
10.7k
                                               StartLoc, EndLoc));
1012
10.7k
  return MatchOperand_Success;
1013
10.7k
}
1014
1015
480
bool SystemZAsmParser::ParseDirective(AsmToken DirectiveID) {
1016
480
  StringRef IDVal = DirectiveID.getIdentifier();
1017
480
1018
480
  if (IDVal == ".insn")
1019
29
    return ParseDirectiveInsn(DirectiveID.getLoc());
1020
451
1021
451
  return true;
1022
451
}
1023
1024
/// ParseDirectiveInsn
1025
/// ::= .insn [ format, encoding, (operands (, operands)*) ]
1026
29
bool SystemZAsmParser::ParseDirectiveInsn(SMLoc L) {
1027
29
  MCAsmParser &Parser = getParser();
1028
29
1029
29
  // Expect instruction format as identifier.
1030
29
  StringRef Format;
1031
29
  SMLoc ErrorLoc = Parser.getTok().getLoc();
1032
29
  if (Parser.parseIdentifier(Format))
1033
0
    return Error(ErrorLoc, "expected instruction format");
1034
29
1035
29
  SmallVector<std::unique_ptr<MCParsedAsmOperand>, 8> Operands;
1036
29
1037
29
  // Find entry for this format in InsnMatchTable.
1038
29
  auto EntryRange =
1039
29
    std::equal_range(std::begin(InsnMatchTable), std::end(InsnMatchTable),
1040
29
                     Format, CompareInsn());
1041
29
1042
29
  // If first == second, couldn't find a match in the table.
1043
29
  if (EntryRange.first == EntryRange.second)
1044
0
    return Error(ErrorLoc, "unrecognized format");
1045
29
1046
29
  struct InsnMatchEntry *Entry = EntryRange.first;
1047
29
1048
29
  // Format should match from equal_range.
1049
29
  assert(Entry->Format == Format);
1050
29
1051
29
  // Parse the following operands using the table's information.
1052
129
  for (int i = 0; i < Entry->NumOperands; 
i++100
) {
1053
100
    MatchClassKind Kind = Entry->OperandKinds[i];
1054
100
1055
100
    SMLoc StartLoc = Parser.getTok().getLoc();
1056
100
1057
100
    // Always expect commas as separators for operands.
1058
100
    if (getLexer().isNot(AsmToken::Comma))
1059
0
      return Error(StartLoc, "unexpected token in directive");
1060
100
    Lex();
1061
100
1062
100
    // Parse operands.
1063
100
    OperandMatchResultTy ResTy;
1064
100
    if (Kind == MCK_AnyReg)
1065
37
      ResTy = parseAnyReg(Operands);
1066
63
    else if (Kind == MCK_BDXAddr64Disp12 || 
Kind == MCK_BDXAddr64Disp2059
)
1067
5
      ResTy = parseBDXAddr64(Operands);
1068
58
    else if (Kind == MCK_BDAddr64Disp12 || 
Kind == MCK_BDAddr64Disp2046
)
1069
14
      ResTy = parseBDAddr64(Operands);
1070
44
    else if (Kind == MCK_PCRel32)
1071
2
      ResTy = parsePCRel32(Operands);
1072
42
    else if (Kind == MCK_PCRel16)
1073
4
      ResTy = parsePCRel16(Operands);
1074
38
    else {
1075
38
      // Only remaining operand kind is an immediate.
1076
38
      const MCExpr *Expr;
1077
38
      SMLoc StartLoc = Parser.getTok().getLoc();
1078
38
1079
38
      // Expect immediate expression.
1080
38
      if (Parser.parseExpression(Expr))
1081
0
        return Error(StartLoc, "unexpected token in directive");
1082
38
1083
38
      SMLoc EndLoc =
1084
38
        SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1085
38
1086
38
      Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1087
38
      ResTy = MatchOperand_Success;
1088
38
    }
1089
100
1090
100
    if (ResTy != MatchOperand_Success)
1091
0
      return true;
1092
100
  }
1093
29
1094
29
  // Build the instruction with the parsed operands.
1095
29
  MCInst Inst = MCInstBuilder(Entry->Opcode);
1096
29
1097
129
  for (size_t i = 0; i < Operands.size(); 
i++100
) {
1098
100
    MCParsedAsmOperand &Operand = *Operands[i];
1099
100
    MatchClassKind Kind = Entry->OperandKinds[i];
1100
100
1101
100
    // Verify operand.
1102
100
    unsigned Res = validateOperandClass(Operand, Kind);
1103
100
    if (Res != Match_Success)
1104
0
      return Error(Operand.getStartLoc(), "unexpected operand type");
1105
100
1106
100
    // Add operands to instruction.
1107
100
    SystemZOperand &ZOperand = static_cast<SystemZOperand &>(Operand);
1108
100
    if (ZOperand.isReg())
1109
34
      ZOperand.addRegOperands(Inst, 1);
1110
66
    else if (ZOperand.isMem(BDMem))
1111
14
      ZOperand.addBDAddrOperands(Inst, 2);
1112
52
    else if (ZOperand.isMem(BDXMem))
1113
5
      ZOperand.addBDXAddrOperands(Inst, 3);
1114
47
    else if (ZOperand.isImm())
1115
47
      ZOperand.addImmOperands(Inst, 1);
1116
47
    else
1117
47
      
llvm_unreachable0
("unexpected operand type");
1118
100
  }
1119
29
1120
29
  // Emit as a regular instruction.
1121
29
  Parser.getStreamer().EmitInstruction(Inst, getSTI());
1122
29
1123
29
  return false;
1124
29
}
1125
1126
bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
1127
94
                                     SMLoc &EndLoc) {
1128
94
  Register Reg;
1129
94
  if (parseRegister(Reg))
1130
13
    return true;
1131
81
  if (Reg.Group == RegGR)
1132
26
    RegNo = SystemZMC::GR64Regs[Reg.Num];
1133
55
  else if (Reg.Group == RegFP)
1134
24
    RegNo = SystemZMC::FP64Regs[Reg.Num];
1135
31
  else if (Reg.Group == RegV)
1136
0
    RegNo = SystemZMC::VR128Regs[Reg.Num];
1137
31
  else if (Reg.Group == RegAR)
1138
15
    RegNo = SystemZMC::AR32Regs[Reg.Num];
1139
16
  else if (Reg.Group == RegCR)
1140
16
    RegNo = SystemZMC::CR64Regs[Reg.Num];
1141
81
  StartLoc = Reg.StartLoc;
1142
81
  EndLoc = Reg.EndLoc;
1143
81
  return false;
1144
81
}
1145
1146
bool SystemZAsmParser::ParseInstruction(ParseInstructionInfo &Info,
1147
                                        StringRef Name, SMLoc NameLoc,
1148
26.8k
                                        OperandVector &Operands) {
1149
26.8k
  Operands.push_back(SystemZOperand::createToken(Name, NameLoc));
1150
26.8k
1151
26.8k
  // Read the remaining operands.
1152
26.8k
  if (getLexer().isNot(AsmToken::EndOfStatement)) {
1153
26.7k
    // Read the first operand.
1154
26.7k
    if (parseOperand(Operands, Name)) {
1155
843
      return true;
1156
843
    }
1157
25.9k
1158
25.9k
    // Read any subsequent operands.
1159
72.9k
    
while (25.9k
getLexer().is(AsmToken::Comma)) {
1160
48.2k
      Parser.Lex();
1161
48.2k
      if (parseOperand(Operands, Name)) {
1162
1.22k
        return true;
1163
1.22k
      }
1164
48.2k
    }
1165
25.9k
    
if (24.7k
getLexer().isNot(AsmToken::EndOfStatement)24.7k
) {
1166
1
      SMLoc Loc = getLexer().getLoc();
1167
1
      return Error(Loc, "unexpected token in argument list");
1168
1
    }
1169
24.7k
  }
1170
24.7k
1171
24.7k
  // Consume the EndOfStatement.
1172
24.7k
  Parser.Lex();
1173
24.7k
  return false;
1174
24.7k
}
1175
1176
bool SystemZAsmParser::parseOperand(OperandVector &Operands,
1177
74.9k
                                    StringRef Mnemonic) {
1178
74.9k
  // Check if the current operand has a custom associated parser, if so, try to
1179
74.9k
  // custom parse the operand, or fallback to the general approach.  Force all
1180
74.9k
  // features to be available during the operand check, or else we will fail to
1181
74.9k
  // find the custom parser, and then we will later get an InvalidOperand error
1182
74.9k
  // instead of a MissingFeature errror.
1183
74.9k
  FeatureBitset AvailableFeatures = getAvailableFeatures();
1184
74.9k
  FeatureBitset All;
1185
74.9k
  All.set();
1186
74.9k
  setAvailableFeatures(All);
1187
74.9k
  OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
1188
74.9k
  setAvailableFeatures(AvailableFeatures);
1189
74.9k
  if (ResTy == MatchOperand_Success)
1190
58.7k
    return false;
1191
16.1k
1192
16.1k
  // If there wasn't a custom match, try the generic matcher below. Otherwise,
1193
16.1k
  // there was a match, but an error occurred, in which case, just return that
1194
16.1k
  // the operand parsing failed.
1195
16.1k
  if (ResTy == MatchOperand_ParseFail)
1196
2.05k
    return true;
1197
14.1k
1198
14.1k
  // Check for a register.  All real register operands should have used
1199
14.1k
  // a context-dependent parse routine, which gives the required register
1200
14.1k
  // class.  The code is here to mop up other cases, like those where
1201
14.1k
  // the instruction isn't recognized.
1202
14.1k
  if (Parser.getTok().is(AsmToken::Percent)) {
1203
138
    Register Reg;
1204
138
    if (parseRegister(Reg))
1205
6
      return true;
1206
132
    Operands.push_back(SystemZOperand::createInvalid(Reg.StartLoc, Reg.EndLoc));
1207
132
    return false;
1208
132
  }
1209
14.0k
1210
14.0k
  // The only other type of operand is an immediate or address.  As above,
1211
14.0k
  // real address operands should have used a context-dependent parse routine,
1212
14.0k
  // so we treat any plain expression as an immediate.
1213
14.0k
  SMLoc StartLoc = Parser.getTok().getLoc();
1214
14.0k
  Register Reg1, Reg2;
1215
14.0k
  bool HaveReg1, HaveReg2;
1216
14.0k
  const MCExpr *Expr;
1217
14.0k
  const MCExpr *Length;
1218
14.0k
  if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Expr, Length))
1219
4
    return true;
1220
14.0k
  // If the register combination is not valid for any instruction, reject it.
1221
14.0k
  // Otherwise, fall back to reporting an unrecognized instruction.
1222
14.0k
  if (HaveReg1 && 
Reg1.Group != RegGR19
&&
Reg1.Group != RegV4
1223
14.0k
      && 
parseAddressRegister(Reg1)1
)
1224
1
    return true;
1225
14.0k
  if (HaveReg2 && 
parseAddressRegister(Reg2)10
)
1226
4
    return true;
1227
13.9k
1228
13.9k
  SMLoc EndLoc =
1229
13.9k
    SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1230
13.9k
  if (HaveReg1 || 
HaveReg213.9k
||
Length13.9k
)
1231
19
    Operands.push_back(SystemZOperand::createInvalid(StartLoc, EndLoc));
1232
13.9k
  else
1233
13.9k
    Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1234
13.9k
  return false;
1235
13.9k
}
1236
1237
static std::string SystemZMnemonicSpellCheck(StringRef S,
1238
                                             const FeatureBitset &FBS,
1239
                                             unsigned VariantID = 0);
1240
1241
bool SystemZAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1242
                                               OperandVector &Operands,
1243
                                               MCStreamer &Out,
1244
                                               uint64_t &ErrorInfo,
1245
24.7k
                                               bool MatchingInlineAsm) {
1246
24.7k
  MCInst Inst;
1247
24.7k
  unsigned MatchResult;
1248
24.7k
1249
24.7k
  FeatureBitset MissingFeatures;
1250
24.7k
  MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
1251
24.7k
                                     MissingFeatures, MatchingInlineAsm);
1252
24.7k
  switch (MatchResult) {
1253
24.7k
  case Match_Success:
1254
18.0k
    Inst.setLoc(IDLoc);
1255
18.0k
    Out.EmitInstruction(Inst, getSTI());
1256
18.0k
    return false;
1257
24.7k
1258
24.7k
  case Match_MissingFeature: {
1259
1.59k
    assert(MissingFeatures.any() && "Unknown missing feature!");
1260
1.59k
    // Special case the error message for the very common case where only
1261
1.59k
    // a single subtarget feature is missing
1262
1.59k
    std::string Msg = "instruction requires:";
1263
308k
    for (unsigned I = 0, E = MissingFeatures.size(); I != E; 
++I306k
) {
1264
306k
      if (MissingFeatures[I]) {
1265
1.59k
        Msg += " ";
1266
1.59k
        Msg += getSubtargetFeatureName(I);
1267
1.59k
      }
1268
306k
    }
1269
1.59k
    return Error(IDLoc, Msg);
1270
24.7k
  }
1271
24.7k
1272
24.7k
  case Match_InvalidOperand: {
1273
4.96k
    SMLoc ErrorLoc = IDLoc;
1274
4.96k
    if (ErrorInfo != ~0ULL) {
1275
4.96k
      if (ErrorInfo >= Operands.size())
1276
125
        return Error(IDLoc, "too few operands for instruction");
1277
4.83k
1278
4.83k
      ErrorLoc = ((SystemZOperand &)*Operands[ErrorInfo]).getStartLoc();
1279
4.83k
      if (ErrorLoc == SMLoc())
1280
0
        ErrorLoc = IDLoc;
1281
4.83k
    }
1282
4.96k
    
return Error(ErrorLoc, "invalid operand for instruction")4.83k
;
1283
4.96k
  }
1284
4.96k
1285
4.96k
  case Match_MnemonicFail: {
1286
95
    FeatureBitset FBS = ComputeAvailableFeatures(getSTI().getFeatureBits());
1287
95
    std::string Suggestion = SystemZMnemonicSpellCheck(
1288
95
      ((SystemZOperand &)*Operands[0]).getToken(), FBS);
1289
95
    return Error(IDLoc, "invalid instruction" + Suggestion,
1290
95
                 ((SystemZOperand &)*Operands[0]).getLocRange());
1291
0
  }
1292
0
  }
1293
0
1294
0
  llvm_unreachable("Unexpected match type");
1295
0
}
1296
1297
OperandMatchResultTy
1298
SystemZAsmParser::parsePCRel(OperandVector &Operands, int64_t MinVal,
1299
1.54k
                             int64_t MaxVal, bool AllowTLS) {
1300
1.54k
  MCContext &Ctx = getContext();
1301
1.54k
  MCStreamer &Out = getStreamer();
1302
1.54k
  const MCExpr *Expr;
1303
1.54k
  SMLoc StartLoc = Parser.getTok().getLoc();
1304
1.54k
  if (getParser().parseExpression(Expr))
1305
0
    return MatchOperand_NoMatch;
1306
1.54k
1307
1.54k
  // For consistency with the GNU assembler, treat immediates as offsets
1308
1.54k
  // from ".".
1309
1.54k
  if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
1310
665
    int64_t Value = CE->getValue();
1311
665
    if ((Value & 1) || 
Value < MinVal485
||
Value > MaxVal395
) {
1312
360
      Error(StartLoc, "offset out of range");
1313
360
      return MatchOperand_ParseFail;
1314
360
    }
1315
305
    MCSymbol *Sym = Ctx.createTempSymbol();
1316
305
    Out.EmitLabel(Sym);
1317
305
    const MCExpr *Base = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None,
1318
305
                                                 Ctx);
1319
305
    Expr = Value == 0 ? 
Base152
:
MCBinaryExpr::createAdd(Base, Expr, Ctx)153
;
1320
305
  }
1321
1.54k
1322
1.54k
  // Optionally match :tls_gdcall: or :tls_ldcall: followed by a TLS symbol.
1323
1.54k
  const MCExpr *Sym = nullptr;
1324
1.18k
  if (AllowTLS && 
getLexer().is(AsmToken::Colon)45
) {
1325
8
    Parser.Lex();
1326
8
1327
8
    if (Parser.getTok().isNot(AsmToken::Identifier)) {
1328
0
      Error(Parser.getTok().getLoc(), "unexpected token");
1329
0
      return MatchOperand_ParseFail;
1330
0
    }
1331
8
1332
8
    MCSymbolRefExpr::VariantKind Kind = MCSymbolRefExpr::VK_None;
1333
8
    StringRef Name = Parser.getTok().getString();
1334
8
    if (Name == "tls_gdcall")
1335
4
      Kind = MCSymbolRefExpr::VK_TLSGD;
1336
4
    else if (Name == "tls_ldcall")
1337
4
      Kind = MCSymbolRefExpr::VK_TLSLDM;
1338
0
    else {
1339
0
      Error(Parser.getTok().getLoc(), "unknown TLS tag");
1340
0
      return MatchOperand_ParseFail;
1341
0
    }
1342
8
    Parser.Lex();
1343
8
1344
8
    if (Parser.getTok().isNot(AsmToken::Colon)) {
1345
0
      Error(Parser.getTok().getLoc(), "unexpected token");
1346
0
      return MatchOperand_ParseFail;
1347
0
    }
1348
8
    Parser.Lex();
1349
8
1350
8
    if (Parser.getTok().isNot(AsmToken::Identifier)) {
1351
0
      Error(Parser.getTok().getLoc(), "unexpected token");
1352
0
      return MatchOperand_ParseFail;
1353
0
    }
1354
8
1355
8
    StringRef Identifier = Parser.getTok().getString();
1356
8
    Sym = MCSymbolRefExpr::create(Ctx.getOrCreateSymbol(Identifier),
1357
8
                                  Kind, Ctx);
1358
8
    Parser.Lex();
1359
8
  }
1360
1.18k
1361
1.18k
  SMLoc EndLoc =
1362
1.18k
    SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1363
1.18k
1364
1.18k
  if (AllowTLS)
1365
45
    Operands.push_back(SystemZOperand::createImmTLS(Expr, Sym,
1366
45
                                                    StartLoc, EndLoc));
1367
1.14k
  else
1368
1.14k
    Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1369
1.18k
1370
1.18k
  return MatchOperand_Success;
1371
1.18k
}
1372
1373
// Force static initialization.
1374
91.7k
extern "C" void LLVMInitializeSystemZAsmParser() {
1375
91.7k
  RegisterMCAsmParser<SystemZAsmParser> X(getTheSystemZTarget());
1376
91.7k
}