Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp
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//===-- SystemZMCTargetDesc.cpp - SystemZ target descriptions -------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "SystemZMCTargetDesc.h"
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#include "SystemZInstPrinter.h"
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#include "SystemZMCAsmInfo.h"
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#include "TargetInfo/SystemZTargetInfo.h"
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#include "llvm/MC/MCDwarf.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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#define GET_INSTRINFO_MC_DESC
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#include "SystemZGenInstrInfo.inc"
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#define GET_SUBTARGETINFO_MC_DESC
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#include "SystemZGenSubtargetInfo.inc"
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#define GET_REGINFO_MC_DESC
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#include "SystemZGenRegisterInfo.inc"
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const unsigned SystemZMC::GR32Regs[16] = {
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  SystemZ::R0L, SystemZ::R1L, SystemZ::R2L, SystemZ::R3L,
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  SystemZ::R4L, SystemZ::R5L, SystemZ::R6L, SystemZ::R7L,
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  SystemZ::R8L, SystemZ::R9L, SystemZ::R10L, SystemZ::R11L,
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  SystemZ::R12L, SystemZ::R13L, SystemZ::R14L, SystemZ::R15L
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};
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const unsigned SystemZMC::GRH32Regs[16] = {
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  SystemZ::R0H, SystemZ::R1H, SystemZ::R2H, SystemZ::R3H,
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  SystemZ::R4H, SystemZ::R5H, SystemZ::R6H, SystemZ::R7H,
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  SystemZ::R8H, SystemZ::R9H, SystemZ::R10H, SystemZ::R11H,
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  SystemZ::R12H, SystemZ::R13H, SystemZ::R14H, SystemZ::R15H
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};
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const unsigned SystemZMC::GR64Regs[16] = {
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  SystemZ::R0D, SystemZ::R1D, SystemZ::R2D, SystemZ::R3D,
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  SystemZ::R4D, SystemZ::R5D, SystemZ::R6D, SystemZ::R7D,
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  SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D,
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  SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D
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};
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const unsigned SystemZMC::GR128Regs[16] = {
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  SystemZ::R0Q, 0, SystemZ::R2Q, 0,
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  SystemZ::R4Q, 0, SystemZ::R6Q, 0,
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  SystemZ::R8Q, 0, SystemZ::R10Q, 0,
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  SystemZ::R12Q, 0, SystemZ::R14Q, 0
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};
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const unsigned SystemZMC::FP32Regs[16] = {
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  SystemZ::F0S, SystemZ::F1S, SystemZ::F2S, SystemZ::F3S,
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  SystemZ::F4S, SystemZ::F5S, SystemZ::F6S, SystemZ::F7S,
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  SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S,
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  SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S
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};
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const unsigned SystemZMC::FP64Regs[16] = {
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  SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D,
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  SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D,
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  SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D,
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  SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D
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};
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const unsigned SystemZMC::FP128Regs[16] = {
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  SystemZ::F0Q, SystemZ::F1Q, 0, 0,
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  SystemZ::F4Q, SystemZ::F5Q, 0, 0,
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  SystemZ::F8Q, SystemZ::F9Q, 0, 0,
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  SystemZ::F12Q, SystemZ::F13Q, 0, 0
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};
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const unsigned SystemZMC::VR32Regs[32] = {
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  SystemZ::F0S, SystemZ::F1S, SystemZ::F2S, SystemZ::F3S,
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  SystemZ::F4S, SystemZ::F5S, SystemZ::F6S, SystemZ::F7S,
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  SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S,
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  SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S,
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  SystemZ::F16S, SystemZ::F17S, SystemZ::F18S, SystemZ::F19S,
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  SystemZ::F20S, SystemZ::F21S, SystemZ::F22S, SystemZ::F23S,
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  SystemZ::F24S, SystemZ::F25S, SystemZ::F26S, SystemZ::F27S,
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  SystemZ::F28S, SystemZ::F29S, SystemZ::F30S, SystemZ::F31S
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};
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const unsigned SystemZMC::VR64Regs[32] = {
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  SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D,
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  SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D,
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  SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D,
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  SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D,
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  SystemZ::F16D, SystemZ::F17D, SystemZ::F18D, SystemZ::F19D,
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  SystemZ::F20D, SystemZ::F21D, SystemZ::F22D, SystemZ::F23D,
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  SystemZ::F24D, SystemZ::F25D, SystemZ::F26D, SystemZ::F27D,
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  SystemZ::F28D, SystemZ::F29D, SystemZ::F30D, SystemZ::F31D
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};
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const unsigned SystemZMC::VR128Regs[32] = {
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  SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3,
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  SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7,
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  SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11,
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  SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15,
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  SystemZ::V16, SystemZ::V17, SystemZ::V18, SystemZ::V19,
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  SystemZ::V20, SystemZ::V21, SystemZ::V22, SystemZ::V23,
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  SystemZ::V24, SystemZ::V25, SystemZ::V26, SystemZ::V27,
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  SystemZ::V28, SystemZ::V29, SystemZ::V30, SystemZ::V31
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};
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const unsigned SystemZMC::AR32Regs[16] = {
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  SystemZ::A0, SystemZ::A1, SystemZ::A2, SystemZ::A3,
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  SystemZ::A4, SystemZ::A5, SystemZ::A6, SystemZ::A7,
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  SystemZ::A8, SystemZ::A9, SystemZ::A10, SystemZ::A11,
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  SystemZ::A12, SystemZ::A13, SystemZ::A14, SystemZ::A15
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};
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const unsigned SystemZMC::CR64Regs[16] = {
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  SystemZ::C0, SystemZ::C1, SystemZ::C2, SystemZ::C3,
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  SystemZ::C4, SystemZ::C5, SystemZ::C6, SystemZ::C7,
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  SystemZ::C8, SystemZ::C9, SystemZ::C10, SystemZ::C11,
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  SystemZ::C12, SystemZ::C13, SystemZ::C14, SystemZ::C15
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};
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unsigned SystemZMC::getFirstReg(unsigned Reg) {
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  static unsigned Map[SystemZ::NUM_TARGET_REGS];
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  static bool Initialized = false;
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  if (!Initialized) {
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    for (unsigned I = 0; I < 16; 
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) {
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      Map[GR32Regs[I]] = I;
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      Map[GRH32Regs[I]] = I;
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      Map[GR64Regs[I]] = I;
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      Map[GR128Regs[I]] = I;
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      Map[FP128Regs[I]] = I;
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      Map[AR32Regs[I]] = I;
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    }
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    for (unsigned I = 0; I < 32; 
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) {
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      Map[VR32Regs[I]] = I;
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      Map[VR64Regs[I]] = I;
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      Map[VR128Regs[I]] = I;
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    }
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  }
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  assert(Reg < SystemZ::NUM_TARGET_REGS);
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  return Map[Reg];
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}
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static MCAsmInfo *createSystemZMCAsmInfo(const MCRegisterInfo &MRI,
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                                         const Triple &TT) {
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  MCAsmInfo *MAI = new SystemZMCAsmInfo(TT);
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  MCCFIInstruction Inst =
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      MCCFIInstruction::createDefCfa(nullptr,
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                                     MRI.getDwarfRegNum(SystemZ::R15D, true),
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                                     SystemZMC::CFAOffsetFromInitialSP);
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  MAI->addInitialFrameState(Inst);
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  return MAI;
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}
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static MCInstrInfo *createSystemZMCInstrInfo() {
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  MCInstrInfo *X = new MCInstrInfo();
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  InitSystemZMCInstrInfo(X);
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  return X;
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}
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static MCRegisterInfo *createSystemZMCRegisterInfo(const Triple &TT) {
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  MCRegisterInfo *X = new MCRegisterInfo();
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  InitSystemZMCRegisterInfo(X, SystemZ::R14D);
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  return X;
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}
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static MCSubtargetInfo *
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createSystemZMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
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  return createSystemZMCSubtargetInfoImpl(TT, CPU, FS);
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}
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static MCInstPrinter *createSystemZMCInstPrinter(const Triple &T,
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                                                 unsigned SyntaxVariant,
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                                                 const MCAsmInfo &MAI,
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                                                 const MCInstrInfo &MII,
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                                                 const MCRegisterInfo &MRI) {
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  return new SystemZInstPrinter(MAI, MII, MRI);
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}
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extern "C" void LLVMInitializeSystemZTargetMC() {
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  // Register the MCAsmInfo.
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  TargetRegistry::RegisterMCAsmInfo(getTheSystemZTarget(),
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                                    createSystemZMCAsmInfo);
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  // Register the MCCodeEmitter.
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  TargetRegistry::RegisterMCCodeEmitter(getTheSystemZTarget(),
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                                        createSystemZMCCodeEmitter);
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  // Register the MCInstrInfo.
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  TargetRegistry::RegisterMCInstrInfo(getTheSystemZTarget(),
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                                      createSystemZMCInstrInfo);
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  // Register the MCRegisterInfo.
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  TargetRegistry::RegisterMCRegInfo(getTheSystemZTarget(),
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                                    createSystemZMCRegisterInfo);
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  // Register the MCSubtargetInfo.
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  TargetRegistry::RegisterMCSubtargetInfo(getTheSystemZTarget(),
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                                          createSystemZMCSubtargetInfo);
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  // Register the MCAsmBackend.
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  TargetRegistry::RegisterMCAsmBackend(getTheSystemZTarget(),
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                                       createSystemZMCAsmBackend);
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  // Register the MCInstPrinter.
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  TargetRegistry::RegisterMCInstPrinter(getTheSystemZTarget(),
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                                        createSystemZMCInstPrinter);
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}