Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/SystemZ/SystemZElimCompare.cpp
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Source (jump to first uncovered line)
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//===-- SystemZElimCompare.cpp - Eliminate comparison instructions --------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This pass:
10
// (1) tries to remove compares if CC already contains the required information
11
// (2) fuses compares and branches into COMPARE AND BRANCH instructions
12
//
13
//===----------------------------------------------------------------------===//
14
15
#include "SystemZ.h"
16
#include "SystemZInstrInfo.h"
17
#include "SystemZTargetMachine.h"
18
#include "llvm/ADT/SmallVector.h"
19
#include "llvm/ADT/Statistic.h"
20
#include "llvm/ADT/StringRef.h"
21
#include "llvm/CodeGen/MachineBasicBlock.h"
22
#include "llvm/CodeGen/MachineFunction.h"
23
#include "llvm/CodeGen/MachineFunctionPass.h"
24
#include "llvm/CodeGen/MachineInstr.h"
25
#include "llvm/CodeGen/MachineInstrBuilder.h"
26
#include "llvm/CodeGen/MachineOperand.h"
27
#include "llvm/CodeGen/TargetRegisterInfo.h"
28
#include "llvm/CodeGen/TargetSubtargetInfo.h"
29
#include "llvm/MC/MCInstrDesc.h"
30
#include <cassert>
31
#include <cstdint>
32
33
using namespace llvm;
34
35
#define DEBUG_TYPE "systemz-elim-compare"
36
37
STATISTIC(BranchOnCounts, "Number of branch-on-count instructions");
38
STATISTIC(LoadAndTraps, "Number of load-and-trap instructions");
39
STATISTIC(EliminatedComparisons, "Number of eliminated comparisons");
40
STATISTIC(FusedComparisons, "Number of fused compare-and-branch instructions");
41
42
namespace {
43
44
// Represents the references to a particular register in one or more
45
// instructions.
46
struct Reference {
47
2.75k
  Reference() = default;
48
49
1.62k
  Reference &operator|=(const Reference &Other) {
50
1.62k
    Def |= Other.Def;
51
1.62k
    Use |= Other.Use;
52
1.62k
    return *this;
53
1.62k
  }
54
55
528
  explicit operator bool() const { return Def || 
Use518
; }
56
57
  // True if the register is defined or used in some form, either directly or
58
  // via a sub- or super-register.
59
  bool Def = false;
60
  bool Use = false;
61
};
62
63
class SystemZElimCompare : public MachineFunctionPass {
64
public:
65
  static char ID;
66
67
  SystemZElimCompare(const SystemZTargetMachine &tm)
68
1.00k
    : MachineFunctionPass(ID) {}
69
70
9.10k
  StringRef getPassName() const override {
71
9.10k
    return "SystemZ Comparison Elimination";
72
9.10k
  }
73
74
  bool processBlock(MachineBasicBlock &MBB);
75
  bool runOnMachineFunction(MachineFunction &F) override;
76
77
999
  MachineFunctionProperties getRequiredProperties() const override {
78
999
    return MachineFunctionProperties().set(
79
999
        MachineFunctionProperties::Property::NoVRegs);
80
999
  }
81
82
private:
83
  Reference getRegReferences(MachineInstr &MI, unsigned Reg);
84
  bool convertToBRCT(MachineInstr &MI, MachineInstr &Compare,
85
                     SmallVectorImpl<MachineInstr *> &CCUsers);
86
  bool convertToLoadAndTrap(MachineInstr &MI, MachineInstr &Compare,
87
                            SmallVectorImpl<MachineInstr *> &CCUsers);
88
  bool convertToLoadAndTest(MachineInstr &MI, MachineInstr &Compare,
89
                            SmallVectorImpl<MachineInstr *> &CCUsers);
90
  bool adjustCCMasksForInstr(MachineInstr &MI, MachineInstr &Compare,
91
                             SmallVectorImpl<MachineInstr *> &CCUsers,
92
                             unsigned ConvOpc = 0);
93
  bool optimizeCompareZero(MachineInstr &Compare,
94
                           SmallVectorImpl<MachineInstr *> &CCUsers);
95
  bool fuseCompareOperations(MachineInstr &Compare,
96
                             SmallVectorImpl<MachineInstr *> &CCUsers);
97
98
  const SystemZInstrInfo *TII = nullptr;
99
  const TargetRegisterInfo *TRI = nullptr;
100
};
101
102
char SystemZElimCompare::ID = 0;
103
104
} // end anonymous namespace
105
106
// Return true if CC is live out of MBB.
107
11.0k
static bool isCCLiveOut(MachineBasicBlock &MBB) {
108
15.0k
  for (auto SI = MBB.succ_begin(), SE = MBB.succ_end(); SI != SE; 
++SI3.99k
)
109
4.05k
    if ((*SI)->isLiveIn(SystemZ::CC))
110
58
      return true;
111
11.0k
  
return false10.9k
;
112
11.0k
}
113
114
// Returns true if MI is an instruction whose output equals the value in Reg.
115
1.04k
static bool preservesValueOf(MachineInstr &MI, unsigned Reg) {
116
1.04k
  switch (MI.getOpcode()) {
117
1.04k
  case SystemZ::LR:
118
30
  case SystemZ::LGR:
119
30
  case SystemZ::LGFR:
120
30
  case SystemZ::LTR:
121
30
  case SystemZ::LTGR:
122
30
  case SystemZ::LTGFR:
123
30
  case SystemZ::LER:
124
30
  case SystemZ::LDR:
125
30
  case SystemZ::LXR:
126
30
  case SystemZ::LTEBR:
127
30
  case SystemZ::LTDBR:
128
30
  case SystemZ::LTXBR:
129
30
    if (MI.getOperand(1).getReg() == Reg)
130
15
      return true;
131
1.02k
  }
132
1.02k
133
1.02k
  return false;
134
1.02k
}
135
136
// Return true if any CC result of MI would (perhaps after conversion)
137
// reflect the value of Reg.
138
967
static bool resultTests(MachineInstr &MI, unsigned Reg) {
139
967
  if (MI.getNumOperands() > 0 && MI.getOperand(0).isReg() &&
140
967
      
MI.getOperand(0).isDef()739
&&
MI.getOperand(0).getReg() == Reg584
)
141
160
    return true;
142
807
143
807
  return (preservesValueOf(MI, Reg));
144
807
}
145
146
// Describe the references to Reg or any of its aliases in MI.
147
2.08k
Reference SystemZElimCompare::getRegReferences(MachineInstr &MI, unsigned Reg) {
148
2.08k
  Reference Ref;
149
2.08k
  if (MI.isDebugInstr())
150
6
    return Ref;
151
2.07k
152
9.44k
  
for (unsigned I = 0, E = MI.getNumOperands(); 2.07k
I != E;
++I7.37k
) {
153
7.37k
    const MachineOperand &MO = MI.getOperand(I);
154
7.37k
    if (MO.isReg()) {
155
4.52k
      if (unsigned MOReg = MO.getReg()) {
156
3.64k
        if (TRI->regsOverlap(MOReg, Reg)) {
157
401
          if (MO.isUse())
158
264
            Ref.Use = true;
159
137
          else if (MO.isDef())
160
137
            Ref.Def = true;
161
401
        }
162
3.64k
      }
163
4.52k
    }
164
7.37k
  }
165
2.07k
  return Ref;
166
2.07k
}
167
168
// Return true if this is a load and test which can be optimized the
169
// same way as compare instruction.
170
65.4k
static bool isLoadAndTestAsCmp(MachineInstr &MI) {
171
65.4k
  // If we during isel used a load-and-test as a compare with 0, the
172
65.4k
  // def operand is dead.
173
65.4k
  return (MI.getOpcode() == SystemZ::LTEBR ||
174
65.4k
          
MI.getOpcode() == SystemZ::LTDBR65.4k
||
175
65.4k
          
MI.getOpcode() == SystemZ::LTXBR65.4k
) &&
176
65.4k
         
MI.getOperand(0).isDead()27
;
177
65.4k
}
178
179
// Return the source register of Compare, which is the unknown value
180
// being tested.
181
376
static unsigned getCompareSourceReg(MachineInstr &Compare) {
182
376
  unsigned reg = 0;
183
376
  if (Compare.isCompare())
184
368
    reg = Compare.getOperand(0).getReg();
185
8
  else if (isLoadAndTestAsCmp(Compare))
186
8
    reg = Compare.getOperand(1).getReg();
187
376
  assert(reg);
188
376
189
376
  return reg;
190
376
}
191
192
// Compare compares the result of MI against zero.  If MI is an addition
193
// of -1 and if CCUsers is a single branch on nonzero, eliminate the addition
194
// and convert the branch to a BRCT(G) or BRCTH.  Return true on success.
195
bool SystemZElimCompare::convertToBRCT(
196
    MachineInstr &MI, MachineInstr &Compare,
197
160
    SmallVectorImpl<MachineInstr *> &CCUsers) {
198
160
  // Check whether we have an addition of -1.
199
160
  unsigned Opcode = MI.getOpcode();
200
160
  unsigned BRCT;
201
160
  if (Opcode == SystemZ::AHI)
202
9
    BRCT = SystemZ::BRCT;
203
151
  else if (Opcode == SystemZ::AGHI)
204
9
    BRCT = SystemZ::BRCTG;
205
142
  else if (Opcode == SystemZ::AIH)
206
2
    BRCT = SystemZ::BRCTH;
207
140
  else
208
140
    return false;
209
20
  if (MI.getOperand(2).getImm() != -1)
210
1
    return false;
211
19
212
19
  // Check whether we have a single JLH.
213
19
  if (CCUsers.size() != 1)
214
0
    return false;
215
19
  MachineInstr *Branch = CCUsers[0];
216
19
  if (Branch->getOpcode() != SystemZ::BRC ||
217
19
      Branch->getOperand(0).getImm() != SystemZ::CCMASK_ICMP ||
218
19
      Branch->getOperand(1).getImm() != SystemZ::CCMASK_CMP_NE)
219
0
    return false;
220
19
221
19
  // We already know that there are no references to the register between
222
19
  // MI and Compare.  Make sure that there are also no references between
223
19
  // Compare and Branch.
224
19
  unsigned SrcReg = getCompareSourceReg(Compare);
225
19
  MachineBasicBlock::iterator MBBI = Compare, MBBE = Branch;
226
28
  for (++MBBI; MBBI != MBBE; 
++MBBI9
)
227
9
    if (getRegReferences(*MBBI, SrcReg))
228
0
      return false;
229
19
230
19
  // The transformation is OK.  Rebuild Branch as a BRCT(G) or BRCTH.
231
19
  MachineOperand Target(Branch->getOperand(2));
232
95
  while (Branch->getNumOperands())
233
76
    Branch->RemoveOperand(0);
234
19
  Branch->setDesc(TII->get(BRCT));
235
19
  MachineInstrBuilder MIB(*Branch->getParent()->getParent(), Branch);
236
19
  MIB.add(MI.getOperand(0)).add(MI.getOperand(1)).add(Target);
237
19
  // Add a CC def to BRCT(G), since we may have to split them again if the
238
19
  // branch displacement overflows.  BRCTH has a 32-bit displacement, so
239
19
  // this is not necessary there.
240
19
  if (BRCT != SystemZ::BRCTH)
241
17
    MIB.addReg(SystemZ::CC, RegState::ImplicitDefine | RegState::Dead);
242
19
  MI.eraseFromParent();
243
19
  return true;
244
19
}
245
246
// Compare compares the result of MI against zero.  If MI is a suitable load
247
// instruction and if CCUsers is a single conditional trap on zero, eliminate
248
// the load and convert the branch to a load-and-trap.  Return true on success.
249
bool SystemZElimCompare::convertToLoadAndTrap(
250
    MachineInstr &MI, MachineInstr &Compare,
251
141
    SmallVectorImpl<MachineInstr *> &CCUsers) {
252
141
  unsigned LATOpcode = TII->getLoadAndTrap(MI.getOpcode());
253
141
  if (!LATOpcode)
254
115
    return false;
255
26
256
26
  // Check whether we have a single CondTrap that traps on zero.
257
26
  if (CCUsers.size() != 1)
258
0
    return false;
259
26
  MachineInstr *Branch = CCUsers[0];
260
26
  if (Branch->getOpcode() != SystemZ::CondTrap ||
261
26
      
Branch->getOperand(0).getImm() != SystemZ::CCMASK_ICMP21
||
262
26
      
Branch->getOperand(1).getImm() != SystemZ::CCMASK_CMP_EQ21
)
263
5
    return false;
264
21
265
21
  // We already know that there are no references to the register between
266
21
  // MI and Compare.  Make sure that there are also no references between
267
21
  // Compare and Branch.
268
21
  unsigned SrcReg = getCompareSourceReg(Compare);
269
21
  MachineBasicBlock::iterator MBBI = Compare, MBBE = Branch;
270
22
  for (++MBBI; MBBI != MBBE; 
++MBBI1
)
271
1
    if (getRegReferences(*MBBI, SrcReg))
272
0
      return false;
273
21
274
21
  // The transformation is OK.  Rebuild Branch as a load-and-trap.
275
84
  
while (21
Branch->getNumOperands())
276
63
    Branch->RemoveOperand(0);
277
21
  Branch->setDesc(TII->get(LATOpcode));
278
21
  MachineInstrBuilder(*Branch->getParent()->getParent(), Branch)
279
21
      .add(MI.getOperand(0))
280
21
      .add(MI.getOperand(1))
281
21
      .add(MI.getOperand(2))
282
21
      .add(MI.getOperand(3));
283
21
  MI.eraseFromParent();
284
21
  return true;
285
21
}
286
287
// If MI is a load instruction, try to convert it into a LOAD AND TEST.
288
// Return true on success.
289
bool SystemZElimCompare::convertToLoadAndTest(
290
    MachineInstr &MI, MachineInstr &Compare,
291
127
    SmallVectorImpl<MachineInstr *> &CCUsers) {
292
127
293
127
  // Try to adjust CC masks for the LOAD AND TEST opcode that could replace MI.
294
127
  unsigned Opcode = TII->getLoadAndTest(MI.getOpcode());
295
127
  if (!Opcode || 
!adjustCCMasksForInstr(MI, Compare, CCUsers, Opcode)45
)
296
83
    return false;
297
44
298
44
  // Rebuild to get the CC operand in the right place.
299
44
  auto MIB = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), TII->get(Opcode));
300
44
  for (const auto &MO : MI.operands())
301
116
    MIB.add(MO);
302
44
  MIB.setMemRefs(MI.memoperands());
303
44
  MI.eraseFromParent();
304
44
305
44
  return true;
306
44
}
307
308
// The CC users in CCUsers are testing the result of a comparison of some
309
// value X against zero and we know that any CC value produced by MI would
310
// also reflect the value of X.  ConvOpc may be used to pass the transfomed
311
// opcode MI will have if this succeeds.  Try to adjust CCUsers so that they
312
// test the result of MI directly, returning true on success.  Leave
313
// everything unchanged on failure.
314
bool SystemZElimCompare::adjustCCMasksForInstr(
315
    MachineInstr &MI, MachineInstr &Compare,
316
    SmallVectorImpl<MachineInstr *> &CCUsers,
317
128
    unsigned ConvOpc) {
318
128
  int Opcode = (ConvOpc ? 
ConvOpc45
:
MI.getOpcode()83
);
319
128
  const MCInstrDesc &Desc = TII->get(Opcode);
320
128
  unsigned MIFlags = Desc.TSFlags;
321
128
322
128
  // See which compare-style condition codes are available.
323
128
  unsigned ReusableCCMask = SystemZII::getCompareZeroCCMask(MIFlags);
324
128
325
128
  // For unsigned comparisons with zero, only equality makes sense.
326
128
  unsigned CompareFlags = Compare.getDesc().TSFlags;
327
128
  if (CompareFlags & SystemZII::IsLogical)
328
3
    ReusableCCMask &= SystemZ::CCMASK_CMP_EQ;
329
128
330
128
  if (ReusableCCMask == 0)
331
34
    return false;
332
94
333
94
  unsigned CCValues = SystemZII::getCCValues(MIFlags);
334
94
  assert((ReusableCCMask & ~CCValues) == 0 && "Invalid CCValues");
335
94
336
94
  bool MIEquivalentToCmp =
337
94
    (ReusableCCMask == CCValues &&
338
94
     
CCValues == SystemZII::getCCValues(CompareFlags)59
);
339
94
340
94
  if (!MIEquivalentToCmp) {
341
35
    // Now check whether these flags are enough for all users.
342
35
    SmallVector<MachineOperand *, 4> AlterMasks;
343
63
    for (unsigned int I = 0, E = CCUsers.size(); I != E; 
++I28
) {
344
35
      MachineInstr *MI = CCUsers[I];
345
35
346
35
      // Fail if this isn't a use of CC that we understand.
347
35
      unsigned Flags = MI->getDesc().TSFlags;
348
35
      unsigned FirstOpNum;
349
35
      if (Flags & SystemZII::CCMaskFirst)
350
26
        FirstOpNum = 0;
351
9
      else if (Flags & SystemZII::CCMaskLast)
352
9
        FirstOpNum = MI->getNumExplicitOperands() - 2;
353
0
      else
354
0
        return false;
355
35
356
35
      // Check whether the instruction predicate treats all CC values
357
35
      // outside of ReusableCCMask in the same way.  In that case it
358
35
      // doesn't matter what those CC values mean.
359
35
      unsigned CCValid = MI->getOperand(FirstOpNum).getImm();
360
35
      unsigned CCMask = MI->getOperand(FirstOpNum + 1).getImm();
361
35
      unsigned OutValid = ~ReusableCCMask & CCValid;
362
35
      unsigned OutMask = ~ReusableCCMask & CCMask;
363
35
      if (OutMask != 0 && 
OutMask != OutValid25
)
364
7
        return false;
365
28
366
28
      AlterMasks.push_back(&MI->getOperand(FirstOpNum));
367
28
      AlterMasks.push_back(&MI->getOperand(FirstOpNum + 1));
368
28
    }
369
35
370
35
    // All users are OK.  Adjust the masks for MI.
371
56
    
for (unsigned I = 0, E = AlterMasks.size(); 28
I != E;
I += 228
) {
372
28
      AlterMasks[I]->setImm(CCValues);
373
28
      unsigned CCMask = AlterMasks[I + 1]->getImm();
374
28
      if (CCMask & ~ReusableCCMask)
375
18
        AlterMasks[I + 1]->setImm((CCMask & ReusableCCMask) |
376
18
                                  (CCValues & ~ReusableCCMask));
377
28
    }
378
28
  }
379
94
380
94
  // CC is now live after MI.
381
94
  
if (87
!ConvOpc87
) {
382
43
    int CCDef = MI.findRegisterDefOperandIdx(SystemZ::CC, false, true, TRI);
383
43
    assert(CCDef >= 0 && "Couldn't find CC set");
384
43
    MI.getOperand(CCDef).setIsDead(false);
385
43
  }
386
87
387
87
  // Check if MI lies before Compare.
388
87
  bool BeforeCmp = false;
389
87
  MachineBasicBlock::iterator MBBI = MI, MBBE = MI.getParent()->end();
390
106
  for (++MBBI; MBBI != MBBE; 
++MBBI19
)
391
101
    if (MBBI == Compare) {
392
82
      BeforeCmp = true;
393
82
      break;
394
82
    }
395
87
396
87
  // Clear any intervening kills of CC.
397
87
  if (BeforeCmp) {
398
82
    MachineBasicBlock::iterator MBBI = MI, MBBE = Compare;
399
91
    for (++MBBI; MBBI != MBBE; 
++MBBI9
)
400
9
      MBBI->clearRegisterKills(SystemZ::CC, TRI);
401
82
  }
402
87
403
87
  return true;
404
94
}
405
406
// Return true if Compare is a comparison against zero.
407
1.66k
static bool isCompareZero(MachineInstr &Compare) {
408
1.66k
  switch (Compare.getOpcode()) {
409
1.66k
  case SystemZ::LTEBRCompare:
410
32
  case SystemZ::LTDBRCompare:
411
32
  case SystemZ::LTXBRCompare:
412
32
    return true;
413
32
414
1.63k
  default:
415
1.63k
    if (isLoadAndTestAsCmp(Compare))
416
8
      return true;
417
1.62k
    return Compare.getNumExplicitOperands() == 2 &&
418
1.62k
           
Compare.getOperand(1).isImm()1.21k
&&
Compare.getOperand(1).getImm() == 0743
;
419
1.66k
  }
420
1.66k
}
421
422
// Try to optimize cases where comparison instruction Compare is testing
423
// a value against zero.  Return true on success and if Compare should be
424
// deleted as dead.  CCUsers is the list of instructions that use the CC
425
// value produced by Compare.
426
bool SystemZElimCompare::optimizeCompareZero(
427
1.66k
    MachineInstr &Compare, SmallVectorImpl<MachineInstr *> &CCUsers) {
428
1.66k
  if (!isCompareZero(Compare))
429
1.32k
    return false;
430
336
431
336
  // Search back for CC results that are based on the first operand.
432
336
  unsigned SrcReg = getCompareSourceReg(Compare);
433
336
  MachineBasicBlock &MBB = *Compare.getParent();
434
336
  Reference CCRefs;
435
336
  Reference SrcRefs;
436
336
  for (MachineBasicBlock::reverse_iterator MBBI =
437
336
         std::next(MachineBasicBlock::reverse_iterator(&Compare)),
438
1.11k
         MBBE = MBB.rend(); MBBI != MBBE;) {
439
967
    MachineInstr &MI = *MBBI++;
440
967
    if (resultTests(MI, SrcReg)) {
441
170
      // Try to remove both MI and Compare by converting a branch to BRCT(G).
442
170
      // or a load-and-trap instruction.  We don't care in this case whether
443
170
      // CC is modified between MI and Compare.
444
170
      if (!CCRefs.Use && !SrcRefs) {
445
160
        if (convertToBRCT(MI, Compare, CCUsers)) {
446
19
          BranchOnCounts += 1;
447
19
          return true;
448
19
        }
449
141
        if (convertToLoadAndTrap(MI, Compare, CCUsers)) {
450
21
          LoadAndTraps += 1;
451
21
          return true;
452
21
        }
453
130
      }
454
130
      // Try to eliminate Compare by reusing a CC result from MI.
455
130
      if ((!CCRefs && 
convertToLoadAndTest(MI, Compare, CCUsers)122
) ||
456
130
          
(91
!CCRefs.Def91
&&
adjustCCMasksForInstr(MI, Compare, CCUsers)83
)) {
457
82
        EliminatedComparisons += 1;
458
82
        return true;
459
82
      }
460
845
    }
461
845
    SrcRefs |= getRegReferences(MI, SrcReg);
462
845
    if (SrcRefs.Def)
463
66
      break;
464
779
    CCRefs |= getRegReferences(MI, SystemZ::CC);
465
779
    if (CCRefs.Use && 
CCRefs.Def13
)
466
5
      break;
467
779
  }
468
336
469
336
  // Also do a forward search to handle cases where an instruction after the
470
336
  // compare can be converted, like
471
336
  // LTEBRCompare %f0s, %f0s; %f2s = LER %f0s  =>  LTEBRCompare %f2s, %f0s
472
336
  for (MachineBasicBlock::iterator MBBI =
473
214
         std::next(MachineBasicBlock::iterator(&Compare)), MBBE = MBB.end();
474
234
       MBBI != MBBE;) {
475
234
    MachineInstr &MI = *MBBI++;
476
234
    if (preservesValueOf(MI, SrcReg)) {
477
5
      // Try to eliminate Compare by reusing a CC result from MI.
478
5
      if (convertToLoadAndTest(MI, Compare, CCUsers)) {
479
5
        EliminatedComparisons += 1;
480
5
        return true;
481
5
      }
482
229
    }
483
229
    if (getRegReferences(MI, SrcReg).Def)
484
11
      return false;
485
218
    if (getRegReferences(MI, SystemZ::CC))
486
198
      return false;
487
218
  }
488
214
489
214
  
return false0
;
490
214
}
491
492
// Try to fuse comparison instruction Compare into a later branch.
493
// Return true on success and if Compare is therefore redundant.
494
bool SystemZElimCompare::fuseCompareOperations(
495
1.53k
    MachineInstr &Compare, SmallVectorImpl<MachineInstr *> &CCUsers) {
496
1.53k
  // See whether we have a single branch with which to fuse.
497
1.53k
  if (CCUsers.size() != 1)
498
9
    return false;
499
1.52k
  MachineInstr *Branch = CCUsers[0];
500
1.52k
  SystemZII::FusedCompareType Type;
501
1.52k
  switch (Branch->getOpcode()) {
502
1.52k
  case SystemZ::BRC:
503
599
    Type = SystemZII::CompareAndBranch;
504
599
    break;
505
1.52k
  case SystemZ::CondReturn:
506
542
    Type = SystemZII::CompareAndReturn;
507
542
    break;
508
1.52k
  case SystemZ::CallBCR:
509
23
    Type = SystemZII::CompareAndSibcall;
510
23
    break;
511
1.52k
  case SystemZ::CondTrap:
512
13
    Type = SystemZII::CompareAndTrap;
513
13
    break;
514
1.52k
  default:
515
349
    return false;
516
1.17k
  }
517
1.17k
518
1.17k
  // See whether we have a comparison that can be fused.
519
1.17k
  unsigned FusedOpcode =
520
1.17k
      TII->getFusedCompare(Compare.getOpcode(), Type, &Compare);
521
1.17k
  if (!FusedOpcode)
522
786
    return false;
523
391
524
391
  // Make sure that the operands are available at the branch.
525
391
  // SrcReg2 is the register if the source operand is a register,
526
391
  // 0 if the source operand is immediate, and the base register
527
391
  // if the source operand is memory (index is not supported).
528
391
  Register SrcReg = Compare.getOperand(0).getReg();
529
391
  Register SrcReg2 =
530
391
    Compare.getOperand(1).isReg() ? 
Compare.getOperand(1).getReg()177
:
Register()214
;
531
391
  MachineBasicBlock::iterator MBBI = Compare, MBBE = Branch;
532
425
  for (++MBBI; MBBI != MBBE; 
++MBBI34
)
533
37
    if (MBBI->modifiesRegister(SrcReg, TRI) ||
534
37
        
(34
SrcReg234
&&
MBBI->modifiesRegister(SrcReg2, TRI)23
))
535
3
      return false;
536
391
537
391
  // Read the branch mask, target (if applicable), regmask (if applicable).
538
391
  MachineOperand CCMask(MBBI->getOperand(1));
539
388
  assert((CCMask.getImm() & ~SystemZ::CCMASK_ICMP) == 0 &&
540
388
         "Invalid condition-code mask for integer comparison");
541
388
  // This is only valid for CompareAndBranch.
542
388
  MachineOperand Target(MBBI->getOperand(
543
388
    Type == SystemZII::CompareAndBranch ? 
2301
:
087
));
544
388
  const uint32_t *RegMask;
545
388
  if (Type == SystemZII::CompareAndSibcall)
546
19
    RegMask = MBBI->getOperand(2).getRegMask();
547
388
548
388
  // Clear out all current operands.
549
388
  int CCUse = MBBI->findRegisterUseOperandIdx(SystemZ::CC, false, TRI);
550
388
  assert(CCUse >= 0 && "BRC/BCR must use CC");
551
388
  Branch->RemoveOperand(CCUse);
552
388
  // Remove target (branch) or regmask (sibcall).
553
388
  if (Type == SystemZII::CompareAndBranch ||
554
388
      
Type == SystemZII::CompareAndSibcall87
)
555
320
    Branch->RemoveOperand(2);
556
388
  Branch->RemoveOperand(1);
557
388
  Branch->RemoveOperand(0);
558
388
559
388
  // Rebuild Branch as a fused compare and branch.
560
388
  // SrcNOps is the number of MI operands of the compare instruction
561
388
  // that we need to copy over.
562
388
  unsigned SrcNOps = 2;
563
388
  if (FusedOpcode == SystemZ::CLT || 
FusedOpcode == SystemZ::CLGT387
)
564
2
    SrcNOps = 3;
565
388
  Branch->setDesc(TII->get(FusedOpcode));
566
388
  MachineInstrBuilder MIB(*Branch->getParent()->getParent(), Branch);
567
1.16k
  for (unsigned I = 0; I < SrcNOps; 
I++778
)
568
778
    MIB.add(Compare.getOperand(I));
569
388
  MIB.add(CCMask);
570
388
571
388
  if (Type == SystemZII::CompareAndBranch) {
572
301
    // Only conditional branches define CC, as they may be converted back
573
301
    // to a non-fused branch because of a long displacement.  Conditional
574
301
    // returns don't have that problem.
575
301
    MIB.add(Target).addReg(SystemZ::CC,
576
301
                           RegState::ImplicitDefine | RegState::Dead);
577
301
  }
578
388
579
388
  if (Type == SystemZII::CompareAndSibcall)
580
19
    MIB.addRegMask(RegMask);
581
388
582
388
  // Clear any intervening kills of SrcReg and SrcReg2.
583
388
  MBBI = Compare;
584
422
  for (++MBBI; MBBI != MBBE; 
++MBBI34
) {
585
34
    MBBI->clearRegisterKills(SrcReg, TRI);
586
34
    if (SrcReg2)
587
23
      MBBI->clearRegisterKills(SrcReg2, TRI);
588
34
  }
589
388
  FusedComparisons += 1;
590
388
  return true;
591
391
}
592
593
// Process all comparison instructions in MBB.  Return true if something
594
// changed.
595
11.0k
bool SystemZElimCompare::processBlock(MachineBasicBlock &MBB) {
596
11.0k
  bool Changed = false;
597
11.0k
598
11.0k
  // Walk backwards through the block looking for comparisons, recording
599
11.0k
  // all CC users as we go.  The subroutines can delete Compare and
600
11.0k
  // instructions before it.
601
11.0k
  bool CompleteCCUsers = !isCCLiveOut(MBB);
602
11.0k
  SmallVector<MachineInstr *, 4> CCUsers;
603
11.0k
  MachineBasicBlock::iterator MBBI = MBB.end();
604
76.6k
  while (MBBI != MBB.begin()) {
605
65.6k
    MachineInstr &MI = *--MBBI;
606
65.6k
    if (CompleteCCUsers && 
(65.4k
MI.isCompare()65.4k
||
isLoadAndTestAsCmp(MI)63.8k
) &&
607
65.6k
        
(1.66k
optimizeCompareZero(MI, CCUsers)1.66k
||
608
1.66k
         
fuseCompareOperations(MI, CCUsers)1.53k
)) {
609
515
      ++MBBI;
610
515
      MI.eraseFromParent();
611
515
      Changed = true;
612
515
      CCUsers.clear();
613
515
      continue;
614
515
    }
615
65.0k
616
65.0k
    if (MI.definesRegister(SystemZ::CC)) {
617
11.6k
      CCUsers.clear();
618
11.6k
      CompleteCCUsers = true;
619
11.6k
    }
620
65.0k
    if (MI.readsRegister(SystemZ::CC) && 
CompleteCCUsers3.65k
)
621
3.60k
      CCUsers.push_back(&MI);
622
65.0k
  }
623
11.0k
  return Changed;
624
11.0k
}
625
626
8.10k
bool SystemZElimCompare::runOnMachineFunction(MachineFunction &F) {
627
8.10k
  if (skipFunction(F.getFunction()))
628
0
    return false;
629
8.10k
630
8.10k
  TII = static_cast<const SystemZInstrInfo *>(F.getSubtarget().getInstrInfo());
631
8.10k
  TRI = &TII->getRegisterInfo();
632
8.10k
633
8.10k
  bool Changed = false;
634
8.10k
  for (auto &MBB : F)
635
11.0k
    Changed |= processBlock(MBB);
636
8.10k
637
8.10k
  return Changed;
638
8.10k
}
639
640
1.00k
FunctionPass *llvm::createSystemZElimComparePass(SystemZTargetMachine &TM) {
641
1.00k
  return new SystemZElimCompare(TM);
642
1.00k
}