Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
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Source (jump to first uncovered line)
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//===-- SystemZFrameLowering.cpp - Frame lowering for SystemZ -------------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
9
#include "SystemZFrameLowering.h"
10
#include "SystemZCallingConv.h"
11
#include "SystemZInstrBuilder.h"
12
#include "SystemZInstrInfo.h"
13
#include "SystemZMachineFunctionInfo.h"
14
#include "SystemZRegisterInfo.h"
15
#include "SystemZSubtarget.h"
16
#include "llvm/CodeGen/MachineModuleInfo.h"
17
#include "llvm/CodeGen/MachineRegisterInfo.h"
18
#include "llvm/CodeGen/RegisterScavenging.h"
19
#include "llvm/IR/Function.h"
20
21
using namespace llvm;
22
23
namespace {
24
// The ABI-defined register save slots, relative to the incoming stack
25
// pointer.
26
static const TargetFrameLowering::SpillSlot SpillOffsetTable[] = {
27
  { SystemZ::R2D,  0x10 },
28
  { SystemZ::R3D,  0x18 },
29
  { SystemZ::R4D,  0x20 },
30
  { SystemZ::R5D,  0x28 },
31
  { SystemZ::R6D,  0x30 },
32
  { SystemZ::R7D,  0x38 },
33
  { SystemZ::R8D,  0x40 },
34
  { SystemZ::R9D,  0x48 },
35
  { SystemZ::R10D, 0x50 },
36
  { SystemZ::R11D, 0x58 },
37
  { SystemZ::R12D, 0x60 },
38
  { SystemZ::R13D, 0x68 },
39
  { SystemZ::R14D, 0x70 },
40
  { SystemZ::R15D, 0x78 },
41
  { SystemZ::F0D,  0x80 },
42
  { SystemZ::F2D,  0x88 },
43
  { SystemZ::F4D,  0x90 },
44
  { SystemZ::F6D,  0x98 }
45
};
46
} // end anonymous namespace
47
48
SystemZFrameLowering::SystemZFrameLowering()
49
    : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 8,
50
                          -SystemZMC::CallFrameSize, 8,
51
1.09k
                          false /* StackRealignable */) {
52
1.09k
  // Create a mapping from register number to save slot offset.
53
1.09k
  RegSpillOffsets.grow(SystemZ::NUM_TARGET_REGS);
54
20.8k
  for (unsigned I = 0, E = array_lengthof(SpillOffsetTable); I != E; 
++I19.7k
)
55
19.7k
    RegSpillOffsets[SpillOffsetTable[I].Reg] = SpillOffsetTable[I].Offset;
56
1.09k
}
57
58
const TargetFrameLowering::SpillSlot *
59
763
SystemZFrameLowering::getCalleeSavedSpillSlots(unsigned &NumEntries) const {
60
763
  NumEntries = array_lengthof(SpillOffsetTable);
61
763
  return SpillOffsetTable;
62
763
}
63
64
void SystemZFrameLowering::determineCalleeSaves(MachineFunction &MF,
65
                                                BitVector &SavedRegs,
66
8.12k
                                                RegScavenger *RS) const {
67
8.12k
  TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
68
8.12k
69
8.12k
  MachineFrameInfo &MFFrame = MF.getFrameInfo();
70
8.12k
  const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
71
8.12k
  bool HasFP = hasFP(MF);
72
8.12k
  SystemZMachineFunctionInfo *MFI = MF.getInfo<SystemZMachineFunctionInfo>();
73
8.12k
  bool IsVarArg = MF.getFunction().isVarArg();
74
8.12k
75
8.12k
  // va_start stores incoming FPR varargs in the normal way, but delegates
76
8.12k
  // the saving of incoming GPR varargs to spillCalleeSavedRegisters().
77
8.12k
  // Record these pending uses, which typically include the call-saved
78
8.12k
  // argument register R6D.
79
8.12k
  if (IsVarArg)
80
0
    for (unsigned I = MFI->getVarArgsFirstGPR(); I < SystemZ::NumArgGPRs; ++I)
81
0
      SavedRegs.set(SystemZ::ArgGPRs[I]);
82
8.12k
83
8.12k
  // If there are any landing pads, entering them will modify r6/r7.
84
8.12k
  if (!MF.getLandingPads().empty()) {
85
4
    SavedRegs.set(SystemZ::R6D);
86
4
    SavedRegs.set(SystemZ::R7D);
87
4
  }
88
8.12k
89
8.12k
  // If the function requires a frame pointer, record that the hard
90
8.12k
  // frame pointer will be clobbered.
91
8.12k
  if (HasFP)
92
88
    SavedRegs.set(SystemZ::R11D);
93
8.12k
94
8.12k
  // If the function calls other functions, record that the return
95
8.12k
  // address register will be clobbered.
96
8.12k
  if (MFFrame.hasCalls())
97
577
    SavedRegs.set(SystemZ::R14D);
98
8.12k
99
8.12k
  // If we are saving GPRs other than the stack pointer, we might as well
100
8.12k
  // save and restore the stack pointer at the same time, via STMG and LMG.
101
8.12k
  // This allows the deallocation to be done by the LMG, rather than needing
102
8.12k
  // a separate %r15 addition.
103
8.12k
  const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF);
104
145k
  for (unsigned I = 0; CSRegs[I]; 
++I136k
) {
105
137k
    unsigned Reg = CSRegs[I];
106
137k
    if (SystemZ::GR64BitRegClass.contains(Reg) && 
SavedRegs.test(Reg)78.6k
) {
107
741
      SavedRegs.set(SystemZ::R15D);
108
741
      break;
109
741
    }
110
137k
  }
111
8.12k
}
112
113
// Add GPR64 to the save instruction being built by MIB, which is in basic
114
// block MBB.  IsImplicit says whether this is an explicit operand to the
115
// instruction, or an implicit one that comes between the explicit start
116
// and end registers.
117
static void addSavedGPR(MachineBasicBlock &MBB, MachineInstrBuilder &MIB,
118
4.32k
                        unsigned GPR64, bool IsImplicit) {
119
4.32k
  const TargetRegisterInfo *RI =
120
4.32k
      MBB.getParent()->getSubtarget().getRegisterInfo();
121
4.32k
  unsigned GPR32 = RI->getSubReg(GPR64, SystemZ::subreg_l32);
122
4.32k
  bool IsLive = MBB.isLiveIn(GPR64) || 
MBB.isLiveIn(GPR32)2.84k
;
123
4.32k
  if (!IsLive || 
!IsImplicit1.47k
) {
124
2.84k
    MIB.addReg(GPR64, getImplRegState(IsImplicit) | getKillRegState(!IsLive));
125
2.84k
    if (!IsLive)
126
2.84k
      MBB.addLiveIn(GPR64);
127
2.84k
  }
128
4.32k
}
129
130
bool SystemZFrameLowering::
131
spillCalleeSavedRegisters(MachineBasicBlock &MBB,
132
                          MachineBasicBlock::iterator MBBI,
133
                          const std::vector<CalleeSavedInfo> &CSI,
134
763
                          const TargetRegisterInfo *TRI) const {
135
763
  if (CSI.empty())
136
0
    return false;
137
763
138
763
  MachineFunction &MF = *MBB.getParent();
139
763
  const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
140
763
  SystemZMachineFunctionInfo *ZFI = MF.getInfo<SystemZMachineFunctionInfo>();
141
763
  bool IsVarArg = MF.getFunction().isVarArg();
142
763
  DebugLoc DL;
143
763
144
763
  // Scan the call-saved GPRs and find the bounds of the register spill area.
145
763
  unsigned LowGPR = 0;
146
763
  unsigned HighGPR = SystemZ::R15D;
147
763
  unsigned StartOffset = -1U;
148
4.40k
  for (unsigned I = 0, E = CSI.size(); I != E; 
++I3.64k
) {
149
3.64k
    unsigned Reg = CSI[I].getReg();
150
3.64k
    if (SystemZ::GR64BitRegClass.contains(Reg)) {
151
2.84k
      unsigned Offset = RegSpillOffsets[Reg];
152
2.84k
      assert(Offset && "Unexpected GPR save");
153
2.84k
      if (StartOffset > Offset) {
154
737
        LowGPR = Reg;
155
737
        StartOffset = Offset;
156
737
      }
157
2.84k
    }
158
3.64k
  }
159
763
160
763
  // Save the range of call-saved registers, for use by the epilogue inserter.
161
763
  ZFI->setLowSavedGPR(LowGPR);
162
763
  ZFI->setHighSavedGPR(HighGPR);
163
763
164
763
  // Include the GPR varargs, if any.  R6D is call-saved, so would
165
763
  // be included by the loop above, but we also need to handle the
166
763
  // call-clobbered argument registers.
167
763
  if (IsVarArg) {
168
0
    unsigned FirstGPR = ZFI->getVarArgsFirstGPR();
169
0
    if (FirstGPR < SystemZ::NumArgGPRs) {
170
0
      unsigned Reg = SystemZ::ArgGPRs[FirstGPR];
171
0
      unsigned Offset = RegSpillOffsets[Reg];
172
0
      if (StartOffset > Offset) {
173
0
        LowGPR = Reg; StartOffset = Offset;
174
0
      }
175
0
    }
176
0
  }
177
763
178
763
  // Save GPRs
179
763
  if (LowGPR) {
180
737
    assert(LowGPR != HighGPR && "Should be saving %r15 and something else");
181
737
182
737
    // Build an STMG instruction.
183
737
    MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(SystemZ::STMG));
184
737
185
737
    // Add the explicit register operands.
186
737
    addSavedGPR(MBB, MIB, LowGPR, false);
187
737
    addSavedGPR(MBB, MIB, HighGPR, false);
188
737
189
737
    // Add the address.
190
737
    MIB.addReg(SystemZ::R15D).addImm(StartOffset);
191
737
192
737
    // Make sure all call-saved GPRs are included as operands and are
193
737
    // marked as live on entry.
194
4.21k
    for (unsigned I = 0, E = CSI.size(); I != E; 
++I3.47k
) {
195
3.47k
      unsigned Reg = CSI[I].getReg();
196
3.47k
      if (SystemZ::GR64BitRegClass.contains(Reg))
197
2.84k
        addSavedGPR(MBB, MIB, Reg, true);
198
3.47k
    }
199
737
200
737
    // ...likewise GPR varargs.
201
737
    if (IsVarArg)
202
0
      for (unsigned I = ZFI->getVarArgsFirstGPR(); I < SystemZ::NumArgGPRs; ++I)
203
0
        addSavedGPR(MBB, MIB, SystemZ::ArgGPRs[I], true);
204
737
  }
205
763
206
763
  // Save FPRs/VRs in the normal TargetInstrInfo way.
207
4.40k
  for (unsigned I = 0, E = CSI.size(); I != E; 
++I3.64k
) {
208
3.64k
    unsigned Reg = CSI[I].getReg();
209
3.64k
    if (SystemZ::FP64BitRegClass.contains(Reg)) {
210
767
      MBB.addLiveIn(Reg);
211
767
      TII->storeRegToStackSlot(MBB, MBBI, Reg, true, CSI[I].getFrameIdx(),
212
767
                               &SystemZ::FP64BitRegClass, TRI);
213
767
    }
214
3.64k
    if (SystemZ::VR128BitRegClass.contains(Reg)) {
215
32
      MBB.addLiveIn(Reg);
216
32
      TII->storeRegToStackSlot(MBB, MBBI, Reg, true, CSI[I].getFrameIdx(),
217
32
                               &SystemZ::VR128BitRegClass, TRI);
218
32
    }
219
3.64k
  }
220
763
221
763
  return true;
222
763
}
223
224
bool SystemZFrameLowering::
225
restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
226
                            MachineBasicBlock::iterator MBBI,
227
                            std::vector<CalleeSavedInfo> &CSI,
228
770
                            const TargetRegisterInfo *TRI) const {
229
770
  if (CSI.empty())
230
0
    return false;
231
770
232
770
  MachineFunction &MF = *MBB.getParent();
233
770
  const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
234
770
  SystemZMachineFunctionInfo *ZFI = MF.getInfo<SystemZMachineFunctionInfo>();
235
770
  bool HasFP = hasFP(MF);
236
770
  DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : 
DebugLoc()0
;
237
770
238
770
  // Restore FPRs/VRs in the normal TargetInstrInfo way.
239
4.40k
  for (unsigned I = 0, E = CSI.size(); I != E; 
++I3.63k
) {
240
3.63k
    unsigned Reg = CSI[I].getReg();
241
3.63k
    if (SystemZ::FP64BitRegClass.contains(Reg))
242
767
      TII->loadRegFromStackSlot(MBB, MBBI, Reg, CSI[I].getFrameIdx(),
243
767
                                &SystemZ::FP64BitRegClass, TRI);
244
3.63k
    if (SystemZ::VR128BitRegClass.contains(Reg))
245
32
      TII->loadRegFromStackSlot(MBB, MBBI, Reg, CSI[I].getFrameIdx(),
246
32
                                &SystemZ::VR128BitRegClass, TRI);
247
3.63k
  }
248
770
249
770
  // Restore call-saved GPRs (but not call-clobbered varargs, which at
250
770
  // this point might hold return values).
251
770
  unsigned LowGPR = ZFI->getLowSavedGPR();
252
770
  unsigned HighGPR = ZFI->getHighSavedGPR();
253
770
  unsigned StartOffset = RegSpillOffsets[LowGPR];
254
770
  if (LowGPR) {
255
744
    // If we saved any of %r2-%r5 as varargs, we should also be saving
256
744
    // and restoring %r6.  If we're saving %r6 or above, we should be
257
744
    // restoring it too.
258
744
    assert(LowGPR != HighGPR && "Should be loading %r15 and something else");
259
744
260
744
    // Build an LMG instruction.
261
744
    MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(SystemZ::LMG));
262
744
263
744
    // Add the explicit register operands.
264
744
    MIB.addReg(LowGPR, RegState::Define);
265
744
    MIB.addReg(HighGPR, RegState::Define);
266
744
267
744
    // Add the address.
268
744
    MIB.addReg(HasFP ? 
SystemZ::R11D84
:
SystemZ::R15D660
);
269
744
    MIB.addImm(StartOffset);
270
744
271
744
    // Do a second scan adding regs as being defined by instruction
272
4.20k
    for (unsigned I = 0, E = CSI.size(); I != E; 
++I3.46k
) {
273
3.46k
      unsigned Reg = CSI[I].getReg();
274
3.46k
      if (Reg != LowGPR && 
Reg != HighGPR2.72k
&&
275
3.46k
          
SystemZ::GR64BitRegClass.contains(Reg)1.97k
)
276
1.34k
        MIB.addReg(Reg, RegState::ImplicitDefine);
277
3.46k
    }
278
744
  }
279
770
280
770
  return true;
281
770
}
282
283
void SystemZFrameLowering::
284
processFunctionBeforeFrameFinalized(MachineFunction &MF,
285
8.11k
                                    RegScavenger *RS) const {
286
8.11k
  MachineFrameInfo &MFFrame = MF.getFrameInfo();
287
8.11k
  // Get the size of our stack frame to be allocated ...
288
8.11k
  uint64_t StackSize = (MFFrame.estimateStackSize(MF) +
289
8.11k
                        SystemZMC::CallFrameSize);
290
8.11k
  // ... and the maximum offset we may need to reach into the
291
8.11k
  // caller's frame to access the save area or stack arguments.
292
8.11k
  int64_t MaxArgOffset = SystemZMC::CallFrameSize;
293
11.1k
  for (int I = MFFrame.getObjectIndexBegin(); I != 0; 
++I3.00k
)
294
3.00k
    if (MFFrame.getObjectOffset(I) >= 0) {
295
3.00k
      int64_t ArgOffset = SystemZMC::CallFrameSize +
296
3.00k
                          MFFrame.getObjectOffset(I) +
297
3.00k
                          MFFrame.getObjectSize(I);
298
3.00k
      MaxArgOffset = std::max(MaxArgOffset, ArgOffset);
299
3.00k
    }
300
8.11k
301
8.11k
  uint64_t MaxReach = StackSize + MaxArgOffset;
302
8.11k
  if (!isUInt<12>(MaxReach)) {
303
113
    // We may need register scavenging slots if some parts of the frame
304
113
    // are outside the reach of an unsigned 12-bit displacement.
305
113
    // Create 2 for the case where both addresses in an MVC are
306
113
    // out of range.
307
113
    RS->addScavengingFrameIndex(MFFrame.CreateStackObject(8, 8, false));
308
113
    RS->addScavengingFrameIndex(MFFrame.CreateStackObject(8, 8, false));
309
113
  }
310
8.11k
}
311
312
// Emit instructions before MBBI (in MBB) to add NumBytes to Reg.
313
static void emitIncrement(MachineBasicBlock &MBB,
314
                          MachineBasicBlock::iterator &MBBI,
315
                          const DebugLoc &DL,
316
                          unsigned Reg, int64_t NumBytes,
317
851
                          const TargetInstrInfo *TII) {
318
1.70k
  while (NumBytes) {
319
854
    unsigned Opcode;
320
854
    int64_t ThisVal = NumBytes;
321
854
    if (isInt<16>(NumBytes))
322
757
      Opcode = SystemZ::AGHI;
323
97
    else {
324
97
      Opcode = SystemZ::AGFI;
325
97
      // Make sure we maintain 8-byte stack alignment.
326
97
      int64_t MinVal = -uint64_t(1) << 31;
327
97
      int64_t MaxVal = (int64_t(1) << 31) - 8;
328
97
      if (ThisVal < MinVal)
329
1
        ThisVal = MinVal;
330
96
      else if (ThisVal > MaxVal)
331
2
        ThisVal = MaxVal;
332
97
    }
333
854
    MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII->get(Opcode), Reg)
334
854
      .addReg(Reg).addImm(ThisVal);
335
854
    // The CC implicit def is dead.
336
854
    MI->getOperand(3).setIsDead();
337
854
    NumBytes -= ThisVal;
338
854
  }
339
851
}
340
341
void SystemZFrameLowering::emitPrologue(MachineFunction &MF,
342
8.11k
                                        MachineBasicBlock &MBB) const {
343
8.11k
  assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
344
8.11k
  MachineFrameInfo &MFFrame = MF.getFrameInfo();
345
8.11k
  auto *ZII =
346
8.11k
      static_cast<const SystemZInstrInfo *>(MF.getSubtarget().getInstrInfo());
347
8.11k
  SystemZMachineFunctionInfo *ZFI = MF.getInfo<SystemZMachineFunctionInfo>();
348
8.11k
  MachineBasicBlock::iterator MBBI = MBB.begin();
349
8.11k
  MachineModuleInfo &MMI = MF.getMMI();
350
8.11k
  const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
351
8.11k
  const std::vector<CalleeSavedInfo> &CSI = MFFrame.getCalleeSavedInfo();
352
8.11k
  bool HasFP = hasFP(MF);
353
8.11k
354
8.11k
  // Debug location must be unknown since the first debug location is used
355
8.11k
  // to determine the end of the prologue.
356
8.11k
  DebugLoc DL;
357
8.11k
358
8.11k
  // The current offset of the stack pointer from the CFA.
359
8.11k
  int64_t SPOffsetFromCFA = -SystemZMC::CFAOffsetFromInitialSP;
360
8.11k
361
8.11k
  if (ZFI->getLowSavedGPR()) {
362
737
    // Skip over the GPR saves.
363
737
    if (MBBI != MBB.end() && MBBI->getOpcode() == SystemZ::STMG)
364
737
      ++MBBI;
365
737
    else
366
737
      
llvm_unreachable0
("Couldn't skip over GPR saves");
367
737
368
737
    // Add CFI for the GPR saves.
369
3.47k
    
for (auto &Save : CSI)737
{
370
3.47k
      unsigned Reg = Save.getReg();
371
3.47k
      if (SystemZ::GR64BitRegClass.contains(Reg)) {
372
2.84k
        int64_t Offset = SPOffsetFromCFA + RegSpillOffsets[Reg];
373
2.84k
        unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
374
2.84k
            nullptr, MRI->getDwarfRegNum(Reg, true), Offset));
375
2.84k
        BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION))
376
2.84k
            .addCFIIndex(CFIIndex);
377
2.84k
      }
378
3.47k
    }
379
737
  }
380
8.11k
381
8.11k
  uint64_t StackSize = MFFrame.getStackSize();
382
8.11k
  // We need to allocate the ABI-defined 160-byte base area whenever
383
8.11k
  // we allocate stack space for our own use and whenever we call another
384
8.11k
  // function.
385
8.11k
  if (StackSize || 
MFFrame.hasVarSizedObjects()7.57k
||
MFFrame.hasCalls()7.56k
) {
386
746
    StackSize += SystemZMC::CallFrameSize;
387
746
    MFFrame.setStackSize(StackSize);
388
746
  }
389
8.11k
390
8.11k
  if (StackSize) {
391
746
    // Determine if we want to store a backchain.
392
746
    bool StoreBackchain = MF.getFunction().hasFnAttribute("backchain");
393
746
394
746
    // If we need backchain, save current stack pointer.  R1 is free at this
395
746
    // point.
396
746
    if (StoreBackchain)
397
4
      BuildMI(MBB, MBBI, DL, ZII->get(SystemZ::LGR))
398
4
        .addReg(SystemZ::R1D, RegState::Define).addReg(SystemZ::R15D);
399
746
400
746
    // Allocate StackSize bytes.
401
746
    int64_t Delta = -int64_t(StackSize);
402
746
    emitIncrement(MBB, MBBI, DL, SystemZ::R15D, Delta, ZII);
403
746
404
746
    // Add CFI for the allocation.
405
746
    unsigned CFIIndex = MF.addFrameInst(
406
746
        MCCFIInstruction::createDefCfaOffset(nullptr, SPOffsetFromCFA + Delta));
407
746
    BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION))
408
746
        .addCFIIndex(CFIIndex);
409
746
    SPOffsetFromCFA += Delta;
410
746
411
746
    if (StoreBackchain)
412
4
      BuildMI(MBB, MBBI, DL, ZII->get(SystemZ::STG))
413
4
        .addReg(SystemZ::R1D, RegState::Kill).addReg(SystemZ::R15D).addImm(0).addReg(0);
414
746
  }
415
8.11k
416
8.11k
  if (HasFP) {
417
85
    // Copy the base of the frame to R11.
418
85
    BuildMI(MBB, MBBI, DL, ZII->get(SystemZ::LGR), SystemZ::R11D)
419
85
      .addReg(SystemZ::R15D);
420
85
421
85
    // Add CFI for the new frame location.
422
85
    unsigned HardFP = MRI->getDwarfRegNum(SystemZ::R11D, true);
423
85
    unsigned CFIIndex = MF.addFrameInst(
424
85
        MCCFIInstruction::createDefCfaRegister(nullptr, HardFP));
425
85
    BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION))
426
85
        .addCFIIndex(CFIIndex);
427
85
428
85
    // Mark the FramePtr as live at the beginning of every block except
429
85
    // the entry block.  (We'll have marked R11 as live on entry when
430
85
    // saving the GPRs.)
431
108
    for (auto I = std::next(MF.begin()), E = MF.end(); I != E; 
++I23
)
432
23
      I->addLiveIn(SystemZ::R11D);
433
85
  }
434
8.11k
435
8.11k
  // Skip over the FPR/VR saves.
436
8.11k
  SmallVector<unsigned, 8> CFIIndexes;
437
8.11k
  for (auto &Save : CSI) {
438
3.64k
    unsigned Reg = Save.getReg();
439
3.64k
    if (SystemZ::FP64BitRegClass.contains(Reg)) {
440
767
      if (MBBI != MBB.end() &&
441
767
          (MBBI->getOpcode() == SystemZ::STD ||
442
767
           
MBBI->getOpcode() == SystemZ::STDY0
))
443
767
        ++MBBI;
444
767
      else
445
767
        
llvm_unreachable0
("Couldn't skip over FPR save");
446
2.87k
    } else if (SystemZ::VR128BitRegClass.contains(Reg)) {
447
32
      if (MBBI != MBB.end() &&
448
32
          MBBI->getOpcode() == SystemZ::VST)
449
32
        ++MBBI;
450
32
      else
451
32
        
llvm_unreachable0
("Couldn't skip over VR save");
452
32
    } else
453
2.84k
      continue;
454
799
455
799
    // Add CFI for the this save.
456
799
    unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
457
799
    unsigned IgnoredFrameReg;
458
799
    int64_t Offset =
459
799
        getFrameIndexReference(MF, Save.getFrameIdx(), IgnoredFrameReg);
460
799
461
799
    unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
462
799
          nullptr, DwarfReg, SPOffsetFromCFA + Offset));
463
799
    CFIIndexes.push_back(CFIIndex);
464
799
  }
465
8.11k
  // Complete the CFI for the FPR/VR saves, modelling them as taking effect
466
8.11k
  // after the last save.
467
8.11k
  for (auto CFIIndex : CFIIndexes) {
468
799
    BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION))
469
799
        .addCFIIndex(CFIIndex);
470
799
  }
471
8.11k
}
472
473
void SystemZFrameLowering::emitEpilogue(MachineFunction &MF,
474
8.24k
                                        MachineBasicBlock &MBB) const {
475
8.24k
  MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
476
8.24k
  auto *ZII =
477
8.24k
      static_cast<const SystemZInstrInfo *>(MF.getSubtarget().getInstrInfo());
478
8.24k
  SystemZMachineFunctionInfo *ZFI = MF.getInfo<SystemZMachineFunctionInfo>();
479
8.24k
  MachineFrameInfo &MFFrame = MF.getFrameInfo();
480
8.24k
481
8.24k
  // Skip the return instruction.
482
8.24k
  assert(MBBI->isReturn() && "Can only insert epilogue into returning blocks");
483
8.24k
484
8.24k
  uint64_t StackSize = MFFrame.getStackSize();
485
8.24k
  if (ZFI->getLowSavedGPR()) {
486
744
    --MBBI;
487
744
    unsigned Opcode = MBBI->getOpcode();
488
744
    if (Opcode != SystemZ::LMG)
489
744
      
llvm_unreachable0
("Expected to see callee-save register restore code");
490
744
491
744
    unsigned AddrOpNo = 2;
492
744
    DebugLoc DL = MBBI->getDebugLoc();
493
744
    uint64_t Offset = StackSize + MBBI->getOperand(AddrOpNo + 1).getImm();
494
744
    unsigned NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset);
495
744
496
744
    // If the offset is too large, use the largest stack-aligned offset
497
744
    // and add the rest to the base register (the stack or frame pointer).
498
744
    if (!NewOpcode) {
499
27
      uint64_t NumBytes = Offset - 0x7fff8;
500
27
      emitIncrement(MBB, MBBI, DL, MBBI->getOperand(AddrOpNo).getReg(),
501
27
                    NumBytes, ZII);
502
27
      Offset -= NumBytes;
503
27
      NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset);
504
27
      assert(NewOpcode && "No restore instruction available");
505
27
    }
506
744
507
744
    MBBI->setDesc(ZII->get(NewOpcode));
508
744
    MBBI->getOperand(AddrOpNo + 1).ChangeToImmediate(Offset);
509
7.49k
  } else if (StackSize) {
510
78
    DebugLoc DL = MBBI->getDebugLoc();
511
78
    emitIncrement(MBB, MBBI, DL, SystemZ::R15D, StackSize, ZII);
512
78
  }
513
8.24k
}
514
515
54.3k
bool SystemZFrameLowering::hasFP(const MachineFunction &MF) const {
516
54.3k
  return (MF.getTarget().Options.DisableFramePointerElim(MF) ||
517
54.3k
          
MF.getFrameInfo().hasVarSizedObjects()53.6k
||
518
54.3k
          
MF.getInfo<SystemZMachineFunctionInfo>()->getManipulatesSP()53.4k
);
519
54.3k
}
520
521
bool
522
2.93k
SystemZFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
523
2.93k
  // The ABI requires us to allocate 160 bytes of stack space for the callee,
524
2.93k
  // with any outgoing stack arguments being placed above that.  It seems
525
2.93k
  // better to make that area a permanent feature of the frame even if
526
2.93k
  // we're using a frame pointer.
527
2.93k
  return true;
528
2.93k
}
529
530
MachineBasicBlock::iterator SystemZFrameLowering::
531
eliminateCallFramePseudoInstr(MachineFunction &MF,
532
                              MachineBasicBlock &MBB,
533
1.80k
                              MachineBasicBlock::iterator MI) const {
534
1.80k
  switch (MI->getOpcode()) {
535
1.80k
  case SystemZ::ADJCALLSTACKDOWN:
536
1.80k
  case SystemZ::ADJCALLSTACKUP:
537
1.80k
    assert(hasReservedCallFrame(MF) &&
538
1.80k
           "ADJSTACKDOWN and ADJSTACKUP should be no-ops");
539
1.80k
    return MBB.erase(MI);
540
1.80k
    
break0
;
541
1.80k
542
1.80k
  default:
543
0
    llvm_unreachable("Unexpected call frame instruction");
544
1.80k
  }
545
1.80k
}