Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
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//===-- SystemZInstrInfo.cpp - SystemZ instruction information ------------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file contains the SystemZ implementation of the TargetInstrInfo class.
10
//
11
//===----------------------------------------------------------------------===//
12
13
#include "SystemZInstrInfo.h"
14
#include "MCTargetDesc/SystemZMCTargetDesc.h"
15
#include "SystemZ.h"
16
#include "SystemZInstrBuilder.h"
17
#include "SystemZSubtarget.h"
18
#include "llvm/ADT/Statistic.h"
19
#include "llvm/CodeGen/LiveInterval.h"
20
#include "llvm/CodeGen/LiveIntervals.h"
21
#include "llvm/CodeGen/LiveVariables.h"
22
#include "llvm/CodeGen/MachineBasicBlock.h"
23
#include "llvm/CodeGen/MachineFrameInfo.h"
24
#include "llvm/CodeGen/MachineFunction.h"
25
#include "llvm/CodeGen/MachineInstr.h"
26
#include "llvm/CodeGen/MachineMemOperand.h"
27
#include "llvm/CodeGen/MachineOperand.h"
28
#include "llvm/CodeGen/MachineRegisterInfo.h"
29
#include "llvm/CodeGen/SlotIndexes.h"
30
#include "llvm/CodeGen/TargetInstrInfo.h"
31
#include "llvm/CodeGen/TargetSubtargetInfo.h"
32
#include "llvm/MC/MCInstrDesc.h"
33
#include "llvm/MC/MCRegisterInfo.h"
34
#include "llvm/Support/BranchProbability.h"
35
#include "llvm/Support/ErrorHandling.h"
36
#include "llvm/Support/MathExtras.h"
37
#include "llvm/Target/TargetMachine.h"
38
#include <cassert>
39
#include <cstdint>
40
#include <iterator>
41
42
using namespace llvm;
43
44
#define GET_INSTRINFO_CTOR_DTOR
45
#define GET_INSTRMAP_INFO
46
#include "SystemZGenInstrInfo.inc"
47
48
#define DEBUG_TYPE "systemz-II"
49
STATISTIC(LOCRMuxJumps, "Number of LOCRMux jump-sequences (lower is better)");
50
51
// Return a mask with Count low bits set.
52
7.21k
static uint64_t allOnes(unsigned int Count) {
53
7.21k
  return Count == 0 ? 
00
: (uint64_t(1) << (Count - 1) << 1) - 1;
54
7.21k
}
55
56
// Reg should be a 32-bit GPR.  Return true if it is a high register rather
57
// than a low register.
58
3.99k
static bool isHighReg(unsigned int Reg) {
59
3.99k
  if (SystemZ::GRH32BitRegClass.contains(Reg))
60
1.36k
    return true;
61
2.62k
  assert(SystemZ::GR32BitRegClass.contains(Reg) && "Invalid GRX32");
62
2.62k
  return false;
63
2.62k
}
64
65
// Pin the vtable to this file.
66
0
void SystemZInstrInfo::anchor() {}
67
68
SystemZInstrInfo::SystemZInstrInfo(SystemZSubtarget &sti)
69
  : SystemZGenInstrInfo(SystemZ::ADJCALLSTACKDOWN, SystemZ::ADJCALLSTACKUP),
70
1.09k
    RI(), STI(sti) {
71
1.09k
}
72
73
// MI is a 128-bit load or store.  Split it into two 64-bit loads or stores,
74
// each having the opcode given by NewOpcode.
75
void SystemZInstrInfo::splitMove(MachineBasicBlock::iterator MI,
76
486
                                 unsigned NewOpcode) const {
77
486
  MachineBasicBlock *MBB = MI->getParent();
78
486
  MachineFunction &MF = *MBB->getParent();
79
486
80
486
  // Get two load or store instructions.  Use the original instruction for one
81
486
  // of them (arbitrarily the second here) and create a clone for the other.
82
486
  MachineInstr *EarlierMI = MF.CloneMachineInstr(&*MI);
83
486
  MBB->insert(MI, EarlierMI);
84
486
85
486
  // Set up the two 64-bit registers and remember super reg and its flags.
86
486
  MachineOperand &HighRegOp = EarlierMI->getOperand(0);
87
486
  MachineOperand &LowRegOp = MI->getOperand(0);
88
486
  unsigned Reg128 = LowRegOp.getReg();
89
486
  unsigned Reg128Killed = getKillRegState(LowRegOp.isKill());
90
486
  unsigned Reg128Undef  = getUndefRegState(LowRegOp.isUndef());
91
486
  HighRegOp.setReg(RI.getSubReg(HighRegOp.getReg(), SystemZ::subreg_h64));
92
486
  LowRegOp.setReg(RI.getSubReg(LowRegOp.getReg(), SystemZ::subreg_l64));
93
486
94
486
  if (MI->mayStore()) {
95
285
    // Add implicit uses of the super register in case one of the subregs is
96
285
    // undefined. We could track liveness and skip storing an undefined
97
285
    // subreg, but this is hopefully rare (discovered with llvm-stress).
98
285
    // If Reg128 was killed, set kill flag on MI.
99
285
    unsigned Reg128UndefImpl = (Reg128Undef | RegState::Implicit);
100
285
    MachineInstrBuilder(MF, EarlierMI).addReg(Reg128, Reg128UndefImpl);
101
285
    MachineInstrBuilder(MF, MI).addReg(Reg128, (Reg128UndefImpl | Reg128Killed));
102
285
  }
103
486
104
486
  // The address in the first (high) instruction is already correct.
105
486
  // Adjust the offset in the second (low) instruction.
106
486
  MachineOperand &HighOffsetOp = EarlierMI->getOperand(2);
107
486
  MachineOperand &LowOffsetOp = MI->getOperand(2);
108
486
  LowOffsetOp.setImm(LowOffsetOp.getImm() + 8);
109
486
110
486
  // Clear the kill flags on the registers in the first instruction.
111
486
  if (EarlierMI->getOperand(0).isReg() && EarlierMI->getOperand(0).isUse())
112
285
    EarlierMI->getOperand(0).setIsKill(false);
113
486
  EarlierMI->getOperand(1).setIsKill(false);
114
486
  EarlierMI->getOperand(3).setIsKill(false);
115
486
116
486
  // Set the opcodes.
117
486
  unsigned HighOpcode = getOpcodeForOffset(NewOpcode, HighOffsetOp.getImm());
118
486
  unsigned LowOpcode = getOpcodeForOffset(NewOpcode, LowOffsetOp.getImm());
119
486
  assert(HighOpcode && LowOpcode && "Both offsets should be in range");
120
486
121
486
  EarlierMI->setDesc(get(HighOpcode));
122
486
  MI->setDesc(get(LowOpcode));
123
486
}
124
125
// Split ADJDYNALLOC instruction MI.
126
46
void SystemZInstrInfo::splitAdjDynAlloc(MachineBasicBlock::iterator MI) const {
127
46
  MachineBasicBlock *MBB = MI->getParent();
128
46
  MachineFunction &MF = *MBB->getParent();
129
46
  MachineFrameInfo &MFFrame = MF.getFrameInfo();
130
46
  MachineOperand &OffsetMO = MI->getOperand(2);
131
46
132
46
  uint64_t Offset = (MFFrame.getMaxCallFrameSize() +
133
46
                     SystemZMC::CallFrameSize +
134
46
                     OffsetMO.getImm());
135
46
  unsigned NewOpcode = getOpcodeForOffset(SystemZ::LA, Offset);
136
46
  assert(NewOpcode && "No support for huge argument lists yet");
137
46
  MI->setDesc(get(NewOpcode));
138
46
  OffsetMO.setImm(Offset);
139
46
}
140
141
// MI is an RI-style pseudo instruction.  Replace it with LowOpcode
142
// if the first operand is a low GR32 and HighOpcode if the first operand
143
// is a high GR32.  ConvertHigh is true if LowOpcode takes a signed operand
144
// and HighOpcode takes an unsigned 32-bit operand.  In those cases,
145
// MI has the same kind of operand as LowOpcode, so needs to be converted
146
// if HighOpcode is used.
147
void SystemZInstrInfo::expandRIPseudo(MachineInstr &MI, unsigned LowOpcode,
148
                                      unsigned HighOpcode,
149
1.16k
                                      bool ConvertHigh) const {
150
1.16k
  unsigned Reg = MI.getOperand(0).getReg();
151
1.16k
  bool IsHigh = isHighReg(Reg);
152
1.16k
  MI.setDesc(get(IsHigh ? 
HighOpcode409
:
LowOpcode751
));
153
1.16k
  if (IsHigh && 
ConvertHigh409
)
154
361
    MI.getOperand(1).setImm(uint32_t(MI.getOperand(1).getImm()));
155
1.16k
}
156
157
// MI is a three-operand RIE-style pseudo instruction.  Replace it with
158
// LowOpcodeK if the registers are both low GR32s, otherwise use a move
159
// followed by HighOpcode or LowOpcode, depending on whether the target
160
// is a high or low GR32.
161
void SystemZInstrInfo::expandRIEPseudo(MachineInstr &MI, unsigned LowOpcode,
162
                                       unsigned LowOpcodeK,
163
55
                                       unsigned HighOpcode) const {
164
55
  unsigned DestReg = MI.getOperand(0).getReg();
165
55
  unsigned SrcReg = MI.getOperand(1).getReg();
166
55
  bool DestIsHigh = isHighReg(DestReg);
167
55
  bool SrcIsHigh = isHighReg(SrcReg);
168
55
  if (!DestIsHigh && 
!SrcIsHigh43
)
169
42
    MI.setDesc(get(LowOpcodeK));
170
13
  else {
171
13
    if (DestReg != SrcReg) {
172
3
      emitGRX32Move(*MI.getParent(), MI, MI.getDebugLoc(), DestReg, SrcReg,
173
3
                    SystemZ::LR, 32, MI.getOperand(1).isKill(),
174
3
                    MI.getOperand(1).isUndef());
175
3
      MI.getOperand(1).setReg(DestReg);
176
3
    }
177
13
    MI.setDesc(get(DestIsHigh ? 
HighOpcode12
:
LowOpcode1
));
178
13
    MI.tieOperands(0, 1);
179
13
  }
180
55
}
181
182
// MI is an RXY-style pseudo instruction.  Replace it with LowOpcode
183
// if the first operand is a low GR32 and HighOpcode if the first operand
184
// is a high GR32.
185
void SystemZInstrInfo::expandRXYPseudo(MachineInstr &MI, unsigned LowOpcode,
186
1.02k
                                       unsigned HighOpcode) const {
187
1.02k
  unsigned Reg = MI.getOperand(0).getReg();
188
1.02k
  unsigned Opcode = getOpcodeForOffset(isHighReg(Reg) ? 
HighOpcode455
:
LowOpcode572
,
189
1.02k
                                       MI.getOperand(2).getImm());
190
1.02k
  MI.setDesc(get(Opcode));
191
1.02k
}
192
193
// MI is a load-on-condition pseudo instruction with a single register
194
// (source or destination) operand.  Replace it with LowOpcode if the
195
// register is a low GR32 and HighOpcode if the register is a high GR32.
196
void SystemZInstrInfo::expandLOCPseudo(MachineInstr &MI, unsigned LowOpcode,
197
503
                                       unsigned HighOpcode) const {
198
503
  unsigned Reg = MI.getOperand(0).getReg();
199
503
  unsigned Opcode = isHighReg(Reg) ? 
HighOpcode368
:
LowOpcode135
;
200
503
  MI.setDesc(get(Opcode));
201
503
}
202
203
// MI is a load-register-on-condition pseudo instruction.  Replace it with
204
// LowOpcode if source and destination are both low GR32s and HighOpcode if
205
// source and destination are both high GR32s.
206
void SystemZInstrInfo::expandLOCRPseudo(MachineInstr &MI, unsigned LowOpcode,
207
17
                                        unsigned HighOpcode) const {
208
17
  unsigned DestReg = MI.getOperand(0).getReg();
209
17
  unsigned SrcReg = MI.getOperand(2).getReg();
210
17
  bool DestIsHigh = isHighReg(DestReg);
211
17
  bool SrcIsHigh = isHighReg(SrcReg);
212
17
213
17
  if (!DestIsHigh && 
!SrcIsHigh12
)
214
10
    MI.setDesc(get(LowOpcode));
215
7
  else if (DestIsHigh && 
SrcIsHigh5
)
216
3
    MI.setDesc(get(HighOpcode));
217
4
  else
218
4
    LOCRMuxJumps++;
219
17
220
17
  // If we were unable to implement the pseudo with a single instruction, we
221
17
  // need to convert it back into a branch sequence.  This cannot be done here
222
17
  // since the caller of expandPostRAPseudo does not handle changes to the CFG
223
17
  // correctly.  This change is defered to the SystemZExpandPseudo pass.
224
17
}
225
226
// MI is a select pseudo instruction.  Replace it with LowOpcode if source
227
// and destination are all low GR32s and HighOpcode if source and destination
228
// are all high GR32s.  Otherwise, use the two-operand MixedOpcode.
229
void SystemZInstrInfo::expandSELRPseudo(MachineInstr &MI, unsigned LowOpcode,
230
                                        unsigned HighOpcode,
231
21
                                        unsigned MixedOpcode) const {
232
21
  unsigned DestReg = MI.getOperand(0).getReg();
233
21
  unsigned Src1Reg = MI.getOperand(1).getReg();
234
21
  unsigned Src2Reg = MI.getOperand(2).getReg();
235
21
  bool DestIsHigh = isHighReg(DestReg);
236
21
  bool Src1IsHigh = isHighReg(Src1Reg);
237
21
  bool Src2IsHigh = isHighReg(Src2Reg);
238
21
239
21
  // If sources and destination aren't all high or all low, we may be able to
240
21
  // simplify the operation by moving one of the sources to the destination
241
21
  // first.  But only if this doesn't clobber the other source.
242
21
  if (DestReg != Src1Reg && 
DestReg != Src2Reg15
) {
243
8
    if (DestIsHigh != Src1IsHigh) {
244
0
      emitGRX32Move(*MI.getParent(), MI, MI.getDebugLoc(), DestReg, Src1Reg,
245
0
                    SystemZ::LR, 32, MI.getOperand(1).isKill(),
246
0
                    MI.getOperand(1).isUndef());
247
0
      MI.getOperand(1).setReg(DestReg);
248
0
      Src1Reg = DestReg;
249
0
      Src1IsHigh = DestIsHigh;
250
8
    } else if (DestIsHigh != Src2IsHigh) {
251
0
      emitGRX32Move(*MI.getParent(), MI, MI.getDebugLoc(), DestReg, Src2Reg,
252
0
                    SystemZ::LR, 32, MI.getOperand(2).isKill(),
253
0
                    MI.getOperand(2).isUndef());
254
0
      MI.getOperand(2).setReg(DestReg);
255
0
      Src2Reg = DestReg;
256
0
      Src2IsHigh = DestIsHigh;
257
0
    }
258
8
  }
259
21
260
21
  // If the destination (now) matches one source, prefer this to be first.
261
21
  if (DestReg != Src1Reg && 
DestReg == Src2Reg15
) {
262
7
    commuteInstruction(MI, false, 1, 2);
263
7
    std::swap(Src1Reg, Src2Reg);
264
7
    std::swap(Src1IsHigh, Src2IsHigh);
265
7
  }
266
21
267
21
  if (!DestIsHigh && 
!Src1IsHigh13
&&
!Src2IsHigh13
)
268
11
    MI.setDesc(get(LowOpcode));
269
10
  else if (DestIsHigh && 
Src1IsHigh8
&&
Src2IsHigh8
)
270
6
    MI.setDesc(get(HighOpcode));
271
4
  else {
272
4
    // Given the simplifcation above, we must already have a two-operand case.
273
4
    assert (DestReg == Src1Reg);
274
4
    MI.setDesc(get(MixedOpcode));
275
4
    MI.tieOperands(0, 1);
276
4
    LOCRMuxJumps++;
277
4
  }
278
21
279
21
  // If we were unable to implement the pseudo with a single instruction, we
280
21
  // need to convert it back into a branch sequence.  This cannot be done here
281
21
  // since the caller of expandPostRAPseudo does not handle changes to the CFG
282
21
  // correctly.  This change is defered to the SystemZExpandPseudo pass.
283
21
}
284
285
// MI is an RR-style pseudo instruction that zero-extends the low Size bits
286
// of one GRX32 into another.  Replace it with LowOpcode if both operands
287
// are low registers, otherwise use RISB[LH]G.
288
void SystemZInstrInfo::expandZExtPseudo(MachineInstr &MI, unsigned LowOpcode,
289
123
                                        unsigned Size) const {
290
123
  MachineInstrBuilder MIB =
291
123
    emitGRX32Move(*MI.getParent(), MI, MI.getDebugLoc(),
292
123
               MI.getOperand(0).getReg(), MI.getOperand(1).getReg(), LowOpcode,
293
123
               Size, MI.getOperand(1).isKill(), MI.getOperand(1).isUndef());
294
123
295
123
  // Keep the remaining operands as-is.
296
168
  for (unsigned I = 2; I < MI.getNumOperands(); 
++I45
)
297
45
    MIB.add(MI.getOperand(I));
298
123
299
123
  MI.eraseFromParent();
300
123
}
301
302
2
void SystemZInstrInfo::expandLoadStackGuard(MachineInstr *MI) const {
303
2
  MachineBasicBlock *MBB = MI->getParent();
304
2
  MachineFunction &MF = *MBB->getParent();
305
2
  const unsigned Reg64 = MI->getOperand(0).getReg();
306
2
  const unsigned Reg32 = RI.getSubReg(Reg64, SystemZ::subreg_l32);
307
2
308
2
  // EAR can only load the low subregister so us a shift for %a0 to produce
309
2
  // the GR containing %a0 and %a1.
310
2
311
2
  // ear <reg>, %a0
312
2
  BuildMI(*MBB, MI, MI->getDebugLoc(), get(SystemZ::EAR), Reg32)
313
2
    .addReg(SystemZ::A0)
314
2
    .addReg(Reg64, RegState::ImplicitDefine);
315
2
316
2
  // sllg <reg>, <reg>, 32
317
2
  BuildMI(*MBB, MI, MI->getDebugLoc(), get(SystemZ::SLLG), Reg64)
318
2
    .addReg(Reg64)
319
2
    .addReg(0)
320
2
    .addImm(32);
321
2
322
2
  // ear <reg>, %a1
323
2
  BuildMI(*MBB, MI, MI->getDebugLoc(), get(SystemZ::EAR), Reg32)
324
2
    .addReg(SystemZ::A1);
325
2
326
2
  // lg <reg>, 40(<reg>)
327
2
  MI->setDesc(get(SystemZ::LG));
328
2
  MachineInstrBuilder(MF, MI).addReg(Reg64).addImm(40).addReg(0);
329
2
}
330
331
// Emit a zero-extending move from 32-bit GPR SrcReg to 32-bit GPR
332
// DestReg before MBBI in MBB.  Use LowLowOpcode when both DestReg and SrcReg
333
// are low registers, otherwise use RISB[LH]G.  Size is the number of bits
334
// taken from the low end of SrcReg (8 for LLCR, 16 for LLHR and 32 for LR).
335
// KillSrc is true if this move is the last use of SrcReg.
336
MachineInstrBuilder
337
SystemZInstrInfo::emitGRX32Move(MachineBasicBlock &MBB,
338
                                MachineBasicBlock::iterator MBBI,
339
                                const DebugLoc &DL, unsigned DestReg,
340
                                unsigned SrcReg, unsigned LowLowOpcode,
341
                                unsigned Size, bool KillSrc,
342
492
                                bool UndefSrc) const {
343
492
  unsigned Opcode;
344
492
  bool DestIsHigh = isHighReg(DestReg);
345
492
  bool SrcIsHigh = isHighReg(SrcReg);
346
492
  if (DestIsHigh && 
SrcIsHigh18
)
347
4
    Opcode = SystemZ::RISBHH;
348
488
  else if (DestIsHigh && 
!SrcIsHigh14
)
349
14
    Opcode = SystemZ::RISBHL;
350
474
  else if (!DestIsHigh && SrcIsHigh)
351
43
    Opcode = SystemZ::RISBLH;
352
431
  else {
353
431
    return BuildMI(MBB, MBBI, DL, get(LowLowOpcode), DestReg)
354
431
      .addReg(SrcReg, getKillRegState(KillSrc) | getUndefRegState(UndefSrc));
355
431
  }
356
61
  unsigned Rotate = (DestIsHigh != SrcIsHigh ? 
3257
:
04
);
357
61
  return BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
358
61
    .addReg(DestReg, RegState::Undef)
359
61
    .addReg(SrcReg, getKillRegState(KillSrc) | getUndefRegState(UndefSrc))
360
61
    .addImm(32 - Size).addImm(128 + 31).addImm(Rotate);
361
61
}
362
363
MachineInstr *SystemZInstrInfo::commuteInstructionImpl(MachineInstr &MI,
364
                                                       bool NewMI,
365
                                                       unsigned OpIdx1,
366
2.83k
                                                       unsigned OpIdx2) const {
367
2.83k
  auto cloneIfNew = [NewMI](MachineInstr &MI) -> MachineInstr & {
368
270
    if (NewMI)
369
0
      return *MI.getParent()->getParent()->CloneMachineInstr(&MI);
370
270
    return MI;
371
270
  };
372
2.83k
373
2.83k
  switch (MI.getOpcode()) {
374
2.83k
  case SystemZ::SELRMux:
375
270
  case SystemZ::SELFHR:
376
270
  case SystemZ::SELR:
377
270
  case SystemZ::SELGR:
378
270
  case SystemZ::LOCRMux:
379
270
  case SystemZ::LOCFHR:
380
270
  case SystemZ::LOCR:
381
270
  case SystemZ::LOCGR: {
382
270
    auto &WorkingMI = cloneIfNew(MI);
383
270
    // Invert condition.
384
270
    unsigned CCValid = WorkingMI.getOperand(3).getImm();
385
270
    unsigned CCMask = WorkingMI.getOperand(4).getImm();
386
270
    WorkingMI.getOperand(4).setImm(CCMask ^ CCValid);
387
270
    return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
388
270
                                                   OpIdx1, OpIdx2);
389
270
  }
390
2.56k
  default:
391
2.56k
    return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
392
2.83k
  }
393
2.83k
}
394
395
// If MI is a simple load or store for a frame object, return the register
396
// it loads or stores and set FrameIndex to the index of the frame object.
397
// Return 0 otherwise.
398
//
399
// Flag is SimpleBDXLoad for loads and SimpleBDXStore for stores.
400
static int isSimpleMove(const MachineInstr &MI, int &FrameIndex,
401
20.6k
                        unsigned Flag) {
402
20.6k
  const MCInstrDesc &MCID = MI.getDesc();
403
20.6k
  if ((MCID.TSFlags & Flag) && 
MI.getOperand(1).isFI()1.55k
&&
404
20.6k
      
MI.getOperand(2).getImm() == 0335
&&
MI.getOperand(3).getReg() == 0333
) {
405
333
    FrameIndex = MI.getOperand(1).getIndex();
406
333
    return MI.getOperand(0).getReg();
407
333
  }
408
20.3k
  return 0;
409
20.3k
}
410
411
unsigned SystemZInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
412
12.9k
                                               int &FrameIndex) const {
413
12.9k
  return isSimpleMove(MI, FrameIndex, SystemZII::SimpleBDXLoad);
414
12.9k
}
415
416
unsigned SystemZInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
417
7.72k
                                              int &FrameIndex) const {
418
7.72k
  return isSimpleMove(MI, FrameIndex, SystemZII::SimpleBDXStore);
419
7.72k
}
420
421
bool SystemZInstrInfo::isStackSlotCopy(const MachineInstr &MI,
422
                                       int &DestFrameIndex,
423
3.76k
                                       int &SrcFrameIndex) const {
424
3.76k
  // Check for MVC 0(Length,FI1),0(FI2)
425
3.76k
  const MachineFrameInfo &MFI = MI.getParent()->getParent()->getFrameInfo();
426
3.76k
  if (MI.getOpcode() != SystemZ::MVC || 
!MI.getOperand(0).isFI()1
||
427
3.76k
      
MI.getOperand(1).getImm() != 01
||
!MI.getOperand(3).isFI()1
||
428
3.76k
      
MI.getOperand(4).getImm() != 01
)
429
3.76k
    return false;
430
1
431
1
  // Check that Length covers the full slots.
432
1
  int64_t Length = MI.getOperand(2).getImm();
433
1
  unsigned FI1 = MI.getOperand(0).getIndex();
434
1
  unsigned FI2 = MI.getOperand(3).getIndex();
435
1
  if (MFI.getObjectSize(FI1) != Length ||
436
1
      MFI.getObjectSize(FI2) != Length)
437
0
    return false;
438
1
439
1
  DestFrameIndex = FI1;
440
1
  SrcFrameIndex = FI2;
441
1
  return true;
442
1
}
443
444
bool SystemZInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
445
                                     MachineBasicBlock *&TBB,
446
                                     MachineBasicBlock *&FBB,
447
                                     SmallVectorImpl<MachineOperand> &Cond,
448
140k
                                     bool AllowModify) const {
449
140k
  // Most of the code and comments here are boilerplate.
450
140k
451
140k
  // Start from the bottom of the block and work up, examining the
452
140k
  // terminator instructions.
453
140k
  MachineBasicBlock::iterator I = MBB.end();
454
184k
  while (I != MBB.begin()) {
455
180k
    --I;
456
180k
    if (I->isDebugInstr())
457
9
      continue;
458
180k
459
180k
    // Working from the bottom, when we see a non-terminator instruction, we're
460
180k
    // done.
461
180k
    if (!isUnpredicatedTerminator(*I))
462
71.3k
      break;
463
109k
464
109k
    // A terminator that isn't a branch can't easily be handled by this
465
109k
    // analysis.
466
109k
    if (!I->isBranch())
467
65.2k
      return true;
468
44.3k
469
44.3k
    // Can't handle indirect branches.
470
44.3k
    SystemZII::Branch Branch(getBranchInfo(*I));
471
44.3k
    if (!Branch.Target->isMBB())
472
224
      return true;
473
44.0k
474
44.0k
    // Punt on compound branches.
475
44.0k
    if (Branch.Type != SystemZII::BranchNormal)
476
154
      return true;
477
43.9k
478
43.9k
    if (Branch.CCMask == SystemZ::CCMASK_ANY) {
479
6.29k
      // Handle unconditional branches.
480
6.29k
      if (!AllowModify) {
481
4.06k
        TBB = Branch.Target->getMBB();
482
4.06k
        continue;
483
4.06k
      }
484
2.22k
485
2.22k
      // If the block has any instructions after a JMP, delete them.
486
2.22k
      while (std::next(I) != MBB.end())
487
0
        std::next(I)->eraseFromParent();
488
2.22k
489
2.22k
      Cond.clear();
490
2.22k
      FBB = nullptr;
491
2.22k
492
2.22k
      // Delete the JMP if it's equivalent to a fall-through.
493
2.22k
      if (MBB.isLayoutSuccessor(Branch.Target->getMBB())) {
494
682
        TBB = nullptr;
495
682
        I->eraseFromParent();
496
682
        I = MBB.end();
497
682
        continue;
498
682
      }
499
1.54k
500
1.54k
      // TBB is used to indicate the unconditinal destination.
501
1.54k
      TBB = Branch.Target->getMBB();
502
1.54k
      continue;
503
1.54k
    }
504
37.6k
505
37.6k
    // Working from the bottom, handle the first conditional branch.
506
37.6k
    if (Cond.empty()) {
507
37.6k
      // FIXME: add X86-style branch swap
508
37.6k
      FBB = TBB;
509
37.6k
      TBB = Branch.Target->getMBB();
510
37.6k
      Cond.push_back(MachineOperand::CreateImm(Branch.CCValid));
511
37.6k
      Cond.push_back(MachineOperand::CreateImm(Branch.CCMask));
512
37.6k
      continue;
513
37.6k
    }
514
0
515
0
    // Handle subsequent conditional branches.
516
0
    assert(Cond.size() == 2 && TBB && "Should have seen a conditional branch");
517
0
518
0
    // Only handle the case where all conditional branches branch to the same
519
0
    // destination.
520
0
    if (TBB != Branch.Target->getMBB())
521
0
      return true;
522
0
523
0
    // If the conditions are the same, we can leave them alone.
524
0
    unsigned OldCCValid = Cond[0].getImm();
525
0
    unsigned OldCCMask = Cond[1].getImm();
526
0
    if (OldCCValid == Branch.CCValid && OldCCMask == Branch.CCMask)
527
0
      continue;
528
0
529
0
    // FIXME: Try combining conditions like X86 does.  Should be easy on Z!
530
0
    return false;
531
0
  }
532
140k
533
140k
  
return false74.7k
;
534
140k
}
535
536
unsigned SystemZInstrInfo::removeBranch(MachineBasicBlock &MBB,
537
7.24k
                                        int *BytesRemoved) const {
538
7.24k
  assert(!BytesRemoved && "code size not handled");
539
7.24k
540
7.24k
  // Most of the code and comments here are boilerplate.
541
7.24k
  MachineBasicBlock::iterator I = MBB.end();
542
7.24k
  unsigned Count = 0;
543
7.24k
544
14.6k
  while (I != MBB.begin()) {
545
14.3k
    --I;
546
14.3k
    if (I->isDebugInstr())
547
1
      continue;
548
14.3k
    if (!I->isBranch())
549
6.97k
      break;
550
7.36k
    if (!getBranchInfo(*I).Target->isMBB())
551
0
      break;
552
7.36k
    // Remove the branch.
553
7.36k
    I->eraseFromParent();
554
7.36k
    I = MBB.end();
555
7.36k
    ++Count;
556
7.36k
  }
557
7.24k
558
7.24k
  return Count;
559
7.24k
}
560
561
bool SystemZInstrInfo::
562
9.12k
reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
563
9.12k
  assert(Cond.size() == 2 && "Invalid condition");
564
9.12k
  Cond[1].setImm(Cond[1].getImm() ^ Cond[0].getImm());
565
9.12k
  return false;
566
9.12k
}
567
568
unsigned SystemZInstrInfo::insertBranch(MachineBasicBlock &MBB,
569
                                        MachineBasicBlock *TBB,
570
                                        MachineBasicBlock *FBB,
571
                                        ArrayRef<MachineOperand> Cond,
572
                                        const DebugLoc &DL,
573
6.40k
                                        int *BytesAdded) const {
574
6.40k
  // In this function we output 32-bit branches, which should always
575
6.40k
  // have enough range.  They can be shortened and relaxed by later code
576
6.40k
  // in the pipeline, if desired.
577
6.40k
578
6.40k
  // Shouldn't be a fall through.
579
6.40k
  assert(TBB && "insertBranch must not be told to insert a fallthrough");
580
6.40k
  assert((Cond.size() == 2 || Cond.size() == 0) &&
581
6.40k
         "SystemZ branch conditions have one component!");
582
6.40k
  assert(!BytesAdded && "code size not handled");
583
6.40k
584
6.40k
  if (Cond.empty()) {
585
591
    // Unconditional branch?
586
591
    assert(!FBB && "Unconditional branch with multiple successors!");
587
591
    BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(TBB);
588
591
    return 1;
589
591
  }
590
5.81k
591
5.81k
  // Conditional branch.
592
5.81k
  unsigned Count = 0;
593
5.81k
  unsigned CCValid = Cond[0].getImm();
594
5.81k
  unsigned CCMask = Cond[1].getImm();
595
5.81k
  BuildMI(&MBB, DL, get(SystemZ::BRC))
596
5.81k
    .addImm(CCValid).addImm(CCMask).addMBB(TBB);
597
5.81k
  ++Count;
598
5.81k
599
5.81k
  if (FBB) {
600
110
    // Two-way Conditional branch. Insert the second branch.
601
110
    BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(FBB);
602
110
    ++Count;
603
110
  }
604
5.81k
  return Count;
605
5.81k
}
606
607
bool SystemZInstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
608
                                      unsigned &SrcReg2, int &Mask,
609
1.58k
                                      int &Value) const {
610
1.58k
  assert(MI.isCompare() && "Caller should have checked for a comparison");
611
1.58k
612
1.58k
  if (MI.getNumExplicitOperands() == 2 && 
MI.getOperand(0).isReg()1.21k
&&
613
1.58k
      
MI.getOperand(1).isImm()1.21k
) {
614
730
    SrcReg = MI.getOperand(0).getReg();
615
730
    SrcReg2 = 0;
616
730
    Value = MI.getOperand(1).getImm();
617
730
    Mask = ~0;
618
730
    return true;
619
730
  }
620
859
621
859
  return false;
622
859
}
623
624
bool SystemZInstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
625
                                       ArrayRef<MachineOperand> Pred,
626
                                       unsigned TrueReg, unsigned FalseReg,
627
                                       int &CondCycles, int &TrueCycles,
628
737
                                       int &FalseCycles) const {
629
737
  // Not all subtargets have LOCR instructions.
630
737
  if (!STI.hasLoadStoreOnCond())
631
649
    return false;
632
88
  if (Pred.size() != 2)
633
0
    return false;
634
88
635
88
  // Check register classes.
636
88
  const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
637
88
  const TargetRegisterClass *RC =
638
88
    RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
639
88
  if (!RC)
640
0
    return false;
641
88
642
88
  // We have LOCR instructions for 32 and 64 bit general purpose registers.
643
88
  if ((STI.hasLoadStoreOnCond2() &&
644
88
       
SystemZ::GRX32BitRegClass.hasSubClassEq(RC)68
) ||
645
88
      
SystemZ::GR32BitRegClass.hasSubClassEq(RC)64
||
646
88
      
SystemZ::GR64BitRegClass.hasSubClassEq(RC)61
) {
647
42
    CondCycles = 2;
648
42
    TrueCycles = 2;
649
42
    FalseCycles = 2;
650
42
    return true;
651
42
  }
652
46
653
46
  // Can't do anything else.
654
46
  return false;
655
46
}
656
657
void SystemZInstrInfo::insertSelect(MachineBasicBlock &MBB,
658
                                    MachineBasicBlock::iterator I,
659
                                    const DebugLoc &DL, unsigned DstReg,
660
                                    ArrayRef<MachineOperand> Pred,
661
                                    unsigned TrueReg,
662
34
                                    unsigned FalseReg) const {
663
34
  MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
664
34
  const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
665
34
666
34
  assert(Pred.size() == 2 && "Invalid condition");
667
34
  unsigned CCValid = Pred[0].getImm();
668
34
  unsigned CCMask = Pred[1].getImm();
669
34
670
34
  unsigned Opc;
671
34
  if (SystemZ::GRX32BitRegClass.hasSubClassEq(RC)) {
672
22
    if (STI.hasMiscellaneousExtensions3())
673
12
      Opc = SystemZ::SELRMux;
674
10
    else if (STI.hasLoadStoreOnCond2())
675
8
      Opc = SystemZ::LOCRMux;
676
2
    else {
677
2
      Opc = SystemZ::LOCR;
678
2
      MRI.constrainRegClass(DstReg, &SystemZ::GR32BitRegClass);
679
2
      unsigned TReg = MRI.createVirtualRegister(&SystemZ::GR32BitRegClass);
680
2
      unsigned FReg = MRI.createVirtualRegister(&SystemZ::GR32BitRegClass);
681
2
      BuildMI(MBB, I, DL, get(TargetOpcode::COPY), TReg).addReg(TrueReg);
682
2
      BuildMI(MBB, I, DL, get(TargetOpcode::COPY), FReg).addReg(FalseReg);
683
2
      TrueReg = TReg;
684
2
      FalseReg = FReg;
685
2
    }
686
22
  } else 
if (12
SystemZ::GR64BitRegClass.hasSubClassEq(RC)12
) {
687
12
    if (STI.hasMiscellaneousExtensions3())
688
6
      Opc = SystemZ::SELGR;
689
6
    else
690
6
      Opc = SystemZ::LOCGR;
691
12
  } else
692
12
    
llvm_unreachable0
("Invalid register class");
693
34
694
34
  BuildMI(MBB, I, DL, get(Opc), DstReg)
695
34
    .addReg(FalseReg).addReg(TrueReg)
696
34
    .addImm(CCValid).addImm(CCMask);
697
34
}
698
699
bool SystemZInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
700
                                     unsigned Reg,
701
3.07k
                                     MachineRegisterInfo *MRI) const {
702
3.07k
  unsigned DefOpc = DefMI.getOpcode();
703
3.07k
  if (DefOpc != SystemZ::LHIMux && 
DefOpc != SystemZ::LHI2.49k
&&
704
3.07k
      
DefOpc != SystemZ::LGHI2.21k
)
705
1.91k
    return false;
706
1.16k
  if (DefMI.getOperand(0).getReg() != Reg)
707
0
    return false;
708
1.16k
  int32_t ImmVal = (int32_t)DefMI.getOperand(1).getImm();
709
1.16k
710
1.16k
  unsigned UseOpc = UseMI.getOpcode();
711
1.16k
  unsigned NewUseOpc;
712
1.16k
  unsigned UseIdx;
713
1.16k
  int CommuteIdx = -1;
714
1.16k
  bool TieOps = false;
715
1.16k
  switch (UseOpc) {
716
1.16k
  case SystemZ::SELRMux:
717
4
    TieOps = true;
718
4
    LLVM_FALLTHROUGH;
719
8
  case SystemZ::LOCRMux:
720
8
    if (!STI.hasLoadStoreOnCond2())
721
0
      return false;
722
8
    NewUseOpc = SystemZ::LOCHIMux;
723
8
    if (UseMI.getOperand(2).getReg() == Reg)
724
4
      UseIdx = 2;
725
4
    else if (UseMI.getOperand(1).getReg() == Reg)
726
4
      UseIdx = 2, CommuteIdx = 1;
727
0
    else
728
0
      return false;
729
8
    break;
730
8
  case SystemZ::SELGR:
731
2
    TieOps = true;
732
2
    LLVM_FALLTHROUGH;
733
4
  case SystemZ::LOCGR:
734
4
    if (!STI.hasLoadStoreOnCond2())
735
0
      return false;
736
4
    NewUseOpc = SystemZ::LOCGHI;
737
4
    if (UseMI.getOperand(2).getReg() == Reg)
738
2
      UseIdx = 2;
739
2
    else if (UseMI.getOperand(1).getReg() == Reg)
740
2
      UseIdx = 2, CommuteIdx = 1;
741
0
    else
742
0
      return false;
743
4
    break;
744
1.15k
  default:
745
1.15k
    return false;
746
12
  }
747
12
748
12
  if (CommuteIdx != -1)
749
6
    if (!commuteInstruction(UseMI, false, CommuteIdx, UseIdx))
750
0
      return false;
751
12
752
12
  bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
753
12
  UseMI.setDesc(get(NewUseOpc));
754
12
  if (TieOps)
755
6
    UseMI.tieOperands(0, 1);
756
12
  UseMI.getOperand(UseIdx).ChangeToImmediate(ImmVal);
757
12
  if (DeleteDef)
758
12
    DefMI.eraseFromParent();
759
12
760
12
  return true;
761
12
}
762
763
12.1k
bool SystemZInstrInfo::isPredicable(const MachineInstr &MI) const {
764
12.1k
  unsigned Opcode = MI.getOpcode();
765
12.1k
  if (Opcode == SystemZ::Return ||
766
12.1k
      
Opcode == SystemZ::Trap11.0k
||
767
12.1k
      
Opcode == SystemZ::CallJG11.0k
||
768
12.1k
      
Opcode == SystemZ::CallBR10.7k
)
769
1.41k
    return true;
770
10.7k
  return false;
771
10.7k
}
772
773
bool SystemZInstrInfo::
774
isProfitableToIfCvt(MachineBasicBlock &MBB,
775
                    unsigned NumCycles, unsigned ExtraPredCycles,
776
3.38k
                    BranchProbability Probability) const {
777
3.38k
  // Avoid using conditional returns at the end of a loop (since then
778
3.38k
  // we'd need to emit an unconditional branch to the beginning anyway,
779
3.38k
  // making the loop body longer).  This doesn't apply for low-probability
780
3.38k
  // loops (eg. compare-and-swap retry), so just decide based on branch
781
3.38k
  // probability instead of looping structure.
782
3.38k
  // However, since Compare and Trap instructions cost the same as a regular
783
3.38k
  // Compare instruction, we should allow the if conversion to convert this
784
3.38k
  // into a Conditional Compare regardless of the branch probability.
785
3.38k
  if (MBB.getLastNonDebugInstr()->getOpcode() != SystemZ::Trap &&
786
3.38k
      
MBB.succ_empty()3.32k
&&
Probability < BranchProbability(1, 8)1.31k
)
787
13
    return false;
788
3.37k
  // For now only convert single instructions.
789
3.37k
  return NumCycles == 1;
790
3.37k
}
791
792
bool SystemZInstrInfo::
793
isProfitableToIfCvt(MachineBasicBlock &TMBB,
794
                    unsigned NumCyclesT, unsigned ExtraPredCyclesT,
795
                    MachineBasicBlock &FMBB,
796
                    unsigned NumCyclesF, unsigned ExtraPredCyclesF,
797
88
                    BranchProbability Probability) const {
798
88
  // For now avoid converting mutually-exclusive cases.
799
88
  return false;
800
88
}
801
802
bool SystemZInstrInfo::
803
isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
804
3.01k
                          BranchProbability Probability) const {
805
3.01k
  // For now only duplicate single instructions.
806
3.01k
  return NumCycles == 1;
807
3.01k
}
808
809
bool SystemZInstrInfo::PredicateInstruction(
810
831
    MachineInstr &MI, ArrayRef<MachineOperand> Pred) const {
811
831
  assert(Pred.size() == 2 && "Invalid condition");
812
831
  unsigned CCValid = Pred[0].getImm();
813
831
  unsigned CCMask = Pred[1].getImm();
814
831
  assert(CCMask > 0 && CCMask < 15 && "Invalid predicate");
815
831
  unsigned Opcode = MI.getOpcode();
816
831
  if (Opcode == SystemZ::Trap) {
817
34
    MI.setDesc(get(SystemZ::CondTrap));
818
34
    MachineInstrBuilder(*MI.getParent()->getParent(), MI)
819
34
      .addImm(CCValid).addImm(CCMask)
820
34
      .addReg(SystemZ::CC, RegState::Implicit);
821
34
    return true;
822
34
  }
823
797
  if (Opcode == SystemZ::Return) {
824
668
    MI.setDesc(get(SystemZ::CondReturn));
825
668
    MachineInstrBuilder(*MI.getParent()->getParent(), MI)
826
668
      .addImm(CCValid).addImm(CCMask)
827
668
      .addReg(SystemZ::CC, RegState::Implicit);
828
668
    return true;
829
668
  }
830
129
  if (Opcode == SystemZ::CallJG) {
831
106
    MachineOperand FirstOp = MI.getOperand(0);
832
106
    const uint32_t *RegMask = MI.getOperand(1).getRegMask();
833
106
    MI.RemoveOperand(1);
834
106
    MI.RemoveOperand(0);
835
106
    MI.setDesc(get(SystemZ::CallBRCL));
836
106
    MachineInstrBuilder(*MI.getParent()->getParent(), MI)
837
106
        .addImm(CCValid)
838
106
        .addImm(CCMask)
839
106
        .add(FirstOp)
840
106
        .addRegMask(RegMask)
841
106
        .addReg(SystemZ::CC, RegState::Implicit);
842
106
    return true;
843
106
  }
844
23
  if (Opcode == SystemZ::CallBR) {
845
23
    const uint32_t *RegMask = MI.getOperand(0).getRegMask();
846
23
    MI.RemoveOperand(0);
847
23
    MI.setDesc(get(SystemZ::CallBCR));
848
23
    MachineInstrBuilder(*MI.getParent()->getParent(), MI)
849
23
      .addImm(CCValid).addImm(CCMask)
850
23
      .addRegMask(RegMask)
851
23
      .addReg(SystemZ::CC, RegState::Implicit);
852
23
    return true;
853
23
  }
854
0
  return false;
855
0
}
856
857
void SystemZInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
858
                                   MachineBasicBlock::iterator MBBI,
859
                                   const DebugLoc &DL, unsigned DestReg,
860
2.58k
                                   unsigned SrcReg, bool KillSrc) const {
861
2.58k
  // Split 128-bit GPR moves into two 64-bit moves. Add implicit uses of the
862
2.58k
  // super register in case one of the subregs is undefined.
863
2.58k
  // This handles ADDR128 too.
864
2.58k
  if (SystemZ::GR128BitRegClass.contains(DestReg, SrcReg)) {
865
31
    copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_h64),
866
31
                RI.getSubReg(SrcReg, SystemZ::subreg_h64), KillSrc);
867
31
    MachineInstrBuilder(*MBB.getParent(), std::prev(MBBI))
868
31
      .addReg(SrcReg, RegState::Implicit);
869
31
    copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_l64),
870
31
                RI.getSubReg(SrcReg, SystemZ::subreg_l64), KillSrc);
871
31
    MachineInstrBuilder(*MBB.getParent(), std::prev(MBBI))
872
31
      .addReg(SrcReg, (getKillRegState(KillSrc) | RegState::Implicit));
873
31
    return;
874
31
  }
875
2.55k
876
2.55k
  if (SystemZ::GRX32BitRegClass.contains(DestReg, SrcReg)) {
877
366
    emitGRX32Move(MBB, MBBI, DL, DestReg, SrcReg, SystemZ::LR, 32, KillSrc,
878
366
                  false);
879
366
    return;
880
366
  }
881
2.18k
882
2.18k
  // Move 128-bit floating-point values between VR128 and FP128.
883
2.18k
  if (SystemZ::VR128BitRegClass.contains(DestReg) &&
884
2.18k
      
SystemZ::FP128BitRegClass.contains(SrcReg)82
) {
885
6
    unsigned SrcRegHi =
886
6
      RI.getMatchingSuperReg(RI.getSubReg(SrcReg, SystemZ::subreg_h64),
887
6
                             SystemZ::subreg_h64, &SystemZ::VR128BitRegClass);
888
6
    unsigned SrcRegLo =
889
6
      RI.getMatchingSuperReg(RI.getSubReg(SrcReg, SystemZ::subreg_l64),
890
6
                             SystemZ::subreg_h64, &SystemZ::VR128BitRegClass);
891
6
892
6
    BuildMI(MBB, MBBI, DL, get(SystemZ::VMRHG), DestReg)
893
6
      .addReg(SrcRegHi, getKillRegState(KillSrc))
894
6
      .addReg(SrcRegLo, getKillRegState(KillSrc));
895
6
    return;
896
6
  }
897
2.18k
  if (SystemZ::FP128BitRegClass.contains(DestReg) &&
898
2.18k
      
SystemZ::VR128BitRegClass.contains(SrcReg)10
) {
899
5
    unsigned DestRegHi =
900
5
      RI.getMatchingSuperReg(RI.getSubReg(DestReg, SystemZ::subreg_h64),
901
5
                             SystemZ::subreg_h64, &SystemZ::VR128BitRegClass);
902
5
    unsigned DestRegLo =
903
5
      RI.getMatchingSuperReg(RI.getSubReg(DestReg, SystemZ::subreg_l64),
904
5
                             SystemZ::subreg_h64, &SystemZ::VR128BitRegClass);
905
5
906
5
    if (DestRegHi != SrcReg)
907
0
      copyPhysReg(MBB, MBBI, DL, DestRegHi, SrcReg, false);
908
5
    BuildMI(MBB, MBBI, DL, get(SystemZ::VREPG), DestRegLo)
909
5
      .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1);
910
5
    return;
911
5
  }
912
2.17k
913
2.17k
  // Move CC value from/to a GR32.
914
2.17k
  if (SrcReg == SystemZ::CC) {
915
0
    auto MIB = BuildMI(MBB, MBBI, DL, get(SystemZ::IPM), DestReg);
916
0
    if (KillSrc) {
917
0
      const MachineFunction *MF = MBB.getParent();
918
0
      const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
919
0
      MIB->addRegisterKilled(SrcReg, TRI);
920
0
    }
921
0
    return;
922
0
  }
923
2.17k
  if (DestReg == SystemZ::CC) {
924
0
    BuildMI(MBB, MBBI, DL, get(SystemZ::TMLH))
925
0
      .addReg(SrcReg, getKillRegState(KillSrc))
926
0
      .addImm(3 << (SystemZ::IPM_CC - 16));
927
0
    return;
928
0
  }
929
2.17k
930
2.17k
  // Everything else needs only one instruction.
931
2.17k
  unsigned Opcode;
932
2.17k
  if (SystemZ::GR64BitRegClass.contains(DestReg, SrcReg))
933
696
    Opcode = SystemZ::LGR;
934
1.48k
  else if (SystemZ::FP32BitRegClass.contains(DestReg, SrcReg))
935
316
    // For z13 we prefer LDR over LER to avoid partial register dependencies.
936
316
    Opcode = STI.hasVector() ? 
SystemZ::LDR3252
:
SystemZ::LER264
;
937
1.16k
  else if (SystemZ::FP64BitRegClass.contains(DestReg, SrcReg))
938
1.05k
    Opcode = SystemZ::LDR;
939
105
  else if (SystemZ::FP128BitRegClass.contains(DestReg, SrcReg))
940
5
    Opcode = SystemZ::LXR;
941
100
  else if (SystemZ::VR32BitRegClass.contains(DestReg, SrcReg))
942
0
    Opcode = SystemZ::VLR32;
943
100
  else if (SystemZ::VR64BitRegClass.contains(DestReg, SrcReg))
944
0
    Opcode = SystemZ::VLR64;
945
100
  else if (SystemZ::VR128BitRegClass.contains(DestReg, SrcReg))
946
76
    Opcode = SystemZ::VLR;
947
24
  else if (SystemZ::AR32BitRegClass.contains(DestReg, SrcReg))
948
0
    Opcode = SystemZ::CPYA;
949
24
  else if (SystemZ::AR32BitRegClass.contains(DestReg) &&
950
24
           
SystemZ::GR32BitRegClass.contains(SrcReg)0
)
951
0
    Opcode = SystemZ::SAR;
952
24
  else if (SystemZ::GR32BitRegClass.contains(DestReg) &&
953
24
           SystemZ::AR32BitRegClass.contains(SrcReg))
954
24
    Opcode = SystemZ::EAR;
955
24
  else
956
24
    
llvm_unreachable0
("Impossible reg-to-reg copy");
957
2.17k
958
2.17k
  BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
959
2.17k
    .addReg(SrcReg, getKillRegState(KillSrc));
960
2.17k
}
961
962
void SystemZInstrInfo::storeRegToStackSlot(
963
    MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg,
964
    bool isKill, int FrameIdx, const TargetRegisterClass *RC,
965
1.40k
    const TargetRegisterInfo *TRI) const {
966
1.40k
  DebugLoc DL = MBBI != MBB.end() ? 
MBBI->getDebugLoc()1.39k
:
DebugLoc()5
;
967
1.40k
968
1.40k
  // Callers may expect a single instruction, so keep 128-bit moves
969
1.40k
  // together for now and lower them after register allocation.
970
1.40k
  unsigned LoadOpcode, StoreOpcode;
971
1.40k
  getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode);
972
1.40k
  addFrameReference(BuildMI(MBB, MBBI, DL, get(StoreOpcode))
973
1.40k
                        .addReg(SrcReg, getKillRegState(isKill)),
974
1.40k
                    FrameIdx);
975
1.40k
}
976
977
void SystemZInstrInfo::loadRegFromStackSlot(
978
    MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg,
979
    int FrameIdx, const TargetRegisterClass *RC,
980
1.38k
    const TargetRegisterInfo *TRI) const {
981
1.38k
  DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : 
DebugLoc()0
;
982
1.38k
983
1.38k
  // Callers may expect a single instruction, so keep 128-bit moves
984
1.38k
  // together for now and lower them after register allocation.
985
1.38k
  unsigned LoadOpcode, StoreOpcode;
986
1.38k
  getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode);
987
1.38k
  addFrameReference(BuildMI(MBB, MBBI, DL, get(LoadOpcode), DestReg),
988
1.38k
                    FrameIdx);
989
1.38k
}
990
991
// Return true if MI is a simple load or store with a 12-bit displacement
992
// and no index.  Flag is SimpleBDXLoad for loads and SimpleBDXStore for stores.
993
342
static bool isSimpleBD12Move(const MachineInstr *MI, unsigned Flag) {
994
342
  const MCInstrDesc &MCID = MI->getDesc();
995
342
  return ((MCID.TSFlags & Flag) &&
996
342
          
isUInt<12>(MI->getOperand(2).getImm())179
&&
997
342
          
MI->getOperand(3).getReg() == 0179
);
998
342
}
999
1000
namespace {
1001
1002
struct LogicOp {
1003
16
  LogicOp() = default;
1004
  LogicOp(unsigned regSize, unsigned immLSB, unsigned immSize)
1005
345
    : RegSize(regSize), ImmLSB(immLSB), ImmSize(immSize) {}
1006
1007
361
  explicit operator bool() const { return RegSize; }
1008
1009
  unsigned RegSize = 0;
1010
  unsigned ImmLSB = 0;
1011
  unsigned ImmSize = 0;
1012
};
1013
1014
} // end anonymous namespace
1015
1016
361
static LogicOp interpretAndImmediate(unsigned Opcode) {
1017
361
  switch (Opcode) {
1018
361
  
case SystemZ::NILMux: return LogicOp(32, 0, 16)4
;
1019
361
  
case SystemZ::NIHMux: return LogicOp(32, 16, 16)1
;
1020
361
  
case SystemZ::NILL64: return LogicOp(64, 0, 16)302
;
1021
361
  
case SystemZ::NILH64: return LogicOp(64, 16, 16)4
;
1022
361
  
case SystemZ::NIHL64: return LogicOp(64, 32, 16)4
;
1023
361
  
case SystemZ::NIHH64: return LogicOp(64, 48, 16)4
;
1024
361
  
case SystemZ::NIFMux: return LogicOp(32, 0, 32)15
;
1025
361
  
case SystemZ::NILF64: return LogicOp(64, 0, 32)4
;
1026
361
  
case SystemZ::NIHF64: return LogicOp(64, 32, 32)7
;
1027
361
  
default: return LogicOp()16
;
1028
361
  }
1029
361
}
1030
1031
592
static void transferDeadCC(MachineInstr *OldMI, MachineInstr *NewMI) {
1032
592
  if (OldMI->registerDefIsDead(SystemZ::CC)) {
1033
410
    MachineOperand *CCDef = NewMI->findRegisterDefOperand(SystemZ::CC);
1034
410
    if (CCDef != nullptr)
1035
393
      CCDef->setIsDead(true);
1036
410
  }
1037
592
}
1038
1039
MachineInstr *SystemZInstrInfo::convertToThreeAddress(
1040
361
    MachineFunction::iterator &MFI, MachineInstr &MI, LiveVariables *LV) const {
1041
361
  MachineBasicBlock *MBB = MI.getParent();
1042
361
1043
361
  // Try to convert an AND into an RISBG-type instruction.
1044
361
  // TODO: It might be beneficial to select RISBG and shorten to AND instead.
1045
361
  if (LogicOp And = interpretAndImmediate(MI.getOpcode())) {
1046
345
    uint64_t Imm = MI.getOperand(2).getImm() << And.ImmLSB;
1047
345
    // AND IMMEDIATE leaves the other bits of the register unchanged.
1048
345
    Imm |= allOnes(And.RegSize) & ~(allOnes(And.ImmSize) << And.ImmLSB);
1049
345
    unsigned Start, End;
1050
345
    if (isRxSBGMask(Imm, And.RegSize, Start, End)) {
1051
318
      unsigned NewOpcode;
1052
318
      if (And.RegSize == 64) {
1053
301
        NewOpcode = SystemZ::RISBG;
1054
301
        // Prefer RISBGN if available, since it does not clobber CC.
1055
301
        if (STI.hasMiscellaneousExtensions())
1056
0
          NewOpcode = SystemZ::RISBGN;
1057
301
      } else {
1058
17
        NewOpcode = SystemZ::RISBMux;
1059
17
        Start &= 31;
1060
17
        End &= 31;
1061
17
      }
1062
318
      MachineOperand &Dest = MI.getOperand(0);
1063
318
      MachineOperand &Src = MI.getOperand(1);
1064
318
      MachineInstrBuilder MIB =
1065
318
          BuildMI(*MBB, MI, MI.getDebugLoc(), get(NewOpcode))
1066
318
              .add(Dest)
1067
318
              .addReg(0)
1068
318
              .addReg(Src.getReg(), getKillRegState(Src.isKill()),
1069
318
                      Src.getSubReg())
1070
318
              .addImm(Start)
1071
318
              .addImm(End + 128)
1072
318
              .addImm(0);
1073
318
      if (LV) {
1074
318
        unsigned NumOps = MI.getNumOperands();
1075
1.27k
        for (unsigned I = 1; I < NumOps; 
++I954
) {
1076
954
          MachineOperand &Op = MI.getOperand(I);
1077
954
          if (Op.isReg() && 
Op.isKill()636
)
1078
10
            LV->replaceKillInstruction(Op.getReg(), MI, *MIB);
1079
954
        }
1080
318
      }
1081
318
      transferDeadCC(&MI, MIB);
1082
318
      return MIB;
1083
318
    }
1084
43
  }
1085
43
  return nullptr;
1086
43
}
1087
1088
MachineInstr *SystemZInstrInfo::foldMemoryOperandImpl(
1089
    MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
1090
    MachineBasicBlock::iterator InsertPt, int FrameIndex,
1091
1.28k
    LiveIntervals *LIS, VirtRegMap *VRM) const {
1092
1.28k
  const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
1093
1.28k
  const MachineFrameInfo &MFI = MF.getFrameInfo();
1094
1.28k
  unsigned Size = MFI.getObjectSize(FrameIndex);
1095
1.28k
  unsigned Opcode = MI.getOpcode();
1096
1.28k
1097
1.28k
  if (Ops.size() == 2 && 
Ops[0] == 03
&&
Ops[1] == 13
) {
1098
3
    if (LIS != nullptr && (Opcode == SystemZ::LA || 
Opcode == SystemZ::LAY0
) &&
1099
3
        isInt<8>(MI.getOperand(2).getImm()) && !MI.getOperand(3).getReg()) {
1100
3
1101
3
      // Check CC liveness, since new instruction introduces a dead
1102
3
      // def of CC.
1103
3
      MCRegUnitIterator CCUnit(SystemZ::CC, TRI);
1104
3
      LiveRange &CCLiveRange = LIS->getRegUnit(*CCUnit);
1105
3
      ++CCUnit;
1106
3
      assert(!CCUnit.isValid() && "CC only has one reg unit.");
1107
3
      SlotIndex MISlot =
1108
3
          LIS->getSlotIndexes()->getInstructionIndex(MI).getRegSlot();
1109
3
      if (!CCLiveRange.liveAt(MISlot)) {
1110
3
        // LA(Y) %reg, CONST(%reg) -> AGSI %mem, CONST
1111
3
        MachineInstr *BuiltMI = BuildMI(*InsertPt->getParent(), InsertPt,
1112
3
                                        MI.getDebugLoc(), get(SystemZ::AGSI))
1113
3
                                    .addFrameIndex(FrameIndex)
1114
3
                                    .addImm(0)
1115
3
                                    .addImm(MI.getOperand(2).getImm());
1116
3
        BuiltMI->findRegisterDefOperand(SystemZ::CC)->setIsDead(true);
1117
3
        CCLiveRange.createDeadDef(MISlot, LIS->getVNInfoAllocator());
1118
3
        return BuiltMI;
1119
3
      }
1120
0
    }
1121
0
    return nullptr;
1122
0
  }
1123
1.28k
1124
1.28k
  // All other cases require a single operand.
1125
1.28k
  if (Ops.size() != 1)
1126
0
    return nullptr;
1127
1.28k
1128
1.28k
  unsigned OpNum = Ops[0];
1129
1.28k
  assert(Size * 8 ==
1130
1.28k
           TRI->getRegSizeInBits(*MF.getRegInfo()
1131
1.28k
                               .getRegClass(MI.getOperand(OpNum).getReg())) &&
1132
1.28k
         "Invalid size combination");
1133
1.28k
1134
1.28k
  if ((Opcode == SystemZ::AHI || 
Opcode == SystemZ::AGHI1.26k
) &&
OpNum == 035
&&
1135
1.28k
      
isInt<8>(MI.getOperand(2).getImm())35
) {
1136
35
    // A(G)HI %reg, CONST -> A(G)SI %mem, CONST
1137
35
    Opcode = (Opcode == SystemZ::AHI ? 
SystemZ::ASI18
:
SystemZ::AGSI17
);
1138
35
    MachineInstr *BuiltMI =
1139
35
        BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(), get(Opcode))
1140
35
            .addFrameIndex(FrameIndex)
1141
35
            .addImm(0)
1142
35
            .addImm(MI.getOperand(2).getImm());
1143
35
    transferDeadCC(&MI, BuiltMI);
1144
35
    return BuiltMI;
1145
35
  }
1146
1.25k
1147
1.25k
  if ((Opcode == SystemZ::ALFI && 
OpNum == 08
&&
1148
1.25k
       
isInt<8>((int32_t)MI.getOperand(2).getImm())8
) ||
1149
1.25k
      
(1.24k
Opcode == SystemZ::ALGFI1.24k
&&
OpNum == 04
&&
1150
1.24k
       
isInt<8>((int64_t)MI.getOperand(2).getImm())4
)) {
1151
12
    // AL(G)FI %reg, CONST -> AL(G)SI %mem, CONST
1152
12
    Opcode = (Opcode == SystemZ::ALFI ? 
SystemZ::ALSI8
:
SystemZ::ALGSI4
);
1153
12
    MachineInstr *BuiltMI =
1154
12
        BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(), get(Opcode))
1155
12
            .addFrameIndex(FrameIndex)
1156
12
            .addImm(0)
1157
12
            .addImm((int8_t)MI.getOperand(2).getImm());
1158
12
    transferDeadCC(&MI, BuiltMI);
1159
12
    return BuiltMI;
1160
12
  }
1161
1.23k
1162
1.23k
  if ((Opcode == SystemZ::SLFI && 
OpNum == 08
&&
1163
1.23k
       
isInt<8>((int32_t)-MI.getOperand(2).getImm())8
) ||
1164
1.23k
      
(1.23k
Opcode == SystemZ::SLGFI1.23k
&&
OpNum == 04
&&
1165
1.23k
       
isInt<8>((int64_t)-MI.getOperand(2).getImm())4
)) {
1166
12
    // SL(G)FI %reg, CONST -> AL(G)SI %mem, -CONST
1167
12
    Opcode = (Opcode == SystemZ::SLFI ? 
SystemZ::ALSI8
:
SystemZ::ALGSI4
);
1168
12
    MachineInstr *BuiltMI =
1169
12
        BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(), get(Opcode))
1170
12
            .addFrameIndex(FrameIndex)
1171
12
            .addImm(0)
1172
12
            .addImm((int8_t)-MI.getOperand(2).getImm());
1173
12
    transferDeadCC(&MI, BuiltMI);
1174
12
    return BuiltMI;
1175
12
  }
1176
1.22k
1177
1.22k
  if (Opcode == SystemZ::LGDR || 
Opcode == SystemZ::LDGR1.22k
) {
1178
9
    bool Op0IsGPR = (Opcode == SystemZ::LGDR);
1179
9
    bool Op1IsGPR = (Opcode == SystemZ::LDGR);
1180
9
    // If we're spilling the destination of an LDGR or LGDR, store the
1181
9
    // source register instead.
1182
9
    if (OpNum == 0) {
1183
5
      unsigned StoreOpcode = Op1IsGPR ? 
SystemZ::STG3
:
SystemZ::STD2
;
1184
5
      return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1185
5
                     get(StoreOpcode))
1186
5
          .add(MI.getOperand(1))
1187
5
          .addFrameIndex(FrameIndex)
1188
5
          .addImm(0)
1189
5
          .addReg(0);
1190
5
    }
1191
4
    // If we're spilling the source of an LDGR or LGDR, load the
1192
4
    // destination register instead.
1193
4
    if (OpNum == 1) {
1194
4
      unsigned LoadOpcode = Op0IsGPR ? 
SystemZ::LG2
:
SystemZ::LD2
;
1195
4
      return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1196
4
                     get(LoadOpcode))
1197
4
        .add(MI.getOperand(0))
1198
4
        .addFrameIndex(FrameIndex)
1199
4
        .addImm(0)
1200
4
        .addReg(0);
1201
4
    }
1202
1.21k
  }
1203
1.21k
1204
1.21k
  // Look for cases where the source of a simple store or the destination
1205
1.21k
  // of a simple load is being spilled.  Try to use MVC instead.
1206
1.21k
  //
1207
1.21k
  // Although MVC is in practice a fast choice in these cases, it is still
1208
1.21k
  // logically a bytewise copy.  This means that we cannot use it if the
1209
1.21k
  // load or store is volatile.  We also wouldn't be able to use MVC if
1210
1.21k
  // the two memories partially overlap, but that case cannot occur here,
1211
1.21k
  // because we know that one of the memories is a full frame index.
1212
1.21k
  //
1213
1.21k
  // For performance reasons, we also want to avoid using MVC if the addresses
1214
1.21k
  // might be equal.  We don't worry about that case here, because spill slot
1215
1.21k
  // coloring happens later, and because we have special code to remove
1216
1.21k
  // MVCs that turn out to be redundant.
1217
1.21k
  if (OpNum == 0 && 
MI.hasOneMemOperand()593
) {
1218
510
    MachineMemOperand *MMO = *MI.memoperands_begin();
1219
510
    if (MMO->getSize() == Size && 
!MMO->isVolatile()509
&&
!MMO->isAtomic()255
) {
1220
255
      // Handle conversion of loads.
1221
255
      if (isSimpleBD12Move(&MI, SystemZII::SimpleBDXLoad)) {
1222
168
        return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1223
168
                       get(SystemZ::MVC))
1224
168
            .addFrameIndex(FrameIndex)
1225
168
            .addImm(0)
1226
168
            .addImm(Size)
1227
168
            .add(MI.getOperand(1))
1228
168
            .addImm(MI.getOperand(2).getImm())
1229
168
            .addMemOperand(MMO);
1230
168
      }
1231
87
      // Handle conversion of stores.
1232
87
      if (isSimpleBD12Move(&MI, SystemZII::SimpleBDXStore)) {
1233
11
        return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1234
11
                       get(SystemZ::MVC))
1235
11
            .add(MI.getOperand(1))
1236
11
            .addImm(MI.getOperand(2).getImm())
1237
11
            .addImm(Size)
1238
11
            .addFrameIndex(FrameIndex)
1239
11
            .addImm(0)
1240
11
            .addMemOperand(MMO);
1241
11
      }
1242
1.03k
    }
1243
510
  }
1244
1.03k
1245
1.03k
  // If the spilled operand is the final one or the instruction is
1246
1.03k
  // commutable, try to change <INSN>R into <INSN>.
1247
1.03k
  unsigned NumOps = MI.getNumExplicitOperands();
1248
1.03k
  int MemOpcode = SystemZ::getMemOpcode(Opcode);
1249
1.03k
1250
1.03k
  // See if this is a 3-address instruction that is convertible to 2-address
1251
1.03k
  // and suitable for folding below.  Only try this with virtual registers
1252
1.03k
  // and a provided VRM (during regalloc).
1253
1.03k
  bool NeedsCommute = false;
1254
1.03k
  if (SystemZ::getTwoOperandOpcode(Opcode) != -1 && 
MemOpcode != -124
) {
1255
24
    if (VRM == nullptr)
1256
0
      MemOpcode = -1;
1257
24
    else {
1258
24
      assert(NumOps == 3 && "Expected two source registers.");
1259
24
      Register DstReg = MI.getOperand(0).getReg();
1260
24
      Register DstPhys =
1261
24
        (TRI->isVirtualRegister(DstReg) ? VRM->getPhys(DstReg) : 
DstReg0
);
1262
24
      Register SrcReg = (OpNum == 2 ? 
MI.getOperand(1).getReg()22
1263
24
                                    : 
((2
OpNum == 12
&&
MI.isCommutable()1
)
1264
2
                                           ? 
MI.getOperand(2).getReg()1
1265
2
                                         : 
Register()1
));
1266
24
      if (DstPhys && 
!SystemZ::GRH32BitRegClass.contains(DstPhys)23
&&
SrcReg23
&&
1267
24
          
TRI->isVirtualRegister(SrcReg)23
&&
DstPhys == VRM->getPhys(SrcReg)23
)
1268
21
        NeedsCommute = (OpNum == 1);
1269
3
      else
1270
3
        MemOpcode = -1;
1271
24
    }
1272
24
  }
1273
1.03k
1274
1.03k
  if (MemOpcode >= 0) {
1275
234
    if ((OpNum == NumOps - 1) || 
NeedsCommute19
) {
1276
215
      const MCInstrDesc &MemDesc = get(MemOpcode);
1277
215
      uint64_t AccessBytes = SystemZII::getAccessSize(MemDesc.TSFlags);
1278
215
      assert(AccessBytes != 0 && "Size of access should be known");
1279
215
      assert(AccessBytes <= Size && "Access outside the frame index");
1280
215
      uint64_t Offset = Size - AccessBytes;
1281
215
      MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
1282
215
                                        MI.getDebugLoc(), get(MemOpcode));
1283
215
      MIB.add(MI.getOperand(0));
1284
215
      if (NeedsCommute)
1285
0
        MIB.add(MI.getOperand(2));
1286
215
      else
1287
382
        
for (unsigned I = 1; 215
I < OpNum;
++I167
)
1288
167
          MIB.add(MI.getOperand(I));
1289
215
      MIB.addFrameIndex(FrameIndex).addImm(Offset);
1290
215
      if (MemDesc.TSFlags & SystemZII::HasIndex)
1291
215
        MIB.addReg(0);
1292
215
      transferDeadCC(&MI, MIB);
1293
215
      return MIB;
1294
215
    }
1295
824
  }
1296
824
1297
824
  return nullptr;
1298
824
}
1299
1300
MachineInstr *SystemZInstrInfo::foldMemoryOperandImpl(
1301
    MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
1302
    MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
1303
0
    LiveIntervals *LIS) const {
1304
0
  return nullptr;
1305
0
}
1306
1307
21.8k
bool SystemZInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
1308
21.8k
  switch (MI.getOpcode()) {
1309
21.8k
  case SystemZ::L128:
1310
1
    splitMove(MI, SystemZ::LG);
1311
1
    return true;
1312
21.8k
1313
21.8k
  case SystemZ::ST128:
1314
1
    splitMove(MI, SystemZ::STG);
1315
1
    return true;
1316
21.8k
1317
21.8k
  case SystemZ::LX:
1318
200
    splitMove(MI, SystemZ::LD);
1319
200
    return true;
1320
21.8k
1321
21.8k
  case SystemZ::STX:
1322
284
    splitMove(MI, SystemZ::STD);
1323
284
    return true;
1324
21.8k
1325
21.8k
  case SystemZ::LBMux:
1326
21
    expandRXYPseudo(MI, SystemZ::LB, SystemZ::LBH);
1327
21
    return true;
1328
21.8k
1329
21.8k
  case SystemZ::LHMux:
1330
19
    expandRXYPseudo(MI, SystemZ::LH, SystemZ::LHH);
1331
19
    return true;
1332
21.8k
1333
21.8k
  case SystemZ::LLCRMux:
1334
63
    expandZExtPseudo(MI, SystemZ::LLCR, 8);
1335
63
    return true;
1336
21.8k
1337
21.8k
  case SystemZ::LLHRMux:
1338
60
    expandZExtPseudo(MI, SystemZ::LLHR, 16);
1339
60
    return true;
1340
21.8k
1341
21.8k
  case SystemZ::LLCMux:
1342
18
    expandRXYPseudo(MI, SystemZ::LLC, SystemZ::LLCH);
1343
18
    return true;
1344
21.8k
1345
21.8k
  case SystemZ::LLHMux:
1346
14
    expandRXYPseudo(MI, SystemZ::LLH, SystemZ::LLHH);
1347
14
    return true;
1348
21.8k
1349
21.8k
  case SystemZ::LMux:
1350
193
    expandRXYPseudo(MI, SystemZ::L, SystemZ::LFH);
1351
193
    return true;
1352
21.8k
1353
21.8k
  case SystemZ::LOCMux:
1354
16
    expandLOCPseudo(MI, SystemZ::LOC, SystemZ::LOCFH);
1355
16
    return true;
1356
21.8k
1357
21.8k
  case SystemZ::LOCHIMux:
1358
473
    expandLOCPseudo(MI, SystemZ::LOCHI, SystemZ::LOCHHI);
1359
473
    return true;
1360
21.8k
1361
21.8k
  case SystemZ::LOCRMux:
1362
17
    expandLOCRPseudo(MI, SystemZ::LOCR, SystemZ::LOCFHR);
1363
17
    return true;
1364
21.8k
1365
21.8k
  case SystemZ::SELRMux:
1366
21
    expandSELRPseudo(MI, SystemZ::SELR, SystemZ::SELFHR,
1367
21
                         SystemZ::LOCRMux);
1368
21
    return true;
1369
21.8k
1370
21.8k
  case SystemZ::STCMux:
1371
35
    expandRXYPseudo(MI, SystemZ::STC, SystemZ::STCH);
1372
35
    return true;
1373
21.8k
1374
21.8k
  case SystemZ::STHMux:
1375
18
    expandRXYPseudo(MI, SystemZ::STH, SystemZ::STHH);
1376
18
    return true;
1377
21.8k
1378
21.8k
  case SystemZ::STMux:
1379
702
    expandRXYPseudo(MI, SystemZ::ST, SystemZ::STFH);
1380
702
    return true;
1381
21.8k
1382
21.8k
  case SystemZ::STOCMux:
1383
14
    expandLOCPseudo(MI, SystemZ::STOC, SystemZ::STOCFH);
1384
14
    return true;
1385
21.8k
1386
21.8k
  case SystemZ::LHIMux:
1387
656
    expandRIPseudo(MI, SystemZ::LHI, SystemZ::IIHF, true);
1388
656
    return true;
1389
21.8k
1390
21.8k
  case SystemZ::IIFMux:
1391
28
    expandRIPseudo(MI, SystemZ::IILF, SystemZ::IIHF, false);
1392
28
    return true;
1393
21.8k
1394
21.8k
  case SystemZ::IILMux:
1395
2
    expandRIPseudo(MI, SystemZ::IILL, SystemZ::IIHL, false);
1396
2
    return true;
1397
21.8k
1398
21.8k
  case SystemZ::IIHMux:
1399
2
    expandRIPseudo(MI, SystemZ::IILH, SystemZ::IIHH, false);
1400
2
    return true;
1401
21.8k
1402
21.8k
  case SystemZ::NIFMux:
1403
22
    expandRIPseudo(MI, SystemZ::NILF, SystemZ::NIHF, false);
1404
22
    return true;
1405
21.8k
1406
21.8k
  case SystemZ::NILMux:
1407
16
    expandRIPseudo(MI, SystemZ::NILL, SystemZ::NIHL, false);
1408
16
    return true;
1409
21.8k
1410
21.8k
  case SystemZ::NIHMux:
1411
5
    expandRIPseudo(MI, SystemZ::NILH, SystemZ::NIHH, false);
1412
5
    return true;
1413
21.8k
1414
21.8k
  case SystemZ::OIFMux:
1415
2
    expandRIPseudo(MI, SystemZ::OILF, SystemZ::OIHF, false);
1416
2
    return true;
1417
21.8k
1418
21.8k
  case SystemZ::OILMux:
1419
4
    expandRIPseudo(MI, SystemZ::OILL, SystemZ::OIHL, false);
1420
4
    return true;
1421
21.8k
1422
21.8k
  case SystemZ::OIHMux:
1423
4
    expandRIPseudo(MI, SystemZ::OILH, SystemZ::OIHH, false);
1424
4
    return true;
1425
21.8k
1426
21.8k
  case SystemZ::XIFMux:
1427
10
    expandRIPseudo(MI, SystemZ::XILF, SystemZ::XIHF, false);
1428
10
    return true;
1429
21.8k
1430
21.8k
  case SystemZ::TMLMux:
1431
38
    expandRIPseudo(MI, SystemZ::TMLL, SystemZ::TMHL, false);
1432
38
    return true;
1433
21.8k
1434
21.8k
  case SystemZ::TMHMux:
1435
6
    expandRIPseudo(MI, SystemZ::TMLH, SystemZ::TMHH, false);
1436
6
    return true;
1437
21.8k
1438
21.8k
  case SystemZ::AHIMux:
1439
4
    expandRIPseudo(MI, SystemZ::AHI, SystemZ::AIH, false);
1440
4
    return true;
1441
21.8k
1442
21.8k
  case SystemZ::AHIMuxK:
1443
55
    expandRIEPseudo(MI, SystemZ::AHI, SystemZ::AHIK, SystemZ::AIH);
1444
55
    return true;
1445
21.8k
1446
21.8k
  case SystemZ::AFIMux:
1447
98
    expandRIPseudo(MI, SystemZ::AFI, SystemZ::AIH, false);
1448
98
    return true;
1449
21.8k
1450
21.8k
  case SystemZ::CHIMux:
1451
150
    expandRIPseudo(MI, SystemZ::CHI, SystemZ::CIH, false);
1452
150
    return true;
1453
21.8k
1454
21.8k
  case SystemZ::CFIMux:
1455
6
    expandRIPseudo(MI, SystemZ::CFI, SystemZ::CIH, false);
1456
6
    return true;
1457
21.8k
1458
21.8k
  case SystemZ::CLFIMux:
1459
107
    expandRIPseudo(MI, SystemZ::CLFI, SystemZ::CLIH, false);
1460
107
    return true;
1461
21.8k
1462
21.8k
  case SystemZ::CMux:
1463
2
    expandRXYPseudo(MI, SystemZ::C, SystemZ::CHF);
1464
2
    return true;
1465
21.8k
1466
21.8k
  case SystemZ::CLMux:
1467
5
    expandRXYPseudo(MI, SystemZ::CL, SystemZ::CLHF);
1468
5
    return true;
1469
21.8k
1470
21.8k
  case SystemZ::RISBMux: {
1471
56
    bool DestIsHigh = isHighReg(MI.getOperand(0).getReg());
1472
56
    bool SrcIsHigh = isHighReg(MI.getOperand(2).getReg());
1473
56
    if (SrcIsHigh == DestIsHigh)
1474
50
      MI.setDesc(get(DestIsHigh ? 
SystemZ::RISBHH3
:
SystemZ::RISBLL47
));
1475
6
    else {
1476
6
      MI.setDesc(get(DestIsHigh ? 
SystemZ::RISBHL3
:
SystemZ::RISBLH3
));
1477
6
      MI.getOperand(5).setImm(MI.getOperand(5).getImm() ^ 32);
1478
6
    }
1479
56
    return true;
1480
21.8k
  }
1481
21.8k
1482
21.8k
  case SystemZ::ADJDYNALLOC:
1483
46
    splitAdjDynAlloc(MI);
1484
46
    return true;
1485
21.8k
1486
21.8k
  case TargetOpcode::LOAD_STACK_GUARD:
1487
2
    expandLoadStackGuard(&MI);
1488
2
    return true;
1489
21.8k
1490
21.8k
  default:
1491
18.3k
    return false;
1492
21.8k
  }
1493
21.8k
}
1494
1495
65.5k
unsigned SystemZInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
1496
65.5k
  if (MI.isInlineAsm()) {
1497
415
    const MachineFunction *MF = MI.getParent()->getParent();
1498
415
    const char *AsmStr = MI.getOperand(0).getSymbolName();
1499
415
    return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
1500
415
  }
1501
65.0k
  return MI.getDesc().getSize();
1502
65.0k
}
1503
1504
SystemZII::Branch
1505
53.3k
SystemZInstrInfo::getBranchInfo(const MachineInstr &MI) const {
1506
53.3k
  switch (MI.getOpcode()) {
1507
53.3k
  case SystemZ::BR:
1508
7.33k
  case SystemZ::BI:
1509
7.33k
  case SystemZ::J:
1510
7.33k
  case SystemZ::JG:
1511
7.33k
    return SystemZII::Branch(SystemZII::BranchNormal, SystemZ::CCMASK_ANY,
1512
7.33k
                             SystemZ::CCMASK_ANY, &MI.getOperand(0));
1513
7.33k
1514
45.3k
  case SystemZ::BRC:
1515
45.3k
  case SystemZ::BRCL:
1516
45.3k
    return SystemZII::Branch(SystemZII::BranchNormal, MI.getOperand(0).getImm(),
1517
45.3k
                             MI.getOperand(1).getImm(), &MI.getOperand(2));
1518
45.3k
1519
45.3k
  case SystemZ::BRCT:
1520
27
  case SystemZ::BRCTH:
1521
27
    return SystemZII::Branch(SystemZII::BranchCT, SystemZ::CCMASK_ICMP,
1522
27
                             SystemZ::CCMASK_CMP_NE, &MI.getOperand(2));
1523
27
1524
27
  case SystemZ::BRCTG:
1525
12
    return SystemZII::Branch(SystemZII::BranchCTG, SystemZ::CCMASK_ICMP,
1526
12
                             SystemZ::CCMASK_CMP_NE, &MI.getOperand(2));
1527
27
1528
423
  case SystemZ::CIJ:
1529
423
  case SystemZ::CRJ:
1530
423
    return SystemZII::Branch(SystemZII::BranchC, SystemZ::CCMASK_ICMP,
1531
423
                             MI.getOperand(2).getImm(), &MI.getOperand(3));
1532
423
1533
423
  case SystemZ::CLIJ:
1534
89
  case SystemZ::CLRJ:
1535
89
    return SystemZII::Branch(SystemZII::BranchCL, SystemZ::CCMASK_ICMP,
1536
89
                             MI.getOperand(2).getImm(), &MI.getOperand(3));
1537
89
1538
95
  case SystemZ::CGIJ:
1539
95
  case SystemZ::CGRJ:
1540
95
    return SystemZII::Branch(SystemZII::BranchCG, SystemZ::CCMASK_ICMP,
1541
95
                             MI.getOperand(2).getImm(), &MI.getOperand(3));
1542
95
1543
95
  case SystemZ::CLGIJ:
1544
18
  case SystemZ::CLGRJ:
1545
18
    return SystemZII::Branch(SystemZII::BranchCLG, SystemZ::CCMASK_ICMP,
1546
18
                             MI.getOperand(2).getImm(), &MI.getOperand(3));
1547
18
1548
18
  default:
1549
0
    llvm_unreachable("Unrecognized branch opcode");
1550
53.3k
  }
1551
53.3k
}
1552
1553
void SystemZInstrInfo::getLoadStoreOpcodes(const TargetRegisterClass *RC,
1554
                                           unsigned &LoadOpcode,
1555
2.79k
                                           unsigned &StoreOpcode) const {
1556
2.79k
  if (RC == &SystemZ::GR32BitRegClass || 
RC == &SystemZ::ADDR32BitRegClass2.56k
) {
1557
228
    LoadOpcode = SystemZ::L;
1558
228
    StoreOpcode = SystemZ::ST;
1559
2.56k
  } else if (RC == &SystemZ::GRH32BitRegClass) {
1560
0
    LoadOpcode = SystemZ::LFH;
1561
0
    StoreOpcode = SystemZ::STFH;
1562
2.56k
  } else if (RC == &SystemZ::GRX32BitRegClass) {
1563
27
    LoadOpcode = SystemZ::LMux;
1564
27
    StoreOpcode = SystemZ::STMux;
1565
2.53k
  } else if (RC == &SystemZ::GR64BitRegClass ||
1566
2.53k
             
RC == &SystemZ::ADDR64BitRegClass2.34k
) {
1567
541
    LoadOpcode = SystemZ::LG;
1568
541
    StoreOpcode = SystemZ::STG;
1569
1.99k
  } else if (RC == &SystemZ::GR128BitRegClass ||
1570
1.99k
             
RC == &SystemZ::ADDR128BitRegClass1.98k
) {
1571
10
    LoadOpcode = SystemZ::L128;
1572
10
    StoreOpcode = SystemZ::ST128;
1573
1.98k
  } else if (RC == &SystemZ::FP32BitRegClass) {
1574
27
    LoadOpcode = SystemZ::LE;
1575
27
    StoreOpcode = SystemZ::STE;
1576
1.95k
  } else if (RC == &SystemZ::FP64BitRegClass) {
1577
1.56k
    LoadOpcode = SystemZ::LD;
1578
1.56k
    StoreOpcode = SystemZ::STD;
1579
1.56k
  } else 
if (398
RC == &SystemZ::FP128BitRegClass398
) {
1580
2
    LoadOpcode = SystemZ::LX;
1581
2
    StoreOpcode = SystemZ::STX;
1582
396
  } else if (RC == &SystemZ::VR32BitRegClass) {
1583
54
    LoadOpcode = SystemZ::VL32;
1584
54
    StoreOpcode = SystemZ::VST32;
1585
342
  } else if (RC == &SystemZ::VR64BitRegClass) {
1586
54
    LoadOpcode = SystemZ::VL64;
1587
54
    StoreOpcode = SystemZ::VST64;
1588
288
  } else if (RC == &SystemZ::VF128BitRegClass ||
1589
288
             RC == &SystemZ::VR128BitRegClass) {
1590
288
    LoadOpcode = SystemZ::VL;
1591
288
    StoreOpcode = SystemZ::VST;
1592
288
  } else
1593
288
    
llvm_unreachable0
("Unsupported regclass to load or store");
1594
2.79k
}
1595
1596
unsigned SystemZInstrInfo::getOpcodeForOffset(unsigned Opcode,
1597
8.14k
                                              int64_t Offset) const {
1598
8.14k
  const MCInstrDesc &MCID = get(Opcode);
1599
8.14k
  int64_t Offset2 = (MCID.TSFlags & SystemZII::Is128Bit ? 
Offset + 8106
:
Offset8.04k
);
1600
8.14k
  if (isUInt<12>(Offset) && 
isUInt<12>(Offset2)7.55k
) {
1601
7.55k
    // Get the instruction to use for unsigned 12-bit displacements.
1602
7.55k
    int Disp12Opcode = SystemZ::getDisp12Opcode(Opcode);
1603
7.55k
    if (Disp12Opcode >= 0)
1604
16
      return Disp12Opcode;
1605
7.53k
1606
7.53k
    // All address-related instructions can use unsigned 12-bit
1607
7.53k
    // displacements.
1608
7.53k
    return Opcode;
1609
7.53k
  }
1610
595
  if (isInt<20>(Offset) && 
isInt<20>(Offset2)490
) {
1611
490
    // Get the instruction to use for signed 20-bit displacements.
1612
490
    int Disp20Opcode = SystemZ::getDisp20Opcode(Opcode);
1613
490
    if (Disp20Opcode >= 0)
1614
155
      return Disp20Opcode;
1615
335
1616
335
    // Check whether Opcode allows signed 20-bit displacements.
1617
335
    if (MCID.TSFlags & SystemZII::Has20BitOffset)
1618
127
      return Opcode;
1619
313
  }
1620
313
  return 0;
1621
313
}
1622
1623
127
unsigned SystemZInstrInfo::getLoadAndTest(unsigned Opcode) const {
1624
127
  switch (Opcode) {
1625
127
  
case SystemZ::L: return SystemZ::LT6
;
1626
127
  
case SystemZ::LY: return SystemZ::LT1
;
1627
127
  
case SystemZ::LG: return SystemZ::LTG3
;
1628
127
  
case SystemZ::LGF: return SystemZ::LTGF2
;
1629
127
  
case SystemZ::LR: return SystemZ::LTR2
;
1630
127
  
case SystemZ::LGFR: return SystemZ::LTGFR4
;
1631
127
  
case SystemZ::LGR: return SystemZ::LTGR6
;
1632
127
  
case SystemZ::LER: return SystemZ::LTEBR3
;
1633
127
  
case SystemZ::LDR: return SystemZ::LTDBR2
;
1634
127
  
case SystemZ::LXR: return SystemZ::LTXBR1
;
1635
127
  
case SystemZ::LCDFR: return SystemZ::LCDBR0
;
1636
127
  
case SystemZ::LPDFR: return SystemZ::LPDBR4
;
1637
127
  
case SystemZ::LNDFR: return SystemZ::LNDBR0
;
1638
127
  
case SystemZ::LCDFR_32: return SystemZ::LCEBR2
;
1639
127
  
case SystemZ::LPDFR_32: return SystemZ::LPEBR6
;
1640
127
  
case SystemZ::LNDFR_32: return SystemZ::LNEBR2
;
1641
127
  // On zEC12 we prefer to use RISBGN.  But if there is a chance to
1642
127
  // actually use the condition code, we may turn it back into RISGB.
1643
127
  // Note that RISBG is not really a "load-and-test" instruction,
1644
127
  // but sets the same condition code values, so is OK to use here.
1645
127
  
case SystemZ::RISBGN: return SystemZ::RISBG1
;
1646
127
  
default: return 082
;
1647
127
  }
1648
127
}
1649
1650
// Return true if Mask matches the regexp 0*1+0*, given that zero masks
1651
// have already been filtered out.  Store the first set bit in LSB and
1652
// the number of set bits in Length if so.
1653
6.52k
static bool isStringOfOnes(uint64_t Mask, unsigned &LSB, unsigned &Length) {
1654
6.52k
  unsigned First = findFirstSet(Mask);
1655
6.52k
  uint64_t Top = (Mask >> First) + 1;
1656
6.52k
  if ((Top & -Top) == Top) {
1657
5.03k
    LSB = First;
1658
5.03k
    Length = findFirstSet(Top);
1659
5.03k
    return true;
1660
5.03k
  }
1661
1.48k
  return false;
1662
1.48k
}
1663
1664
bool SystemZInstrInfo::isRxSBGMask(uint64_t Mask, unsigned BitSize,
1665
5.70k
                                   unsigned &Start, unsigned &End) const {
1666
5.70k
  // Reject trivial all-zero masks.
1667
5.70k
  Mask &= allOnes(BitSize);
1668
5.70k
  if (Mask == 0)
1669
0
    return false;
1670
5.70k
1671
5.70k
  // Handle the 1+0+ or 0+1+0* cases.  Start then specifies the index of
1672
5.70k
  // the msb and End specifies the index of the lsb.
1673
5.70k
  unsigned LSB, Length;
1674
5.70k
  if (isStringOfOnes(Mask, LSB, Length)) {
1675
4.89k
    Start = 63 - (LSB + Length - 1);
1676
4.89k
    End = 63 - LSB;
1677
4.89k
    return true;
1678
4.89k
  }
1679
812
1680
812
  // Handle the wrap-around 1+0+1+ cases.  Start then specifies the msb
1681
812
  // of the low 1s and End specifies the lsb of the high 1s.
1682
812
  if (isStringOfOnes(Mask ^ allOnes(BitSize), LSB, Length)) {
1683
142
    assert(LSB > 0 && "Bottom bit must be set");
1684
142
    assert(LSB + Length < BitSize && "Top bit must be set");
1685
142
    Start = 63 - (LSB - 1);
1686
142
    End = 63 - (LSB + Length);
1687
142
    return true;
1688
142
  }
1689
670
1690
670
  return false;
1691
670
}
1692
1693
unsigned SystemZInstrInfo::getFusedCompare(unsigned Opcode,
1694
                                           SystemZII::FusedCompareType Type,
1695
1.17k
                                           const MachineInstr *MI) const {
1696
1.17k
  switch (Opcode) {
1697
1.17k
  case SystemZ::CHI:
1698
217
  case SystemZ::CGHI:
1699
217
    if (!(MI && isInt<8>(MI->getOperand(1).getImm())))
1700
26
      return 0;
1701
191
    break;
1702
191
  case SystemZ::CLFI:
1703
133
  case SystemZ::CLGFI:
1704
133
    if (!(MI && isUInt<8>(MI->getOperand(1).getImm())))
1705
110
      return 0;
1706
23
    break;
1707
26
  case SystemZ::CL:
1708
26
  case SystemZ::CLG:
1709
26
    if (!STI.hasMiscellaneousExtensions())
1710
22
      return 0;
1711
4
    if (!(MI && MI->getOperand(3).getReg() == 0))
1712
2
      return 0;
1713
2
    break;
1714
1.01k
  }
1715
1.01k
  switch (Type) {
1716
1.01k
  case SystemZII::CompareAndBranch:
1717
542
    switch (Opcode) {
1718
542
    case SystemZ::CR:
1719
72
      return SystemZ::CRJ;
1720
542
    case SystemZ::CGR:
1721
25
      return SystemZ::CGRJ;
1722
542
    case SystemZ::CHI:
1723
112
      return SystemZ::CIJ;
1724
542
    case SystemZ::CGHI:
1725
38
      return SystemZ::CGIJ;
1726
542
    case SystemZ::CLR:
1727
33
      return SystemZ::CLRJ;
1728
542
    case SystemZ::CLGR:
1729
9
      return SystemZ::CLGRJ;
1730
542
    case SystemZ::CLFI:
1731
12
      return SystemZ::CLIJ;
1732
542
    case SystemZ::CLGFI:
1733
3
      return SystemZ::CLGIJ;
1734
542
    default:
1735
238
      return 0;
1736
0
    }
1737
441
  case SystemZII::CompareAndReturn:
1738
441
    switch (Opcode) {
1739
441
    case SystemZ::CR:
1740
1
      return SystemZ::CRBReturn;
1741
441
    case SystemZ::CGR:
1742
5
      return SystemZ::CGRBReturn;
1743
441
    case SystemZ::CHI:
1744
25
      return SystemZ::CIBReturn;
1745
441
    case SystemZ::CGHI:
1746
7
      return SystemZ::CGIBReturn;
1747
441
    case SystemZ::CLR:
1748
7
      return SystemZ::CLRBReturn;
1749
441
    case SystemZ::CLGR:
1750
9
      return SystemZ::CLGRBReturn;
1751
441
    case SystemZ::CLFI:
1752
3
      return SystemZ::CLIBReturn;
1753
441
    case SystemZ::CLGFI:
1754
1
      return SystemZ::CLGIBReturn;
1755
441
    default:
1756
383
      return 0;
1757
0
    }
1758
23
  case SystemZII::CompareAndSibcall:
1759
23
    switch (Opcode) {
1760
23
    case SystemZ::CR:
1761
7
      return SystemZ::CRBCall;
1762
23
    case SystemZ::CGR:
1763
1
      return SystemZ::CGRBCall;
1764
23
    case SystemZ::CHI:
1765
6
      return SystemZ::CIBCall;
1766
23
    case SystemZ::CGHI:
1767
1
      return SystemZ::CGIBCall;
1768
23
    case SystemZ::CLR:
1769
1
      return SystemZ::CLRBCall;
1770
23
    case SystemZ::CLGR:
1771
1
      return SystemZ::CLGRBCall;
1772
23
    case SystemZ::CLFI:
1773
1
      return SystemZ::CLIBCall;
1774
23
    case SystemZ::CLGFI:
1775
1
      return SystemZ::CLGIBCall;
1776
23
    default:
1777
4
      return 0;
1778
0
    }
1779
11
  case SystemZII::CompareAndTrap:
1780
11
    switch (Opcode) {
1781
11
    case SystemZ::CR:
1782
1
      return SystemZ::CRT;
1783
11
    case SystemZ::CGR:
1784
1
      return SystemZ::CGRT;
1785
11
    case SystemZ::CHI:
1786
1
      return SystemZ::CIT;
1787
11
    case SystemZ::CGHI:
1788
1
      return SystemZ::CGIT;
1789
11
    case SystemZ::CLR:
1790
1
      return SystemZ::CLRT;
1791
11
    case SystemZ::CLGR:
1792
1
      return SystemZ::CLGRT;
1793
11
    case SystemZ::CLFI:
1794
1
      return SystemZ::CLFIT;
1795
11
    case SystemZ::CLGFI:
1796
1
      return SystemZ::CLGIT;
1797
11
    case SystemZ::CL:
1798
1
      return SystemZ::CLT;
1799
11
    case SystemZ::CLG:
1800
1
      return SystemZ::CLGT;
1801
11
    default:
1802
1
      return 0;
1803
0
    }
1804
0
  }
1805
0
  return 0;
1806
0
}
1807
1808
141
unsigned SystemZInstrInfo::getLoadAndTrap(unsigned Opcode) const {
1809
141
  if (!STI.hasLoadAndTrap())
1810
87
    return 0;
1811
54
  switch (Opcode) {
1812
54
  case SystemZ::L:
1813
8
  case SystemZ::LY:
1814
8
    return SystemZ::LAT;
1815
8
  case SystemZ::LG:
1816
5
    return SystemZ::LGAT;
1817
8
  case SystemZ::LFH:
1818
4
    return SystemZ::LFHAT;
1819
8
  case SystemZ::LLGF:
1820
5
    return SystemZ::LLGFAT;
1821
8
  case SystemZ::LLGT:
1822
4
    return SystemZ::LLGTAT;
1823
28
  }
1824
28
  return 0;
1825
28
}
1826
1827
void SystemZInstrInfo::loadImmediate(MachineBasicBlock &MBB,
1828
                                     MachineBasicBlock::iterator MBBI,
1829
78
                                     unsigned Reg, uint64_t Value) const {
1830
78
  DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : 
DebugLoc()0
;
1831
78
  unsigned Opcode;
1832
78
  if (isInt<16>(Value))
1833
20
    Opcode = SystemZ::LGHI;
1834
58
  else if (SystemZ::isImmLL(Value))
1835
0
    Opcode = SystemZ::LLILL;
1836
58
  else if (SystemZ::isImmLH(Value)) {
1837
58
    Opcode = SystemZ::LLILH;
1838
58
    Value >>= 16;
1839
58
  } else {
1840
0
    assert(isInt<32>(Value) && "Huge values not handled yet");
1841
0
    Opcode = SystemZ::LGFI;
1842
0
  }
1843
78
  BuildMI(MBB, MBBI, DL, get(Opcode), Reg).addImm(Value);
1844
78
}
1845
1846
bool SystemZInstrInfo::
1847
areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
1848
                                const MachineInstr &MIb,
1849
7.23k
                                AliasAnalysis *AA) const {
1850
7.23k
1851
7.23k
  if (!MIa.hasOneMemOperand() || 
!MIb.hasOneMemOperand()7.19k
)
1852
272
    return false;
1853
6.96k
1854
6.96k
  // If mem-operands show that the same address Value is used by both
1855
6.96k
  // instructions, check for non-overlapping offsets and widths. Not
1856
6.96k
  // sure if a register based analysis would be an improvement...
1857
6.96k
1858
6.96k
  MachineMemOperand *MMOa = *MIa.memoperands_begin();
1859
6.96k
  MachineMemOperand *MMOb = *MIb.memoperands_begin();
1860
6.96k
  const Value *VALa = MMOa->getValue();
1861
6.96k
  const Value *VALb = MMOb->getValue();
1862
6.96k
  bool SameVal = (VALa && 
VALb5.68k
&&
(VALa == VALb)5.03k
);
1863
6.96k
  if (!SameVal) {
1864
5.73k
    const PseudoSourceValue *PSVa = MMOa->getPseudoValue();
1865
5.73k
    const PseudoSourceValue *PSVb = MMOb->getPseudoValue();
1866
5.73k
    if (PSVa && 
PSVb442
&&
(PSVa == PSVb)89
)
1867
42
      SameVal = true;
1868
5.73k
  }
1869
6.96k
  if (SameVal) {
1870
1.27k
    int OffsetA = MMOa->getOffset(), OffsetB = MMOb->getOffset();
1871
1.27k
    int WidthA = MMOa->getSize(), WidthB = MMOb->getSize();
1872
1.27k
    int LowOffset = OffsetA < OffsetB ? 
OffsetA106
:
OffsetB1.16k
;
1873
1.27k
    int HighOffset = OffsetA < OffsetB ? 
OffsetB106
:
OffsetA1.16k
;
1874
1.27k
    int LowWidth = (LowOffset == OffsetA) ? 
WidthA788
:
WidthB486
;
1875
1.27k
    if (LowOffset + LowWidth <= HighOffset)
1876
590
      return true;
1877
6.37k
  }
1878
6.37k
1879
6.37k
  return false;
1880
6.37k
}