Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp
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Source (jump to first uncovered line)
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//===-- SystemZRegisterInfo.cpp - SystemZ register information ------------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
9
#include "SystemZRegisterInfo.h"
10
#include "SystemZInstrInfo.h"
11
#include "SystemZSubtarget.h"
12
#include "llvm/CodeGen/LiveIntervals.h"
13
#include "llvm/ADT/SmallSet.h"
14
#include "llvm/CodeGen/MachineInstrBuilder.h"
15
#include "llvm/CodeGen/MachineRegisterInfo.h"
16
#include "llvm/CodeGen/TargetFrameLowering.h"
17
#include "llvm/CodeGen/VirtRegMap.h"
18
19
using namespace llvm;
20
21
#define GET_REGINFO_TARGET_DESC
22
#include "SystemZGenRegisterInfo.inc"
23
24
SystemZRegisterInfo::SystemZRegisterInfo()
25
1.09k
    : SystemZGenRegisterInfo(SystemZ::R14D) {}
26
27
// Given that MO is a GRX32 operand, return either GR32 or GRH32 if MO
28
// somehow belongs in it. Otherwise, return GRX32.
29
static const TargetRegisterClass *getRC32(MachineOperand &MO,
30
                                          const VirtRegMap *VRM,
31
57
                                          const MachineRegisterInfo *MRI) {
32
57
  const TargetRegisterClass *RC = MRI->getRegClass(MO.getReg());
33
57
34
57
  if (SystemZ::GR32BitRegClass.hasSubClassEq(RC) ||
35
57
      
MO.getSubReg() == SystemZ::subreg_l3236
||
36
57
      
MO.getSubReg() == SystemZ::subreg_hl3233
)
37
25
    return &SystemZ::GR32BitRegClass;
38
32
  if (SystemZ::GRH32BitRegClass.hasSubClassEq(RC) ||
39
32
      MO.getSubReg() == SystemZ::subreg_h32 ||
40
32
      MO.getSubReg() == SystemZ::subreg_hh32)
41
0
    return &SystemZ::GRH32BitRegClass;
42
32
43
32
  if (VRM && VRM->hasPhys(MO.getReg())) {
44
3
    unsigned PhysReg = VRM->getPhys(MO.getReg());
45
3
    if (SystemZ::GR32BitRegClass.contains(PhysReg))
46
3
      return &SystemZ::GR32BitRegClass;
47
0
    assert (SystemZ::GRH32BitRegClass.contains(PhysReg) &&
48
0
            "Phys reg not in GR32 or GRH32?");
49
0
    return &SystemZ::GRH32BitRegClass;
50
0
  }
51
29
52
29
  assert (RC == &SystemZ::GRX32BitRegClass);
53
29
  return RC;
54
29
}
55
56
// Pass the registers of RC as hints while making sure that if any of these
57
// registers are copy hints (and therefore already in Hints), hint them
58
// first.
59
static void addHints(ArrayRef<MCPhysReg> Order,
60
                     SmallVectorImpl<MCPhysReg> &Hints,
61
                     const TargetRegisterClass *RC,
62
28
                     const MachineRegisterInfo *MRI) {
63
28
  SmallSet<unsigned, 4> CopyHints;
64
28
  CopyHints.insert(Hints.begin(), Hints.end());
65
28
  Hints.clear();
66
28
  for (MCPhysReg Reg : Order)
67
840
    if (CopyHints.count(Reg) &&
68
840
        
RC->contains(Reg)14
&&
!MRI->isReserved(Reg)14
)
69
14
      Hints.push_back(Reg);
70
28
  for (MCPhysReg Reg : Order)
71
840
    if (!CopyHints.count(Reg) &&
72
840
        
RC->contains(Reg)826
&&
!MRI->isReserved(Reg)406
)
73
406
      Hints.push_back(Reg);
74
28
}
75
76
bool
77
SystemZRegisterInfo::getRegAllocationHints(unsigned VirtReg,
78
                                           ArrayRef<MCPhysReg> Order,
79
                                           SmallVectorImpl<MCPhysReg> &Hints,
80
                                           const MachineFunction &MF,
81
                                           const VirtRegMap *VRM,
82
47.3k
                                           const LiveRegMatrix *Matrix) const {
83
47.3k
  const MachineRegisterInfo *MRI = &MF.getRegInfo();
84
47.3k
  const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>();
85
47.3k
  const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
86
47.3k
87
47.3k
  bool BaseImplRetVal = TargetRegisterInfo::getRegAllocationHints(
88
47.3k
      VirtReg, Order, Hints, MF, VRM, Matrix);
89
47.3k
90
47.3k
  if (MRI->getRegClass(VirtReg) == &SystemZ::GRX32BitRegClass) {
91
1.91k
    SmallVector<unsigned, 8> Worklist;
92
1.91k
    SmallSet<unsigned, 4> DoneRegs;
93
1.91k
    Worklist.push_back(VirtReg);
94
3.80k
    while (Worklist.size()) {
95
1.91k
      unsigned Reg = Worklist.pop_back_val();
96
1.91k
      if (!DoneRegs.insert(Reg).second)
97
2
        continue;
98
1.91k
99
5.77k
      
for (auto &Use : MRI->reg_instructions(Reg))1.91k
{
100
5.77k
        // For LOCRMux, see if the other operand is already a high or low
101
5.77k
        // register, and in that case give the corresponding hints for
102
5.77k
        // VirtReg. LOCR instructions need both operands in either high or
103
5.77k
        // low parts. Same handling for SELRMux.
104
5.77k
        if (Use.getOpcode() == SystemZ::LOCRMux ||
105
5.77k
            
Use.getOpcode() == SystemZ::SELRMux5.77k
) {
106
22
          MachineOperand &TrueMO = Use.getOperand(1);
107
22
          MachineOperand &FalseMO = Use.getOperand(2);
108
22
          const TargetRegisterClass *RC =
109
22
            TRI->getCommonSubClass(getRC32(FalseMO, VRM, MRI),
110
22
                                   getRC32(TrueMO, VRM, MRI));
111
22
          if (Use.getOpcode() == SystemZ::SELRMux)
112
13
            RC = TRI->getCommonSubClass(RC,
113
13
                                        getRC32(Use.getOperand(0), VRM, MRI));
114
22
          if (RC && RC != &SystemZ::GRX32BitRegClass) {
115
18
            addHints(Order, Hints, RC, MRI);
116
18
            // Return true to make these hints the only regs available to
117
18
            // RA. This may mean extra spilling but since the alternative is
118
18
            // a jump sequence expansion of the LOCRMux, it is preferred.
119
18
            return true;
120
18
          }
121
4
122
4
          // Add the other operand of the LOCRMux to the worklist.
123
4
          unsigned OtherReg =
124
4
            (TrueMO.getReg() == Reg ? 
FalseMO.getReg()2
:
TrueMO.getReg()2
);
125
4
          if (MRI->getRegClass(OtherReg) == &SystemZ::GRX32BitRegClass)
126
4
            Worklist.push_back(OtherReg);
127
4
        } // end LOCRMux
128
5.75k
        else if (Use.getOpcode() == SystemZ::CHIMux ||
129
5.75k
                 
Use.getOpcode() == SystemZ::CFIMux5.65k
) {
130
106
          if (Use.getOperand(1).getImm() == 0) {
131
77
            bool OnlyLMuxes = true;
132
77
            for (MachineInstr &DefMI : MRI->def_instructions(VirtReg))
133
76
              if (DefMI.getOpcode() != SystemZ::LMux)
134
70
                OnlyLMuxes = false;
135
77
            if (OnlyLMuxes) {
136
10
              addHints(Order, Hints, &SystemZ::GR32BitRegClass, MRI);
137
10
              // Return false to make these hints preferred but not obligatory.
138
10
              return false;
139
10
            }
140
77
          }
141
106
        } // end CHIMux / CFIMux
142
5.77k
      }
143
1.91k
    }
144
1.91k
  }
145
47.3k
146
47.3k
  
if (47.2k
VRM == nullptr47.2k
)
147
0
    return BaseImplRetVal;
148
47.2k
149
47.2k
  // Add any two address hints after any copy hints.
150
47.2k
  SmallSet<unsigned, 4> TwoAddrHints;
151
47.2k
  for (auto &Use : MRI->reg_nodbg_instructions(VirtReg))
152
143k
    if (SystemZ::getTwoOperandOpcode(Use.getOpcode()) != -1) {
153
2.08k
      const MachineOperand *VRRegMO = nullptr;
154
2.08k
      const MachineOperand *OtherMO = nullptr;
155
2.08k
      const MachineOperand *CommuMO = nullptr;
156
2.08k
      if (VirtReg == Use.getOperand(0).getReg()) {
157
806
        VRRegMO = &Use.getOperand(0);
158
806
        OtherMO = &Use.getOperand(1);
159
806
        if (Use.isCommutable())
160
303
          CommuMO = &Use.getOperand(2);
161
1.27k
      } else if (VirtReg == Use.getOperand(1).getReg()) {
162
780
        VRRegMO = &Use.getOperand(1);
163
780
        OtherMO = &Use.getOperand(0);
164
780
      } else 
if (498
VirtReg == Use.getOperand(2).getReg()498
&&
Use.isCommutable()498
) {
165
315
        VRRegMO = &Use.getOperand(2);
166
315
        OtherMO = &Use.getOperand(0);
167
315
      } else
168
183
        continue;
169
1.90k
170
2.20k
      
auto tryAddHint = [&](const MachineOperand *MO) -> void 1.90k
{
171
2.20k
        Register Reg = MO->getReg();
172
2.20k
        Register PhysReg = isPhysicalRegister(Reg) ? 
Reg0
: VRM->getPhys(Reg);
173
2.20k
        if (PhysReg) {
174
1.08k
          if (MO->getSubReg())
175
228
            PhysReg = getSubReg(PhysReg, MO->getSubReg());
176
1.08k
          if (VRRegMO->getSubReg())
177
65
            PhysReg = getMatchingSuperReg(PhysReg, VRRegMO->getSubReg(),
178
65
                                          MRI->getRegClass(VirtReg));
179
1.08k
          if (!MRI->isReserved(PhysReg) && !is_contained(Hints, PhysReg))
180
1.03k
            TwoAddrHints.insert(PhysReg);
181
1.08k
        }
182
2.20k
      };
183
1.90k
      tryAddHint(OtherMO);
184
1.90k
      if (CommuMO)
185
303
        tryAddHint(CommuMO);
186
1.90k
    }
187
47.2k
  for (MCPhysReg OrderReg : Order)
188
964k
    if (TwoAddrHints.count(OrderReg))
189
1.01k
      Hints.push_back(OrderReg);
190
47.2k
191
47.2k
  return BaseImplRetVal;
192
47.2k
}
193
194
const MCPhysReg *
195
79.3k
SystemZRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
196
79.3k
  const SystemZSubtarget &Subtarget = MF->getSubtarget<SystemZSubtarget>();
197
79.3k
  if (MF->getFunction().getCallingConv() == CallingConv::AnyReg)
198
17
    return Subtarget.hasVector()? 
CSR_SystemZ_AllRegs_Vector_SaveList9
199
17
                                : 
CSR_SystemZ_AllRegs_SaveList8
;
200
79.3k
  if (MF->getSubtarget().getTargetLowering()->supportSwiftError() &&
201
79.3k
      MF->getFunction().getAttributes().hasAttrSomewhere(
202
79.3k
          Attribute::SwiftError))
203
54
    return CSR_SystemZ_SwiftError_SaveList;
204
79.3k
  return CSR_SystemZ_SaveList;
205
79.3k
}
206
207
const uint32_t *
208
SystemZRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
209
1.04k
                                          CallingConv::ID CC) const {
210
1.04k
  const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>();
211
1.04k
  if (CC == CallingConv::AnyReg)
212
12
    return Subtarget.hasVector()? 
CSR_SystemZ_AllRegs_Vector_RegMask1
213
12
                                : 
CSR_SystemZ_AllRegs_RegMask11
;
214
1.03k
  if (MF.getSubtarget().getTargetLowering()->supportSwiftError() &&
215
1.03k
      MF.getFunction().getAttributes().hasAttrSomewhere(
216
1.03k
          Attribute::SwiftError))
217
8
    return CSR_SystemZ_SwiftError_RegMask;
218
1.02k
  return CSR_SystemZ_RegMask;
219
1.02k
}
220
221
BitVector
222
24.3k
SystemZRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
223
24.3k
  BitVector Reserved(getNumRegs());
224
24.3k
  const SystemZFrameLowering *TFI = getFrameLowering(MF);
225
24.3k
226
24.3k
  if (TFI->hasFP(MF)) {
227
255
    // R11D is the frame pointer.  Reserve all aliases.
228
255
    Reserved.set(SystemZ::R11D);
229
255
    Reserved.set(SystemZ::R11L);
230
255
    Reserved.set(SystemZ::R11H);
231
255
    Reserved.set(SystemZ::R10Q);
232
255
  }
233
24.3k
234
24.3k
  // R15D is the stack pointer.  Reserve all aliases.
235
24.3k
  Reserved.set(SystemZ::R15D);
236
24.3k
  Reserved.set(SystemZ::R15L);
237
24.3k
  Reserved.set(SystemZ::R15H);
238
24.3k
  Reserved.set(SystemZ::R14Q);
239
24.3k
240
24.3k
  // A0 and A1 hold the thread pointer.
241
24.3k
  Reserved.set(SystemZ::A0);
242
24.3k
  Reserved.set(SystemZ::A1);
243
24.3k
244
24.3k
  // FPC is the floating-point control register.
245
24.3k
  Reserved.set(SystemZ::FPC);
246
24.3k
247
24.3k
  return Reserved;
248
24.3k
}
249
250
void
251
SystemZRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
252
                                         int SPAdj, unsigned FIOperandNum,
253
3.98k
                                         RegScavenger *RS) const {
254
3.98k
  assert(SPAdj == 0 && "Outgoing arguments should be part of the frame");
255
3.98k
256
3.98k
  MachineBasicBlock &MBB = *MI->getParent();
257
3.98k
  MachineFunction &MF = *MBB.getParent();
258
3.98k
  auto *TII =
259
3.98k
      static_cast<const SystemZInstrInfo *>(MF.getSubtarget().getInstrInfo());
260
3.98k
  const SystemZFrameLowering *TFI = getFrameLowering(MF);
261
3.98k
  DebugLoc DL = MI->getDebugLoc();
262
3.98k
263
3.98k
  // Decompose the frame index into a base and offset.
264
3.98k
  int FrameIndex = MI->getOperand(FIOperandNum).getIndex();
265
3.98k
  unsigned BasePtr;
266
3.98k
  int64_t Offset = (TFI->getFrameIndexReference(MF, FrameIndex, BasePtr) +
267
3.98k
                    MI->getOperand(FIOperandNum + 1).getImm());
268
3.98k
269
3.98k
  // Special handling of dbg_value instructions.
270
3.98k
  if (MI->isDebugValue()) {
271
0
    MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, /*isDef*/ false);
272
0
    MI->getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
273
0
    return;
274
0
  }
275
3.98k
276
3.98k
  // See if the offset is in range, or if an equivalent instruction that
277
3.98k
  // accepts the offset exists.
278
3.98k
  unsigned Opcode = MI->getOpcode();
279
3.98k
  unsigned OpcodeForOffset = TII->getOpcodeForOffset(Opcode, Offset);
280
3.98k
  if (OpcodeForOffset) {
281
3.87k
    if (OpcodeForOffset == SystemZ::LE &&
282
3.87k
        
MF.getSubtarget<SystemZSubtarget>().hasVector()14
) {
283
0
      // If LE is ok for offset, use LDE instead on z13.
284
0
      OpcodeForOffset = SystemZ::LDE32;
285
0
    }
286
3.87k
    MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
287
3.87k
  }
288
102
  else {
289
102
    // Create an anchor point that is in range.  Start at 0xffff so that
290
102
    // can use LLILH to load the immediate.
291
102
    int64_t OldOffset = Offset;
292
102
    int64_t Mask = 0xffff;
293
266
    do {
294
266
      Offset = OldOffset & Mask;
295
266
      OpcodeForOffset = TII->getOpcodeForOffset(Opcode, Offset);
296
266
      Mask >>= 1;
297
266
      assert(Mask && "One offset must be OK");
298
266
    } while (!OpcodeForOffset);
299
102
300
102
    unsigned ScratchReg =
301
102
      MF.getRegInfo().createVirtualRegister(&SystemZ::ADDR64BitRegClass);
302
102
    int64_t HighOffset = OldOffset - Offset;
303
102
304
102
    if (MI->getDesc().TSFlags & SystemZII::HasIndex
305
102
        && 
MI->getOperand(FIOperandNum + 2).getReg() == 062
) {
306
58
      // Load the offset into the scratch register and use it as an index.
307
58
      // The scratch register then dies here.
308
58
      TII->loadImmediate(MBB, MI, ScratchReg, HighOffset);
309
58
      MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
310
58
      MI->getOperand(FIOperandNum + 2).ChangeToRegister(ScratchReg,
311
58
                                                        false, false, true);
312
58
    } else {
313
44
      // Load the anchor address into a scratch register.
314
44
      unsigned LAOpcode = TII->getOpcodeForOffset(SystemZ::LA, HighOffset);
315
44
      if (LAOpcode)
316
24
        BuildMI(MBB, MI, DL, TII->get(LAOpcode),ScratchReg)
317
24
          .addReg(BasePtr).addImm(HighOffset).addReg(0);
318
20
      else {
319
20
        // Load the high offset into the scratch register and use it as
320
20
        // an index.
321
20
        TII->loadImmediate(MBB, MI, ScratchReg, HighOffset);
322
20
        BuildMI(MBB, MI, DL, TII->get(SystemZ::AGR),ScratchReg)
323
20
          .addReg(ScratchReg, RegState::Kill).addReg(BasePtr);
324
20
      }
325
44
326
44
      // Use the scratch register as the base.  It then dies here.
327
44
      MI->getOperand(FIOperandNum).ChangeToRegister(ScratchReg,
328
44
                                                    false, false, true);
329
44
    }
330
102
  }
331
3.98k
  MI->setDesc(TII->get(OpcodeForOffset));
332
3.98k
  MI->getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
333
3.98k
}
334
335
bool SystemZRegisterInfo::shouldCoalesce(MachineInstr *MI,
336
                                  const TargetRegisterClass *SrcRC,
337
                                  unsigned SubReg,
338
                                  const TargetRegisterClass *DstRC,
339
                                  unsigned DstSubReg,
340
                                  const TargetRegisterClass *NewRC,
341
17.7k
                                  LiveIntervals &LIS) const {
342
17.7k
  assert (MI->isCopy() && "Only expecting COPY instructions");
343
17.7k
344
17.7k
  // Coalesce anything which is not a COPY involving a subreg to/from GR128.
345
17.7k
  if (!(NewRC->hasSuperClassEq(&SystemZ::GR128BitRegClass) &&
346
17.7k
        
(888
getRegSizeInBits(*SrcRC) <= 64888
||
getRegSizeInBits(*DstRC) <= 64648
)))
347
17.2k
    return true;
348
508
349
508
  // Allow coalescing of a GR128 subreg COPY only if the live ranges are small
350
508
  // and local to one MBB with not too much interferring registers. Otherwise
351
508
  // regalloc may run out of registers.
352
508
353
508
  unsigned WideOpNo = (getRegSizeInBits(*SrcRC) == 128 ? 
1268
:
0240
);
354
508
  unsigned GR128Reg = MI->getOperand(WideOpNo).getReg();
355
508
  unsigned GRNarReg = MI->getOperand((WideOpNo == 1) ? 
0268
:
1240
).getReg();
356
508
  LiveInterval &IntGR128 = LIS.getInterval(GR128Reg);
357
508
  LiveInterval &IntGRNar = LIS.getInterval(GRNarReg);
358
508
359
508
  // Check that the two virtual registers are local to MBB.
360
508
  MachineBasicBlock *MBB = MI->getParent();
361
508
  MachineInstr *FirstMI_GR128 =
362
508
    LIS.getInstructionFromIndex(IntGR128.beginIndex());
363
508
  MachineInstr *FirstMI_GRNar =
364
508
    LIS.getInstructionFromIndex(IntGRNar.beginIndex());
365
508
  MachineInstr *LastMI_GR128 = LIS.getInstructionFromIndex(IntGR128.endIndex());
366
508
  MachineInstr *LastMI_GRNar = LIS.getInstructionFromIndex(IntGRNar.endIndex());
367
508
  if ((!FirstMI_GR128 || FirstMI_GR128->getParent() != MBB) ||
368
508
      
(504
!FirstMI_GRNar504
||
FirstMI_GRNar->getParent() != MBB504
) ||
369
508
      
(502
!LastMI_GR128502
||
LastMI_GR128->getParent() != MBB499
) ||
370
508
      
(499
!LastMI_GRNar499
||
LastMI_GRNar->getParent() != MBB498
))
371
10
    return false;
372
498
373
498
  MachineBasicBlock::iterator MII = nullptr, MEE = nullptr;
374
498
  if (WideOpNo == 1) {
375
264
    MII = FirstMI_GR128;
376
264
    MEE = LastMI_GRNar;
377
264
  } else {
378
234
    MII = FirstMI_GRNar;
379
234
    MEE = LastMI_GR128;
380
234
  }
381
498
382
498
  // Check if coalescing seems safe by finding the set of clobbered physreg
383
498
  // pairs in the region.
384
498
  BitVector PhysClobbered(getNumRegs());
385
498
  MEE++;
386
3.00k
  for (; MII != MEE; 
++MII2.50k
) {
387
2.50k
    for (const MachineOperand &MO : MII->operands())
388
6.47k
      if (MO.isReg() && 
isPhysicalRegister(MO.getReg())5.85k
) {
389
486
        for (MCSuperRegIterator SI(MO.getReg(), this, true/*IncludeSelf*/);
390
1.02k
             SI.isValid(); 
++SI536
)
391
840
          if (NewRC->contains(*SI)) {
392
304
            PhysClobbered.set(*SI);
393
304
            break;
394
304
          }
395
486
      }
396
2.50k
  }
397
498
398
498
  // Demand an arbitrary margin of free regs.
399
498
  unsigned const DemandedFreeGR128 = 3;
400
498
  if (PhysClobbered.count() > (NewRC->getNumRegs() - DemandedFreeGR128))
401
2
    return false;
402
496
403
496
  return true;
404
496
}
405
406
Register
407
4.79k
SystemZRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
408
4.79k
  const SystemZFrameLowering *TFI = getFrameLowering(MF);
409
4.79k
  return TFI->hasFP(MF) ? 
SystemZ::R11D235
:
SystemZ::R15D4.56k
;
410
4.79k
}
411
412
const TargetRegisterClass *
413
0
SystemZRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
414
0
  if (RC == &SystemZ::CCRRegClass)
415
0
    return &SystemZ::GR32BitRegClass;
416
0
  return RC;
417
0
}
418