Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h
Line
Count
Source (jump to first uncovered line)
1
//==- WebAssemblyMCTargetDesc.h - WebAssembly Target Descriptions -*- C++ -*-=//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
///
9
/// \file
10
/// This file provides WebAssembly-specific target descriptions.
11
///
12
//===----------------------------------------------------------------------===//
13
14
#ifndef LLVM_LIB_TARGET_WEBASSEMBLY_MCTARGETDESC_WEBASSEMBLYMCTARGETDESC_H
15
#define LLVM_LIB_TARGET_WEBASSEMBLY_MCTARGETDESC_WEBASSEMBLYMCTARGETDESC_H
16
17
#include "../WebAssemblySubtarget.h"
18
#include "llvm/BinaryFormat/Wasm.h"
19
#include "llvm/MC/MCInstrDesc.h"
20
#include "llvm/Support/DataTypes.h"
21
#include <memory>
22
23
namespace llvm {
24
25
class MCAsmBackend;
26
class MCCodeEmitter;
27
class MCContext;
28
class MCInstrInfo;
29
class MCObjectTargetWriter;
30
class MCSubtargetInfo;
31
class MVT;
32
class Target;
33
class Triple;
34
class raw_pwrite_stream;
35
36
MCCodeEmitter *createWebAssemblyMCCodeEmitter(const MCInstrInfo &MCII);
37
38
MCAsmBackend *createWebAssemblyAsmBackend(const Triple &TT);
39
40
std::unique_ptr<MCObjectTargetWriter>
41
createWebAssemblyWasmObjectWriter(bool Is64Bit);
42
43
namespace WebAssembly {
44
enum OperandType {
45
  /// Basic block label in a branch construct.
46
  OPERAND_BASIC_BLOCK = MCOI::OPERAND_FIRST_TARGET,
47
  /// Local index.
48
  OPERAND_LOCAL,
49
  /// Global index.
50
  OPERAND_GLOBAL,
51
  /// 32-bit integer immediates.
52
  OPERAND_I32IMM,
53
  /// 64-bit integer immediates.
54
  OPERAND_I64IMM,
55
  /// 32-bit floating-point immediates.
56
  OPERAND_F32IMM,
57
  /// 64-bit floating-point immediates.
58
  OPERAND_F64IMM,
59
  /// 8-bit vector lane immediate
60
  OPERAND_VEC_I8IMM,
61
  /// 16-bit vector lane immediate
62
  OPERAND_VEC_I16IMM,
63
  /// 32-bit vector lane immediate
64
  OPERAND_VEC_I32IMM,
65
  /// 64-bit vector lane immediate
66
  OPERAND_VEC_I64IMM,
67
  /// 32-bit unsigned function indices.
68
  OPERAND_FUNCTION32,
69
  /// 32-bit unsigned memory offsets.
70
  OPERAND_OFFSET32,
71
  /// p2align immediate for load and store address alignment.
72
  OPERAND_P2ALIGN,
73
  /// signature immediate for block/loop.
74
  OPERAND_SIGNATURE,
75
  /// type signature immediate for call_indirect.
76
  OPERAND_TYPEINDEX,
77
  /// Event index.
78
  OPERAND_EVENT,
79
  /// A list of branch targets for br_list.
80
  OPERAND_BRLIST,
81
};
82
} // end namespace WebAssembly
83
84
namespace WebAssemblyII {
85
86
/// Target Operand Flag enum.
87
enum TOF {
88
  MO_NO_FLAG = 0,
89
90
  // On a symbol operand this indicates that the immediate is a wasm global
91
  // index.  The value of the wasm global will be set to the symbol address at
92
  // runtime.  This adds a level of indirection similar to the GOT on native
93
  // platforms.
94
  MO_GOT,
95
96
  // On a symbol operand this indicates that the immediate is the symbol
97
  // address relative the __memory_base wasm global.
98
  // Only applicable to data symbols.
99
  MO_MEMORY_BASE_REL,
100
101
  // On a symbol operand this indicates that the immediate is the symbol
102
  // address relative the __table_base wasm global.
103
  // Only applicable to function symbols.
104
  MO_TABLE_BASE_REL,
105
};
106
107
} // end namespace WebAssemblyII
108
109
} // end namespace llvm
110
111
// Defines symbolic names for WebAssembly registers. This defines a mapping from
112
// register name to register number.
113
//
114
#define GET_REGINFO_ENUM
115
#include "WebAssemblyGenRegisterInfo.inc"
116
117
// Defines symbolic names for the WebAssembly instructions.
118
//
119
#define GET_INSTRINFO_ENUM
120
#include "WebAssemblyGenInstrInfo.inc"
121
122
namespace llvm {
123
namespace WebAssembly {
124
125
/// This is used to indicate block signatures.
126
enum class ExprType : unsigned {
127
  Void = 0x40,
128
  I32 = 0x7F,
129
  I64 = 0x7E,
130
  F32 = 0x7D,
131
  F64 = 0x7C,
132
  V128 = 0x7B,
133
  Exnref = 0x68,
134
  Invalid = 0x00
135
};
136
137
/// Instruction opcodes emitted via means other than CodeGen.
138
static const unsigned Nop = 0x01;
139
static const unsigned End = 0x0b;
140
141
wasm::ValType toValType(const MVT &Ty);
142
143
/// Return the default p2align value for a load or store with the given opcode.
144
11.6k
inline unsigned GetDefaultP2AlignAny(unsigned Opc) {
145
11.6k
  switch (Opc) {
146
11.6k
  case WebAssembly::LOAD8_S_I32:
147
3.04k
  case WebAssembly::LOAD8_S_I32_S:
148
3.04k
  case WebAssembly::LOAD8_U_I32:
149
3.04k
  case WebAssembly::LOAD8_U_I32_S:
150
3.04k
  case WebAssembly::LOAD8_S_I64:
151
3.04k
  case WebAssembly::LOAD8_S_I64_S:
152
3.04k
  case WebAssembly::LOAD8_U_I64:
153
3.04k
  case WebAssembly::LOAD8_U_I64_S:
154
3.04k
  case WebAssembly::ATOMIC_LOAD8_U_I32:
155
3.04k
  case WebAssembly::ATOMIC_LOAD8_U_I32_S:
156
3.04k
  case WebAssembly::ATOMIC_LOAD8_U_I64:
157
3.04k
  case WebAssembly::ATOMIC_LOAD8_U_I64_S:
158
3.04k
  case WebAssembly::STORE8_I32:
159
3.04k
  case WebAssembly::STORE8_I32_S:
160
3.04k
  case WebAssembly::STORE8_I64:
161
3.04k
  case WebAssembly::STORE8_I64_S:
162
3.04k
  case WebAssembly::ATOMIC_STORE8_I32:
163
3.04k
  case WebAssembly::ATOMIC_STORE8_I32_S:
164
3.04k
  case WebAssembly::ATOMIC_STORE8_I64:
165
3.04k
  case WebAssembly::ATOMIC_STORE8_I64_S:
166
3.04k
  case WebAssembly::ATOMIC_RMW8_U_ADD_I32:
167
3.04k
  case WebAssembly::ATOMIC_RMW8_U_ADD_I32_S:
168
3.04k
  case WebAssembly::ATOMIC_RMW8_U_ADD_I64:
169
3.04k
  case WebAssembly::ATOMIC_RMW8_U_ADD_I64_S:
170
3.04k
  case WebAssembly::ATOMIC_RMW8_U_SUB_I32:
171
3.04k
  case WebAssembly::ATOMIC_RMW8_U_SUB_I32_S:
172
3.04k
  case WebAssembly::ATOMIC_RMW8_U_SUB_I64:
173
3.04k
  case WebAssembly::ATOMIC_RMW8_U_SUB_I64_S:
174
3.04k
  case WebAssembly::ATOMIC_RMW8_U_AND_I32:
175
3.04k
  case WebAssembly::ATOMIC_RMW8_U_AND_I32_S:
176
3.04k
  case WebAssembly::ATOMIC_RMW8_U_AND_I64:
177
3.04k
  case WebAssembly::ATOMIC_RMW8_U_AND_I64_S:
178
3.04k
  case WebAssembly::ATOMIC_RMW8_U_OR_I32:
179
3.04k
  case WebAssembly::ATOMIC_RMW8_U_OR_I32_S:
180
3.04k
  case WebAssembly::ATOMIC_RMW8_U_OR_I64:
181
3.04k
  case WebAssembly::ATOMIC_RMW8_U_OR_I64_S:
182
3.04k
  case WebAssembly::ATOMIC_RMW8_U_XOR_I32:
183
3.04k
  case WebAssembly::ATOMIC_RMW8_U_XOR_I32_S:
184
3.04k
  case WebAssembly::ATOMIC_RMW8_U_XOR_I64:
185
3.04k
  case WebAssembly::ATOMIC_RMW8_U_XOR_I64_S:
186
3.04k
  case WebAssembly::ATOMIC_RMW8_U_XCHG_I32:
187
3.04k
  case WebAssembly::ATOMIC_RMW8_U_XCHG_I32_S:
188
3.04k
  case WebAssembly::ATOMIC_RMW8_U_XCHG_I64:
189
3.04k
  case WebAssembly::ATOMIC_RMW8_U_XCHG_I64_S:
190
3.04k
  case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32:
191
3.04k
  case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_S:
192
3.04k
  case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64:
193
3.04k
  case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_S:
194
3.04k
    return 0;
195
3.04k
  case WebAssembly::LOAD16_S_I32:
196
1.55k
  case WebAssembly::LOAD16_S_I32_S:
197
1.55k
  case WebAssembly::LOAD16_U_I32:
198
1.55k
  case WebAssembly::LOAD16_U_I32_S:
199
1.55k
  case WebAssembly::LOAD16_S_I64:
200
1.55k
  case WebAssembly::LOAD16_S_I64_S:
201
1.55k
  case WebAssembly::LOAD16_U_I64:
202
1.55k
  case WebAssembly::LOAD16_U_I64_S:
203
1.55k
  case WebAssembly::ATOMIC_LOAD16_U_I32:
204
1.55k
  case WebAssembly::ATOMIC_LOAD16_U_I32_S:
205
1.55k
  case WebAssembly::ATOMIC_LOAD16_U_I64:
206
1.55k
  case WebAssembly::ATOMIC_LOAD16_U_I64_S:
207
1.55k
  case WebAssembly::STORE16_I32:
208
1.55k
  case WebAssembly::STORE16_I32_S:
209
1.55k
  case WebAssembly::STORE16_I64:
210
1.55k
  case WebAssembly::STORE16_I64_S:
211
1.55k
  case WebAssembly::ATOMIC_STORE16_I32:
212
1.55k
  case WebAssembly::ATOMIC_STORE16_I32_S:
213
1.55k
  case WebAssembly::ATOMIC_STORE16_I64:
214
1.55k
  case WebAssembly::ATOMIC_STORE16_I64_S:
215
1.55k
  case WebAssembly::ATOMIC_RMW16_U_ADD_I32:
216
1.55k
  case WebAssembly::ATOMIC_RMW16_U_ADD_I32_S:
217
1.55k
  case WebAssembly::ATOMIC_RMW16_U_ADD_I64:
218
1.55k
  case WebAssembly::ATOMIC_RMW16_U_ADD_I64_S:
219
1.55k
  case WebAssembly::ATOMIC_RMW16_U_SUB_I32:
220
1.55k
  case WebAssembly::ATOMIC_RMW16_U_SUB_I32_S:
221
1.55k
  case WebAssembly::ATOMIC_RMW16_U_SUB_I64:
222
1.55k
  case WebAssembly::ATOMIC_RMW16_U_SUB_I64_S:
223
1.55k
  case WebAssembly::ATOMIC_RMW16_U_AND_I32:
224
1.55k
  case WebAssembly::ATOMIC_RMW16_U_AND_I32_S:
225
1.55k
  case WebAssembly::ATOMIC_RMW16_U_AND_I64:
226
1.55k
  case WebAssembly::ATOMIC_RMW16_U_AND_I64_S:
227
1.55k
  case WebAssembly::ATOMIC_RMW16_U_OR_I32:
228
1.55k
  case WebAssembly::ATOMIC_RMW16_U_OR_I32_S:
229
1.55k
  case WebAssembly::ATOMIC_RMW16_U_OR_I64:
230
1.55k
  case WebAssembly::ATOMIC_RMW16_U_OR_I64_S:
231
1.55k
  case WebAssembly::ATOMIC_RMW16_U_XOR_I32:
232
1.55k
  case WebAssembly::ATOMIC_RMW16_U_XOR_I32_S:
233
1.55k
  case WebAssembly::ATOMIC_RMW16_U_XOR_I64:
234
1.55k
  case WebAssembly::ATOMIC_RMW16_U_XOR_I64_S:
235
1.55k
  case WebAssembly::ATOMIC_RMW16_U_XCHG_I32:
236
1.55k
  case WebAssembly::ATOMIC_RMW16_U_XCHG_I32_S:
237
1.55k
  case WebAssembly::ATOMIC_RMW16_U_XCHG_I64:
238
1.55k
  case WebAssembly::ATOMIC_RMW16_U_XCHG_I64_S:
239
1.55k
  case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32:
240
1.55k
  case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_S:
241
1.55k
  case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64:
242
1.55k
  case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_S:
243
1.55k
    return 1;
244
3.25k
  case WebAssembly::LOAD_I32:
245
3.25k
  case WebAssembly::LOAD_I32_S:
246
3.25k
  case WebAssembly::LOAD_F32:
247
3.25k
  case WebAssembly::LOAD_F32_S:
248
3.25k
  case WebAssembly::STORE_I32:
249
3.25k
  case WebAssembly::STORE_I32_S:
250
3.25k
  case WebAssembly::STORE_F32:
251
3.25k
  case WebAssembly::STORE_F32_S:
252
3.25k
  case WebAssembly::LOAD32_S_I64:
253
3.25k
  case WebAssembly::LOAD32_S_I64_S:
254
3.25k
  case WebAssembly::LOAD32_U_I64:
255
3.25k
  case WebAssembly::LOAD32_U_I64_S:
256
3.25k
  case WebAssembly::STORE32_I64:
257
3.25k
  case WebAssembly::STORE32_I64_S:
258
3.25k
  case WebAssembly::ATOMIC_LOAD_I32:
259
3.25k
  case WebAssembly::ATOMIC_LOAD_I32_S:
260
3.25k
  case WebAssembly::ATOMIC_LOAD32_U_I64:
261
3.25k
  case WebAssembly::ATOMIC_LOAD32_U_I64_S:
262
3.25k
  case WebAssembly::ATOMIC_STORE_I32:
263
3.25k
  case WebAssembly::ATOMIC_STORE_I32_S:
264
3.25k
  case WebAssembly::ATOMIC_STORE32_I64:
265
3.25k
  case WebAssembly::ATOMIC_STORE32_I64_S:
266
3.25k
  case WebAssembly::ATOMIC_RMW_ADD_I32:
267
3.25k
  case WebAssembly::ATOMIC_RMW_ADD_I32_S:
268
3.25k
  case WebAssembly::ATOMIC_RMW32_U_ADD_I64:
269
3.25k
  case WebAssembly::ATOMIC_RMW32_U_ADD_I64_S:
270
3.25k
  case WebAssembly::ATOMIC_RMW_SUB_I32:
271
3.25k
  case WebAssembly::ATOMIC_RMW_SUB_I32_S:
272
3.25k
  case WebAssembly::ATOMIC_RMW32_U_SUB_I64:
273
3.25k
  case WebAssembly::ATOMIC_RMW32_U_SUB_I64_S:
274
3.25k
  case WebAssembly::ATOMIC_RMW_AND_I32:
275
3.25k
  case WebAssembly::ATOMIC_RMW_AND_I32_S:
276
3.25k
  case WebAssembly::ATOMIC_RMW32_U_AND_I64:
277
3.25k
  case WebAssembly::ATOMIC_RMW32_U_AND_I64_S:
278
3.25k
  case WebAssembly::ATOMIC_RMW_OR_I32:
279
3.25k
  case WebAssembly::ATOMIC_RMW_OR_I32_S:
280
3.25k
  case WebAssembly::ATOMIC_RMW32_U_OR_I64:
281
3.25k
  case WebAssembly::ATOMIC_RMW32_U_OR_I64_S:
282
3.25k
  case WebAssembly::ATOMIC_RMW_XOR_I32:
283
3.25k
  case WebAssembly::ATOMIC_RMW_XOR_I32_S:
284
3.25k
  case WebAssembly::ATOMIC_RMW32_U_XOR_I64:
285
3.25k
  case WebAssembly::ATOMIC_RMW32_U_XOR_I64_S:
286
3.25k
  case WebAssembly::ATOMIC_RMW_XCHG_I32:
287
3.25k
  case WebAssembly::ATOMIC_RMW_XCHG_I32_S:
288
3.25k
  case WebAssembly::ATOMIC_RMW32_U_XCHG_I64:
289
3.25k
  case WebAssembly::ATOMIC_RMW32_U_XCHG_I64_S:
290
3.25k
  case WebAssembly::ATOMIC_RMW_CMPXCHG_I32:
291
3.25k
  case WebAssembly::ATOMIC_RMW_CMPXCHG_I32_S:
292
3.25k
  case WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64:
293
3.25k
  case WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_S:
294
3.25k
  case WebAssembly::ATOMIC_NOTIFY:
295
3.25k
  case WebAssembly::ATOMIC_NOTIFY_S:
296
3.25k
  case WebAssembly::ATOMIC_WAIT_I32:
297
3.25k
  case WebAssembly::ATOMIC_WAIT_I32_S:
298
3.25k
    return 2;
299
3.25k
  case WebAssembly::LOAD_I64:
300
2.86k
  case WebAssembly::LOAD_I64_S:
301
2.86k
  case WebAssembly::LOAD_F64:
302
2.86k
  case WebAssembly::LOAD_F64_S:
303
2.86k
  case WebAssembly::STORE_I64:
304
2.86k
  case WebAssembly::STORE_I64_S:
305
2.86k
  case WebAssembly::STORE_F64:
306
2.86k
  case WebAssembly::STORE_F64_S:
307
2.86k
  case WebAssembly::ATOMIC_LOAD_I64:
308
2.86k
  case WebAssembly::ATOMIC_LOAD_I64_S:
309
2.86k
  case WebAssembly::ATOMIC_STORE_I64:
310
2.86k
  case WebAssembly::ATOMIC_STORE_I64_S:
311
2.86k
  case WebAssembly::ATOMIC_RMW_ADD_I64:
312
2.86k
  case WebAssembly::ATOMIC_RMW_ADD_I64_S:
313
2.86k
  case WebAssembly::ATOMIC_RMW_SUB_I64:
314
2.86k
  case WebAssembly::ATOMIC_RMW_SUB_I64_S:
315
2.86k
  case WebAssembly::ATOMIC_RMW_AND_I64:
316
2.86k
  case WebAssembly::ATOMIC_RMW_AND_I64_S:
317
2.86k
  case WebAssembly::ATOMIC_RMW_OR_I64:
318
2.86k
  case WebAssembly::ATOMIC_RMW_OR_I64_S:
319
2.86k
  case WebAssembly::ATOMIC_RMW_XOR_I64:
320
2.86k
  case WebAssembly::ATOMIC_RMW_XOR_I64_S:
321
2.86k
  case WebAssembly::ATOMIC_RMW_XCHG_I64:
322
2.86k
  case WebAssembly::ATOMIC_RMW_XCHG_I64_S:
323
2.86k
  case WebAssembly::ATOMIC_RMW_CMPXCHG_I64:
324
2.86k
  case WebAssembly::ATOMIC_RMW_CMPXCHG_I64_S:
325
2.86k
  case WebAssembly::ATOMIC_WAIT_I64:
326
2.86k
  case WebAssembly::ATOMIC_WAIT_I64_S:
327
2.86k
    return 3;
328
2.86k
  case WebAssembly::LOAD_v16i8:
329
516
  case WebAssembly::LOAD_v16i8_S:
330
516
  case WebAssembly::LOAD_v8i16:
331
516
  case WebAssembly::LOAD_v8i16_S:
332
516
  case WebAssembly::LOAD_v4i32:
333
516
  case WebAssembly::LOAD_v4i32_S:
334
516
  case WebAssembly::LOAD_v2i64:
335
516
  case WebAssembly::LOAD_v2i64_S:
336
516
  case WebAssembly::LOAD_v4f32:
337
516
  case WebAssembly::LOAD_v4f32_S:
338
516
  case WebAssembly::LOAD_v2f64:
339
516
  case WebAssembly::LOAD_v2f64_S:
340
516
  case WebAssembly::STORE_v16i8:
341
516
  case WebAssembly::STORE_v16i8_S:
342
516
  case WebAssembly::STORE_v8i16:
343
516
  case WebAssembly::STORE_v8i16_S:
344
516
  case WebAssembly::STORE_v4i32:
345
516
  case WebAssembly::STORE_v4i32_S:
346
516
  case WebAssembly::STORE_v2i64:
347
516
  case WebAssembly::STORE_v2i64_S:
348
516
  case WebAssembly::STORE_v4f32:
349
516
  case WebAssembly::STORE_v4f32_S:
350
516
  case WebAssembly::STORE_v2f64:
351
516
  case WebAssembly::STORE_v2f64_S:
352
516
    return 4;
353
516
  default:
354
353
    return -1;
355
11.6k
  }
356
11.6k
}
357
358
11.1k
inline unsigned GetDefaultP2Align(unsigned Opc) {
359
11.1k
  auto Align = GetDefaultP2AlignAny(Opc);
360
11.1k
  if (Align == -1U) {
361
0
    llvm_unreachable("Only loads and stores have p2align values");
362
0
  }
363
11.1k
  return Align;
364
11.1k
}
365
366
291k
inline bool isArgument(unsigned Opc) {
367
291k
  switch (Opc) {
368
291k
  case WebAssembly::ARGUMENT_i32:
369
59.4k
  case WebAssembly::ARGUMENT_i32_S:
370
59.4k
  case WebAssembly::ARGUMENT_i64:
371
59.4k
  case WebAssembly::ARGUMENT_i64_S:
372
59.4k
  case WebAssembly::ARGUMENT_f32:
373
59.4k
  case WebAssembly::ARGUMENT_f32_S:
374
59.4k
  case WebAssembly::ARGUMENT_f64:
375
59.4k
  case WebAssembly::ARGUMENT_f64_S:
376
59.4k
  case WebAssembly::ARGUMENT_v16i8:
377
59.4k
  case WebAssembly::ARGUMENT_v16i8_S:
378
59.4k
  case WebAssembly::ARGUMENT_v8i16:
379
59.4k
  case WebAssembly::ARGUMENT_v8i16_S:
380
59.4k
  case WebAssembly::ARGUMENT_v4i32:
381
59.4k
  case WebAssembly::ARGUMENT_v4i32_S:
382
59.4k
  case WebAssembly::ARGUMENT_v2i64:
383
59.4k
  case WebAssembly::ARGUMENT_v2i64_S:
384
59.4k
  case WebAssembly::ARGUMENT_v4f32:
385
59.4k
  case WebAssembly::ARGUMENT_v4f32_S:
386
59.4k
  case WebAssembly::ARGUMENT_v2f64:
387
59.4k
  case WebAssembly::ARGUMENT_v2f64_S:
388
59.4k
  case WebAssembly::ARGUMENT_exnref:
389
59.4k
  case WebAssembly::ARGUMENT_exnref_S:
390
59.4k
    return true;
391
231k
  default:
392
231k
    return false;
393
291k
  }
394
291k
}
395
396
8.42k
inline bool isCopy(unsigned Opc) {
397
8.42k
  switch (Opc) {
398
8.42k
  case WebAssembly::COPY_I32:
399
42
  case WebAssembly::COPY_I32_S:
400
42
  case WebAssembly::COPY_I64:
401
42
  case WebAssembly::COPY_I64_S:
402
42
  case WebAssembly::COPY_F32:
403
42
  case WebAssembly::COPY_F32_S:
404
42
  case WebAssembly::COPY_F64:
405
42
  case WebAssembly::COPY_F64_S:
406
42
  case WebAssembly::COPY_V128:
407
42
  case WebAssembly::COPY_V128_S:
408
42
  case WebAssembly::COPY_EXNREF:
409
42
  case WebAssembly::COPY_EXNREF_S:
410
42
    return true;
411
8.37k
  default:
412
8.37k
    return false;
413
8.42k
  }
414
8.42k
}
415
416
8.74k
inline bool isTee(unsigned Opc) {
417
8.74k
  switch (Opc) {
418
8.74k
  case WebAssembly::TEE_I32:
419
323
  case WebAssembly::TEE_I32_S:
420
323
  case WebAssembly::TEE_I64:
421
323
  case WebAssembly::TEE_I64_S:
422
323
  case WebAssembly::TEE_F32:
423
323
  case WebAssembly::TEE_F32_S:
424
323
  case WebAssembly::TEE_F64:
425
323
  case WebAssembly::TEE_F64_S:
426
323
  case WebAssembly::TEE_V128:
427
323
  case WebAssembly::TEE_V128_S:
428
323
  case WebAssembly::TEE_EXNREF:
429
323
  case WebAssembly::TEE_EXNREF_S:
430
323
    return true;
431
8.42k
  default:
432
8.42k
    return false;
433
8.74k
  }
434
8.74k
}
435
436
0
inline bool isCallDirect(unsigned Opc) {
437
0
  switch (Opc) {
438
0
  case WebAssembly::CALL_VOID:
439
0
  case WebAssembly::CALL_VOID_S:
440
0
  case WebAssembly::CALL_i32:
441
0
  case WebAssembly::CALL_i32_S:
442
0
  case WebAssembly::CALL_i64:
443
0
  case WebAssembly::CALL_i64_S:
444
0
  case WebAssembly::CALL_f32:
445
0
  case WebAssembly::CALL_f32_S:
446
0
  case WebAssembly::CALL_f64:
447
0
  case WebAssembly::CALL_f64_S:
448
0
  case WebAssembly::CALL_v16i8:
449
0
  case WebAssembly::CALL_v16i8_S:
450
0
  case WebAssembly::CALL_v8i16:
451
0
  case WebAssembly::CALL_v8i16_S:
452
0
  case WebAssembly::CALL_v4i32:
453
0
  case WebAssembly::CALL_v4i32_S:
454
0
  case WebAssembly::CALL_v2i64:
455
0
  case WebAssembly::CALL_v2i64_S:
456
0
  case WebAssembly::CALL_v4f32:
457
0
  case WebAssembly::CALL_v4f32_S:
458
0
  case WebAssembly::CALL_v2f64:
459
0
  case WebAssembly::CALL_v2f64_S:
460
0
  case WebAssembly::CALL_exnref:
461
0
  case WebAssembly::CALL_exnref_S:
462
0
  case WebAssembly::RET_CALL:
463
0
  case WebAssembly::RET_CALL_S:
464
0
    return true;
465
0
  default:
466
0
    return false;
467
0
  }
468
0
}
469
470
499
inline bool isCallIndirect(unsigned Opc) {
471
499
  switch (Opc) {
472
499
  case WebAssembly::CALL_INDIRECT_VOID:
473
70
  case WebAssembly::CALL_INDIRECT_VOID_S:
474
70
  case WebAssembly::CALL_INDIRECT_i32:
475
70
  case WebAssembly::CALL_INDIRECT_i32_S:
476
70
  case WebAssembly::CALL_INDIRECT_i64:
477
70
  case WebAssembly::CALL_INDIRECT_i64_S:
478
70
  case WebAssembly::CALL_INDIRECT_f32:
479
70
  case WebAssembly::CALL_INDIRECT_f32_S:
480
70
  case WebAssembly::CALL_INDIRECT_f64:
481
70
  case WebAssembly::CALL_INDIRECT_f64_S:
482
70
  case WebAssembly::CALL_INDIRECT_v16i8:
483
70
  case WebAssembly::CALL_INDIRECT_v16i8_S:
484
70
  case WebAssembly::CALL_INDIRECT_v8i16:
485
70
  case WebAssembly::CALL_INDIRECT_v8i16_S:
486
70
  case WebAssembly::CALL_INDIRECT_v4i32:
487
70
  case WebAssembly::CALL_INDIRECT_v4i32_S:
488
70
  case WebAssembly::CALL_INDIRECT_v2i64:
489
70
  case WebAssembly::CALL_INDIRECT_v2i64_S:
490
70
  case WebAssembly::CALL_INDIRECT_v4f32:
491
70
  case WebAssembly::CALL_INDIRECT_v4f32_S:
492
70
  case WebAssembly::CALL_INDIRECT_v2f64:
493
70
  case WebAssembly::CALL_INDIRECT_v2f64_S:
494
70
  case WebAssembly::CALL_INDIRECT_exnref:
495
70
  case WebAssembly::CALL_INDIRECT_exnref_S:
496
70
  case WebAssembly::RET_CALL_INDIRECT:
497
70
  case WebAssembly::RET_CALL_INDIRECT_S:
498
70
    return true;
499
429
  default:
500
429
    return false;
501
499
  }
502
499
}
503
504
/// Returns the operand number of a callee, assuming the argument is a call
505
/// instruction.
506
402
inline unsigned getCalleeOpNo(unsigned Opc) {
507
402
  switch (Opc) {
508
402
  case WebAssembly::CALL_VOID:
509
94
  case WebAssembly::CALL_VOID_S:
510
94
  case WebAssembly::CALL_INDIRECT_VOID:
511
94
  case WebAssembly::CALL_INDIRECT_VOID_S:
512
94
  case WebAssembly::RET_CALL:
513
94
  case WebAssembly::RET_CALL_S:
514
94
  case WebAssembly::RET_CALL_INDIRECT:
515
94
  case WebAssembly::RET_CALL_INDIRECT_S:
516
94
    return 0;
517
308
  case WebAssembly::CALL_i32:
518
308
  case WebAssembly::CALL_i32_S:
519
308
  case WebAssembly::CALL_i64:
520
308
  case WebAssembly::CALL_i64_S:
521
308
  case WebAssembly::CALL_f32:
522
308
  case WebAssembly::CALL_f32_S:
523
308
  case WebAssembly::CALL_f64:
524
308
  case WebAssembly::CALL_f64_S:
525
308
  case WebAssembly::CALL_v16i8:
526
308
  case WebAssembly::CALL_v16i8_S:
527
308
  case WebAssembly::CALL_v8i16:
528
308
  case WebAssembly::CALL_v8i16_S:
529
308
  case WebAssembly::CALL_v4i32:
530
308
  case WebAssembly::CALL_v4i32_S:
531
308
  case WebAssembly::CALL_v2i64:
532
308
  case WebAssembly::CALL_v2i64_S:
533
308
  case WebAssembly::CALL_v4f32:
534
308
  case WebAssembly::CALL_v4f32_S:
535
308
  case WebAssembly::CALL_v2f64:
536
308
  case WebAssembly::CALL_v2f64_S:
537
308
  case WebAssembly::CALL_exnref:
538
308
  case WebAssembly::CALL_exnref_S:
539
308
  case WebAssembly::CALL_INDIRECT_i32:
540
308
  case WebAssembly::CALL_INDIRECT_i32_S:
541
308
  case WebAssembly::CALL_INDIRECT_i64:
542
308
  case WebAssembly::CALL_INDIRECT_i64_S:
543
308
  case WebAssembly::CALL_INDIRECT_f32:
544
308
  case WebAssembly::CALL_INDIRECT_f32_S:
545
308
  case WebAssembly::CALL_INDIRECT_f64:
546
308
  case WebAssembly::CALL_INDIRECT_f64_S:
547
308
  case WebAssembly::CALL_INDIRECT_v16i8:
548
308
  case WebAssembly::CALL_INDIRECT_v16i8_S:
549
308
  case WebAssembly::CALL_INDIRECT_v8i16:
550
308
  case WebAssembly::CALL_INDIRECT_v8i16_S:
551
308
  case WebAssembly::CALL_INDIRECT_v4i32:
552
308
  case WebAssembly::CALL_INDIRECT_v4i32_S:
553
308
  case WebAssembly::CALL_INDIRECT_v2i64:
554
308
  case WebAssembly::CALL_INDIRECT_v2i64_S:
555
308
  case WebAssembly::CALL_INDIRECT_v4f32:
556
308
  case WebAssembly::CALL_INDIRECT_v4f32_S:
557
308
  case WebAssembly::CALL_INDIRECT_v2f64:
558
308
  case WebAssembly::CALL_INDIRECT_v2f64_S:
559
308
  case WebAssembly::CALL_INDIRECT_exnref:
560
308
  case WebAssembly::CALL_INDIRECT_exnref_S:
561
308
    return 1;
562
308
  default:
563
0
    llvm_unreachable("Not a call instruction");
564
402
  }
565
402
}
566
567
6
inline bool isMarker(unsigned Opc) {
568
6
  switch (Opc) {
569
6
  case WebAssembly::BLOCK:
570
2
  case WebAssembly::BLOCK_S:
571
2
  case WebAssembly::END_BLOCK:
572
2
  case WebAssembly::END_BLOCK_S:
573
2
  case WebAssembly::LOOP:
574
2
  case WebAssembly::LOOP_S:
575
2
  case WebAssembly::END_LOOP:
576
2
  case WebAssembly::END_LOOP_S:
577
2
  case WebAssembly::TRY:
578
2
  case WebAssembly::TRY_S:
579
2
  case WebAssembly::END_TRY:
580
2
  case WebAssembly::END_TRY_S:
581
2
    return true;
582
4
  default:
583
4
    return false;
584
6
  }
585
6
}
586
587
} // end namespace WebAssembly
588
} // end namespace llvm
589
590
#endif