Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp
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//===-- WebAssemblyRegisterInfo.cpp - WebAssembly Register Information ----===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file contains the WebAssembly implementation of the
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/// TargetRegisterInfo class.
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///
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//===----------------------------------------------------------------------===//
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#include "WebAssemblyRegisterInfo.h"
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#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
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#include "WebAssemblyFrameLowering.h"
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#include "WebAssemblyInstrInfo.h"
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#include "WebAssemblyMachineFunctionInfo.h"
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#include "WebAssemblySubtarget.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetFrameLowering.h"
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#include "llvm/IR/Function.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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#define DEBUG_TYPE "wasm-reg-info"
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#define GET_REGINFO_TARGET_DESC
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#include "WebAssemblyGenRegisterInfo.inc"
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WebAssemblyRegisterInfo::WebAssemblyRegisterInfo(const Triple &TT)
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    : WebAssemblyGenRegisterInfo(0), TT(TT) {}
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const MCPhysReg *
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WebAssemblyRegisterInfo::getCalleeSavedRegs(const MachineFunction *) const {
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  static const MCPhysReg CalleeSavedRegs[] = {0};
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  return CalleeSavedRegs;
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}
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BitVector
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WebAssemblyRegisterInfo::getReservedRegs(const MachineFunction & /*MF*/) const {
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  BitVector Reserved(getNumRegs());
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  for (auto Reg : {WebAssembly::SP32, WebAssembly::SP64, WebAssembly::FP32,
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                   WebAssembly::FP64})
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    Reserved.set(Reg);
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  return Reserved;
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}
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void WebAssemblyRegisterInfo::eliminateFrameIndex(
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    MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum,
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    RegScavenger * /*RS*/) const {
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  assert(SPAdj == 0);
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  MachineInstr &MI = *II;
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  MachineBasicBlock &MBB = *MI.getParent();
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  MachineFunction &MF = *MBB.getParent();
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  MachineRegisterInfo &MRI = MF.getRegInfo();
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  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
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  const MachineFrameInfo &MFI = MF.getFrameInfo();
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  int64_t FrameOffset = MFI.getStackSize() + MFI.getObjectOffset(FrameIndex);
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  assert(MFI.getObjectSize(FrameIndex) != 0 &&
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         "We assume that variable-sized objects have already been lowered, "
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         "and don't use FrameIndex operands.");
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  Register FrameRegister = getFrameRegister(MF);
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  // If this is the address operand of a load or store, make it relative to SP
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  // and fold the frame offset directly in.
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  unsigned AddrOperandNum = WebAssembly::getNamedOperandIdx(
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      MI.getOpcode(), WebAssembly::OpName::addr);
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  if (AddrOperandNum == FIOperandNum) {
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    unsigned OffsetOperandNum = WebAssembly::getNamedOperandIdx(
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        MI.getOpcode(), WebAssembly::OpName::off);
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    assert(FrameOffset >= 0 && MI.getOperand(OffsetOperandNum).getImm() >= 0);
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    int64_t Offset = MI.getOperand(OffsetOperandNum).getImm() + FrameOffset;
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    if (static_cast<uint64_t>(Offset) <= std::numeric_limits<uint32_t>::max()) {
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      MI.getOperand(OffsetOperandNum).setImm(Offset);
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      MI.getOperand(FIOperandNum)
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          .ChangeToRegister(FrameRegister, /*isDef=*/false);
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      return;
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    }
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  }
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  // If this is an address being added to a constant, fold the frame offset
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  // into the constant.
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  if (MI.getOpcode() == WebAssembly::ADD_I32) {
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    MachineOperand &OtherMO = MI.getOperand(3 - FIOperandNum);
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    if (OtherMO.isReg()) {
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      unsigned OtherMOReg = OtherMO.getReg();
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      if (TargetRegisterInfo::isVirtualRegister(OtherMOReg)) {
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        MachineInstr *Def = MF.getRegInfo().getUniqueVRegDef(OtherMOReg);
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        // TODO: For now we just opportunistically do this in the case where
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        // the CONST_I32 happens to have exactly one def and one use. We
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        // should generalize this to optimize in more cases.
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        if (Def && Def->getOpcode() == WebAssembly::CONST_I32 &&
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            MRI.hasOneNonDBGUse(Def->getOperand(0).getReg())) {
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          MachineOperand &ImmMO = Def->getOperand(1);
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          ImmMO.setImm(ImmMO.getImm() + uint32_t(FrameOffset));
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          MI.getOperand(FIOperandNum)
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              .ChangeToRegister(FrameRegister, /*isDef=*/false);
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          return;
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        }
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      }
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    }
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  }
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  // Otherwise create an i32.add SP, offset and make it the operand.
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  const auto *TII = MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo();
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  unsigned FIRegOperand = FrameRegister;
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  if (FrameOffset) {
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    // Create i32.add SP, offset and make it the operand.
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    const TargetRegisterClass *PtrRC =
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        MRI.getTargetRegisterInfo()->getPointerRegClass(MF);
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    unsigned OffsetOp = MRI.createVirtualRegister(PtrRC);
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    BuildMI(MBB, *II, II->getDebugLoc(), TII->get(WebAssembly::CONST_I32),
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            OffsetOp)
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        .addImm(FrameOffset);
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    FIRegOperand = MRI.createVirtualRegister(PtrRC);
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    BuildMI(MBB, *II, II->getDebugLoc(), TII->get(WebAssembly::ADD_I32),
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            FIRegOperand)
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        .addReg(FrameRegister)
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        .addReg(OffsetOp);
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  }
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  MI.getOperand(FIOperandNum).ChangeToRegister(FIRegOperand, /*isDef=*/false);
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}
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Register
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WebAssemblyRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
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  static const unsigned Regs[2][2] = {
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      /*            !isArch64Bit       isArch64Bit      */
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      /* !hasFP */ {WebAssembly::SP32, WebAssembly::SP64},
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      /*  hasFP */ {WebAssembly::FP32, WebAssembly::FP64}};
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  const WebAssemblyFrameLowering *TFI = getFrameLowering(MF);
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  return Regs[TFI->hasFP(MF)][TT.isArch64Bit()];
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}
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const TargetRegisterClass *
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WebAssemblyRegisterInfo::getPointerRegClass(const MachineFunction &MF,
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                                            unsigned Kind) const {
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  assert(Kind == 0 && "Only one kind of pointer on WebAssembly");
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  if (MF.getSubtarget<WebAssemblySubtarget>().hasAddr64())
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    return &WebAssembly::I64RegClass;
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  return &WebAssembly::I32RegClass;
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}