Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp
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//===-- WebAssemblyTargetTransformInfo.cpp - WebAssembly-specific TTI -----===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file defines the WebAssembly-specific TargetTransformInfo
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/// implementation.
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///
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//===----------------------------------------------------------------------===//
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#include "WebAssemblyTargetTransformInfo.h"
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#include "llvm/CodeGen/CostTable.h"
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#include "llvm/Support/Debug.h"
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using namespace llvm;
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#define DEBUG_TYPE "wasmtti"
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TargetTransformInfo::PopcntSupportKind
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WebAssemblyTTIImpl::getPopcntSupport(unsigned TyWidth) const {
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  assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
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  return TargetTransformInfo::PSK_FastHardware;
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}
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unsigned WebAssemblyTTIImpl::getNumberOfRegisters(bool Vector) {
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  unsigned Result = BaseT::getNumberOfRegisters(Vector);
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  // For SIMD, use at least 16 registers, as a rough guess.
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  if (Vector)
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    Result = std::max(Result, 16u);
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  return Result;
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}
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unsigned WebAssemblyTTIImpl::getRegisterBitWidth(bool Vector) const {
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  if (Vector && getST()->hasSIMD128())
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    return 128;
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  return 64;
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}
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unsigned WebAssemblyTTIImpl::getArithmeticInstrCost(
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    unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info,
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    TTI::OperandValueKind Opd2Info, TTI::OperandValueProperties Opd1PropInfo,
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    TTI::OperandValueProperties Opd2PropInfo, ArrayRef<const Value *> Args) {
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  unsigned Cost = BasicTTIImplBase<WebAssemblyTTIImpl>::getArithmeticInstrCost(
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      Opcode, Ty, Opd1Info, Opd2Info, Opd1PropInfo, Opd2PropInfo);
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0
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  if (auto *VTy = dyn_cast<VectorType>(Ty)) {
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    switch (Opcode) {
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    case Instruction::LShr:
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    case Instruction::AShr:
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    case Instruction::Shl:
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      // SIMD128's shifts currently only accept a scalar shift count. For each
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      // element, we'll need to extract, op, insert. The following is a rough
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      // approxmation.
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      if (Opd2Info != TTI::OK_UniformValue &&
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          Opd2Info != TTI::OK_UniformConstantValue)
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        Cost = VTy->getNumElements() *
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               (TargetTransformInfo::TCC_Basic +
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                getArithmeticInstrCost(Opcode, VTy->getElementType()) +
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                TargetTransformInfo::TCC_Basic);
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      break;
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    }
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  }
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  return Cost;
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}
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unsigned WebAssemblyTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val,
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                                                unsigned Index) {
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  unsigned Cost = BasicTTIImplBase::getVectorInstrCost(Opcode, Val, Index);
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  // SIMD128's insert/extract currently only take constant indices.
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  if (Index == -1u)
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    return Cost + 25 * TargetTransformInfo::TCC_Expensive;
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  return Cost;
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}