Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/X86/AsmParser/X86Operand.h
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Source (jump to first uncovered line)
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//===- X86Operand.h - Parsed X86 machine instruction ------------*- C++ -*-===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
8
9
#ifndef LLVM_LIB_TARGET_X86_ASMPARSER_X86OPERAND_H
10
#define LLVM_LIB_TARGET_X86_ASMPARSER_X86OPERAND_H
11
12
#include "MCTargetDesc/X86IntelInstPrinter.h"
13
#include "MCTargetDesc/X86MCTargetDesc.h"
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#include "X86AsmParserCommon.h"
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#include "llvm/ADT/STLExtras.h"
16
#include "llvm/ADT/StringRef.h"
17
#include "llvm/MC/MCExpr.h"
18
#include "llvm/MC/MCInst.h"
19
#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
20
#include "llvm/MC/MCRegisterInfo.h"
21
#include "llvm/Support/Casting.h"
22
#include "llvm/Support/ErrorHandling.h"
23
#include "llvm/Support/SMLoc.h"
24
#include <cassert>
25
#include <memory>
26
27
namespace llvm {
28
29
/// X86Operand - Instances of this class represent a parsed X86 machine
30
/// instruction.
31
struct X86Operand final : public MCParsedAsmOperand {
32
  enum KindTy { Token, Register, Immediate, Memory, Prefix, DXRegister } Kind;
33
34
  SMLoc StartLoc, EndLoc;
35
  SMLoc OffsetOfLoc;
36
  StringRef SymName;
37
  void *OpDecl;
38
  bool AddressOf;
39
40
  struct TokOp {
41
    const char *Data;
42
    unsigned Length;
43
  };
44
45
  struct RegOp {
46
    unsigned RegNo;
47
  };
48
49
  struct PrefOp {
50
    unsigned Prefixes;
51
  };
52
53
  struct ImmOp {
54
    const MCExpr *Val;
55
  };
56
57
  struct MemOp {
58
    unsigned SegReg;
59
    const MCExpr *Disp;
60
    unsigned BaseReg;
61
    unsigned IndexReg;
62
    unsigned Scale;
63
    unsigned Size;
64
    unsigned ModeSize;
65
66
    /// If the memory operand is unsized and there are multiple instruction
67
    /// matches, prefer the one with this size.
68
    unsigned FrontendSize;
69
  };
70
71
  union {
72
    struct TokOp Tok;
73
    struct RegOp Reg;
74
    struct ImmOp Imm;
75
    struct MemOp Mem;
76
    struct PrefOp Pref;
77
  };
78
79
  X86Operand(KindTy K, SMLoc Start, SMLoc End)
80
585k
      : Kind(K), StartLoc(Start), EndLoc(End) {}
81
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213
  StringRef getSymName() override { return SymName; }
83
150
  void *getOpDecl() override { return OpDecl; }
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85
  /// getStartLoc - Get the location of the first token of this operand.
86
175
  SMLoc getStartLoc() const override { return StartLoc; }
87
88
  /// getEndLoc - Get the location of the last token of this operand.
89
2.45k
  SMLoc getEndLoc() const override { return EndLoc; }
90
91
  /// getLocRange - Get the range between the first and last token of this
92
  /// operand.
93
53
  SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
94
95
  /// getOffsetOfLoc - Get the location of the offset operator.
96
0
  SMLoc getOffsetOfLoc() const override { return OffsetOfLoc; }
97
98
0
  void print(raw_ostream &OS) const override {
99
0
100
0
    auto PrintImmValue = [&](const MCExpr *Val, const char *VName) {
101
0
      if (Val->getKind() == MCExpr::Constant) {
102
0
        if (auto Imm = cast<MCConstantExpr>(Val)->getValue())
103
0
          OS << VName << Imm;
104
0
      } else if (Val->getKind() == MCExpr::SymbolRef) {
105
0
        if (auto *SRE = dyn_cast<MCSymbolRefExpr>(Val)) {
106
0
          const MCSymbol &Sym = SRE->getSymbol();
107
0
          if (auto SymName = Sym.getName().data())
108
0
            OS << VName << SymName;
109
0
        }
110
0
      }
111
0
    };
112
0
113
0
    switch (Kind) {
114
0
    case Token:
115
0
      OS << Tok.Data;
116
0
      break;
117
0
    case Register:
118
0
      OS << "Reg:" << X86IntelInstPrinter::getRegisterName(Reg.RegNo);
119
0
      break;
120
0
    case DXRegister:
121
0
      OS << "DXReg";
122
0
      break;
123
0
    case Immediate:
124
0
      PrintImmValue(Imm.Val, "Imm:");
125
0
      break;
126
0
    case Prefix:
127
0
      OS << "Prefix:" << Pref.Prefixes;
128
0
      break;
129
0
    case Memory:
130
0
      OS << "Memory: ModeSize=" << Mem.ModeSize;
131
0
      if (Mem.Size)
132
0
        OS << ",Size=" << Mem.Size;
133
0
      if (Mem.BaseReg)
134
0
        OS << ",BaseReg=" << X86IntelInstPrinter::getRegisterName(Mem.BaseReg);
135
0
      if (Mem.IndexReg)
136
0
        OS << ",IndexReg="
137
0
           << X86IntelInstPrinter::getRegisterName(Mem.IndexReg);
138
0
      if (Mem.Scale)
139
0
        OS << ",Scale=" << Mem.Scale;
140
0
      if (Mem.Disp)
141
0
        PrintImmValue(Mem.Disp, ",Disp=");
142
0
      if (Mem.SegReg)
143
0
        OS << ",SegReg=" << X86IntelInstPrinter::getRegisterName(Mem.SegReg);
144
0
      break;
145
0
    }
146
0
  }
147
148
492k
  StringRef getToken() const {
149
492k
    assert(Kind == Token && "Invalid access!");
150
492k
    return StringRef(Tok.Data, Tok.Length);
151
492k
  }
152
15.5k
  void setTokenValue(StringRef Value) {
153
15.5k
    assert(Kind == Token && "Invalid access!");
154
15.5k
    Tok.Data = Value.data();
155
15.5k
    Tok.Length = Value.size();
156
15.5k
  }
157
158
994k
  unsigned getReg() const override {
159
994k
    assert(Kind == Register && "Invalid access!");
160
994k
    return Reg.RegNo;
161
994k
  }
162
163
184
  unsigned getPrefix() const {
164
184
    assert(Kind == Prefix && "Invalid access!");
165
184
    return Pref.Prefixes;
166
184
  }
167
168
140k
  const MCExpr *getImm() const {
169
140k
    assert(Kind == Immediate && "Invalid access!");
170
140k
    return Imm.Val;
171
140k
  }
172
173
94.9k
  const MCExpr *getMemDisp() const {
174
94.9k
    assert(Kind == Memory && "Invalid access!");
175
94.9k
    return Mem.Disp;
176
94.9k
  }
177
92.9k
  unsigned getMemSegReg() const {
178
92.9k
    assert(Kind == Memory && "Invalid access!");
179
92.9k
    return Mem.SegReg;
180
92.9k
  }
181
105k
  unsigned getMemBaseReg() const {
182
105k
    assert(Kind == Memory && "Invalid access!");
183
105k
    return Mem.BaseReg;
184
105k
  }
185
94.0k
  unsigned getMemIndexReg() const {
186
94.0k
    assert(Kind == Memory && "Invalid access!");
187
94.0k
    return Mem.IndexReg;
188
94.0k
  }
189
93.4k
  unsigned getMemScale() const {
190
93.4k
    assert(Kind == Memory && "Invalid access!");
191
93.4k
    return Mem.Scale;
192
93.4k
  }
193
0
  unsigned getMemModeSize() const {
194
0
    assert(Kind == Memory && "Invalid access!");
195
0
    return Mem.ModeSize;
196
0
  }
197
35
  unsigned getMemFrontendSize() const {
198
35
    assert(Kind == Memory && "Invalid access!");
199
35
    return Mem.FrontendSize;
200
35
  }
201
202
1.89M
  bool isToken() const override {return Kind == Token; }
203
204
175k
  bool isImm() const override { return Kind == Immediate; }
205
206
3.86k
  bool isImmSExti16i8() const {
207
3.86k
    if (!isImm())
208
1.31k
      return false;
209
2.54k
210
2.54k
    // If this isn't a constant expr, just assume it fits and let relaxation
211
2.54k
    // handle it.
212
2.54k
    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
213
2.54k
    if (!CE)
214
147
      return true;
215
2.40k
216
2.40k
    // Otherwise, check the value is in a range that makes sense for this
217
2.40k
    // extension.
218
2.40k
    return isImmSExti16i8Value(CE->getValue());
219
2.40k
  }
220
4.26k
  bool isImmSExti32i8() const {
221
4.26k
    if (!isImm())
222
1.03k
      return false;
223
3.22k
224
3.22k
    // If this isn't a constant expr, just assume it fits and let relaxation
225
3.22k
    // handle it.
226
3.22k
    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
227
3.22k
    if (!CE)
228
160
      return true;
229
3.06k
230
3.06k
    // Otherwise, check the value is in a range that makes sense for this
231
3.06k
    // extension.
232
3.06k
    return isImmSExti32i8Value(CE->getValue());
233
3.06k
  }
234
3.92k
  bool isImmSExti64i8() const {
235
3.92k
    if (!isImm())
236
1.31k
      return false;
237
2.60k
238
2.60k
    // If this isn't a constant expr, just assume it fits and let relaxation
239
2.60k
    // handle it.
240
2.60k
    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
241
2.60k
    if (!CE)
242
148
      return true;
243
2.46k
244
2.46k
    // Otherwise, check the value is in a range that makes sense for this
245
2.46k
    // extension.
246
2.46k
    return isImmSExti64i8Value(CE->getValue());
247
2.46k
  }
248
3.79k
  bool isImmSExti64i32() const {
249
3.79k
    if (!isImm())
250
2.47k
      return false;
251
1.31k
252
1.31k
    // If this isn't a constant expr, just assume it fits and let relaxation
253
1.31k
    // handle it.
254
1.31k
    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
255
1.31k
    if (!CE)
256
104
      return true;
257
1.21k
258
1.21k
    // Otherwise, check the value is in a range that makes sense for this
259
1.21k
    // extension.
260
1.21k
    return isImmSExti64i32Value(CE->getValue());
261
1.21k
  }
262
263
123k
  bool isImmUnsignedi8() const {
264
123k
    if (!isImm()) 
return false21.5k
;
265
101k
    // If this isn't a constant expr, just assume it fits and let relaxation
266
101k
    // handle it.
267
101k
    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
268
101k
    if (!CE) 
return true4
;
269
101k
    return isImmUnsignedi8Value(CE->getValue());
270
101k
  }
271
272
0
  bool isOffsetOf() const override {
273
0
    return OffsetOfLoc.getPointer();
274
0
  }
275
276
477
  bool needAddressOf() const override {
277
477
    return AddressOf;
278
477
  }
279
280
8.98k
  bool isMem() const override { return Kind == Memory; }
281
50.6k
  bool isMemUnsized() const {
282
50.6k
    return Kind == Memory && 
Mem.Size == 07.95k
;
283
50.6k
  }
284
14.1k
  bool isMem8() const {
285
14.1k
    return Kind == Memory && 
(5.92k
!Mem.Size5.92k
||
Mem.Size == 82.21k
);
286
14.1k
  }
287
17.7k
  bool isMem16() const {
288
17.7k
    return Kind == Memory && 
(8.18k
!Mem.Size8.18k
||
Mem.Size == 163.93k
);
289
17.7k
  }
290
64.5k
  bool isMem32() const {
291
64.5k
    return Kind == Memory && 
(49.7k
!Mem.Size49.7k
||
Mem.Size == 325.49k
);
292
64.5k
  }
293
74.0k
  bool isMem64() const {
294
74.0k
    return Kind == Memory && 
(54.0k
!Mem.Size54.0k
||
Mem.Size == 644.14k
);
295
74.0k
  }
296
138
  bool isMem80() const {
297
138
    return Kind == Memory && (!Mem.Size || 
Mem.Size == 8010
);
298
138
  }
299
107k
  bool isMem128() const {
300
107k
    return Kind == Memory && 
(90.1k
!Mem.Size90.1k
||
Mem.Size == 1281.27k
);
301
107k
  }
302
76.2k
  bool isMem256() const {
303
76.2k
    return Kind == Memory && 
(62.7k
!Mem.Size62.7k
||
Mem.Size == 256973
);
304
76.2k
  }
305
52.5k
  bool isMem512() const {
306
52.5k
    return Kind == Memory && 
(42.2k
!Mem.Size42.2k
||
Mem.Size == 5124.42k
);
307
52.5k
  }
308
954
  bool isMemIndexReg(unsigned LowR, unsigned HighR) const {
309
954
    assert(Kind == Memory && "Invalid access!");
310
954
    return Mem.IndexReg >= LowR && 
Mem.IndexReg <= HighR916
;
311
954
  }
312
313
16
  bool isMem64_RC128() const {
314
16
    return isMem64() && isMemIndexReg(X86::XMM0, X86::XMM15);
315
16
  }
316
50
  bool isMem128_RC128() const {
317
50
    return isMem128() && isMemIndexReg(X86::XMM0, X86::XMM15);
318
50
  }
319
32
  bool isMem128_RC256() const {
320
32
    return isMem128() && 
isMemIndexReg(X86::YMM0, X86::YMM15)30
;
321
32
  }
322
32
  bool isMem256_RC128() const {
323
32
    return isMem256() && 
isMemIndexReg(X86::XMM0, X86::XMM15)18
;
324
32
  }
325
32
  bool isMem256_RC256() const {
326
32
    return isMem256() && isMemIndexReg(X86::YMM0, X86::YMM15);
327
32
  }
328
329
46
  bool isMem64_RC128X() const {
330
46
    return isMem64() && isMemIndexReg(X86::XMM0, X86::XMM31);
331
46
  }
332
308
  bool isMem128_RC128X() const {
333
308
    return isMem128() && 
isMemIndexReg(X86::XMM0, X86::XMM31)212
;
334
308
  }
335
127
  bool isMem128_RC256X() const {
336
127
    return isMem128() && 
isMemIndexReg(X86::YMM0, X86::YMM31)83
;
337
127
  }
338
81
  bool isMem256_RC128X() const {
339
81
    return isMem256() && 
isMemIndexReg(X86::XMM0, X86::XMM31)65
;
340
81
  }
341
161
  bool isMem256_RC256X() const {
342
161
    return isMem256() && 
isMemIndexReg(X86::YMM0, X86::YMM31)129
;
343
161
  }
344
89
  bool isMem256_RC512() const {
345
89
    return isMem256() && 
isMemIndexReg(X86::ZMM0, X86::ZMM31)73
;
346
89
  }
347
67
  bool isMem512_RC256X() const {
348
67
    return isMem512() && isMemIndexReg(X86::YMM0, X86::YMM31);
349
67
  }
350
133
  bool isMem512_RC512() const {
351
133
    return isMem512() && isMemIndexReg(X86::ZMM0, X86::ZMM31);
352
133
  }
353
354
1.54k
  bool isAbsMem() const {
355
1.54k
    return Kind == Memory && 
!getMemSegReg()1.39k
&&
!getMemBaseReg()1.39k
&&
356
1.54k
      
!getMemIndexReg()1.31k
&&
getMemScale() == 11.31k
;
357
1.54k
  }
358
18.0k
  bool isAVX512RC() const{
359
18.0k
      return isImm();
360
18.0k
  }
361
362
2
  bool isAbsMem16() const {
363
2
    return isAbsMem() && Mem.ModeSize == 16;
364
2
  }
365
366
600
  bool isSrcIdx() const {
367
600
    return !getMemIndexReg() && getMemScale() == 1 &&
368
600
      (getMemBaseReg() == X86::RSI || 
getMemBaseReg() == X86::ESI239
||
369
600
       
getMemBaseReg() == X86::SI68
) &&
isa<MCConstantExpr>(getMemDisp())588
&&
370
600
      
cast<MCConstantExpr>(getMemDisp())->getValue() == 0588
;
371
600
  }
372
218
  bool isSrcIdx8() const {
373
218
    return isMem8() && 
isSrcIdx()183
;
374
218
  }
375
177
  bool isSrcIdx16() const {
376
177
    return isMem16() && 
isSrcIdx()169
;
377
177
  }
378
187
  bool isSrcIdx32() const {
379
187
    return isMem32() && 
isSrcIdx()180
;
380
187
  }
381
68
  bool isSrcIdx64() const {
382
68
    return isMem64() && isSrcIdx();
383
68
  }
384
385
610
  bool isDstIdx() const {
386
610
    return !getMemIndexReg() && getMemScale() == 1 &&
387
610
      (getMemSegReg() == 0 || 
getMemSegReg() == X86::ES270
) &&
388
610
      
(607
getMemBaseReg() == X86::RDI607
||
getMemBaseReg() == X86::EDI214
||
389
607
       
getMemBaseReg() == X86::DI33
) && isa<MCConstantExpr>(getMemDisp()) &&
390
610
      
cast<MCConstantExpr>(getMemDisp())->getValue() == 0607
;
391
610
  }
392
200
  bool isDstIdx8() const {
393
200
    return isMem8() && 
isDstIdx()177
;
394
200
  }
395
192
  bool isDstIdx16() const {
396
192
    return isMem16() && 
isDstIdx()172
;
397
192
  }
398
202
  bool isDstIdx32() const {
399
202
    return isMem32() && 
isDstIdx()175
;
400
202
  }
401
88
  bool isDstIdx64() const {
402
88
    return isMem64() && 
isDstIdx()86
;
403
88
  }
404
405
19.6k
  bool isMemOffs() const {
406
19.6k
    return Kind == Memory && 
!getMemBaseReg()11.6k
&&
!getMemIndexReg()1.44k
&&
407
19.6k
      
getMemScale() == 1837
;
408
19.6k
  }
409
410
2.27k
  bool isMemOffs16_8() const {
411
2.27k
    return isMemOffs() && 
Mem.ModeSize == 1658
&&
(1
!Mem.Size1
||
Mem.Size == 80
);
412
2.27k
  }
413
2.25k
  bool isMemOffs16_16() const {
414
2.25k
    return isMemOffs() && 
Mem.ModeSize == 1659
&&
(1
!Mem.Size1
||
Mem.Size == 160
);
415
2.25k
  }
416
3.96k
  bool isMemOffs16_32() const {
417
3.96k
    return isMemOffs() && 
Mem.ModeSize == 16238
&&
(2
!Mem.Size2
||
Mem.Size == 320
);
418
3.96k
  }
419
2.27k
  bool isMemOffs32_8() const {
420
2.27k
    return isMemOffs() && 
Mem.ModeSize == 3257
&&
(6
!Mem.Size6
||
Mem.Size == 80
);
421
2.27k
  }
422
2.25k
  bool isMemOffs32_16() const {
423
2.25k
    return isMemOffs() && 
Mem.ModeSize == 3258
&&
(6
!Mem.Size6
||
Mem.Size == 160
);
424
2.25k
  }
425
3.96k
  bool isMemOffs32_32() const {
426
3.96k
    return isMemOffs() && 
Mem.ModeSize == 32236
&&
(86
!Mem.Size86
||
Mem.Size == 3211
);
427
3.96k
  }
428
2.57k
  bool isMemOffs32_64() const {
429
2.57k
    return isMemOffs() && 
Mem.ModeSize == 32113
&&
(13
!Mem.Size13
||
Mem.Size == 640
);
430
2.57k
  }
431
10
  bool isMemOffs64_8() const {
432
10
    return isMemOffs() && 
Mem.ModeSize == 644
&&
(4
!Mem.Size4
||
Mem.Size == 80
);
433
10
  }
434
10
  bool isMemOffs64_16() const {
435
10
    return isMemOffs() && 
Mem.ModeSize == 644
&&
(4
!Mem.Size4
||
Mem.Size == 160
);
436
10
  }
437
10
  bool isMemOffs64_32() const {
438
10
    return isMemOffs() && 
Mem.ModeSize == 644
&&
(4
!Mem.Size4
||
Mem.Size == 320
);
439
10
  }
440
6
  bool isMemOffs64_64() const {
441
6
    return isMemOffs() && Mem.ModeSize == 64 && (!Mem.Size || 
Mem.Size == 640
);
442
6
  }
443
444
146k
  bool isPrefix() const { return Kind == Prefix; }
445
1.34M
  bool isReg() const override { return Kind == Register; }
446
330
  bool isDXReg() const { return Kind == DXRegister; }
447
448
823
  bool isGR32orGR64() const {
449
823
    return Kind == Register &&
450
823
      
(390
X86MCRegisterClasses[X86::GR32RegClassID].contains(getReg())390
||
451
390
      
X86MCRegisterClasses[X86::GR64RegClassID].contains(getReg())200
);
452
823
  }
453
454
0
  bool isVK1Pair() const {
455
0
    return Kind == Register &&
456
0
      X86MCRegisterClasses[X86::VK1RegClassID].contains(getReg());
457
0
  }
458
459
126
  bool isVK2Pair() const {
460
126
    return Kind == Register &&
461
126
      X86MCRegisterClasses[X86::VK2RegClassID].contains(getReg());
462
126
  }
463
464
206
  bool isVK4Pair() const {
465
206
    return Kind == Register &&
466
206
      X86MCRegisterClasses[X86::VK4RegClassID].contains(getReg());
467
206
  }
468
469
146
  bool isVK8Pair() const {
470
146
    return Kind == Register &&
471
146
      X86MCRegisterClasses[X86::VK8RegClassID].contains(getReg());
472
146
  }
473
474
110
  bool isVK16Pair() const {
475
110
    return Kind == Register &&
476
110
      X86MCRegisterClasses[X86::VK16RegClassID].contains(getReg());
477
110
  }
478
479
117k
  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
480
117k
    // Add as immediates when possible.
481
117k
    if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
482
115k
      Inst.addOperand(MCOperand::createImm(CE->getValue()));
483
1.29k
    else
484
1.29k
      Inst.addOperand(MCOperand::createExpr(Expr));
485
117k
  }
486
487
244k
  void addRegOperands(MCInst &Inst, unsigned N) const {
488
244k
    assert(N == 1 && "Invalid number of operands!");
489
244k
    Inst.addOperand(MCOperand::createReg(getReg()));
490
244k
  }
491
492
363
  void addGR32orGR64Operands(MCInst &Inst, unsigned N) const {
493
363
    assert(N == 1 && "Invalid number of operands!");
494
363
    unsigned RegNo = getReg();
495
363
    if (X86MCRegisterClasses[X86::GR64RegClassID].contains(RegNo))
496
187
      RegNo = getX86SubSuperRegister(RegNo, 32);
497
363
    Inst.addOperand(MCOperand::createReg(RegNo));
498
363
  }
499
500
4.28k
  void addAVX512RCOperands(MCInst &Inst, unsigned N) const {
501
4.28k
    assert(N == 1 && "Invalid number of operands!");
502
4.28k
    addExpr(Inst, getImm());
503
4.28k
  }
504
505
22.8k
  void addImmOperands(MCInst &Inst, unsigned N) const {
506
22.8k
    assert(N == 1 && "Invalid number of operands!");
507
22.8k
    addExpr(Inst, getImm());
508
22.8k
  }
509
510
252
  void addMaskPairOperands(MCInst &Inst, unsigned N) const {
511
252
    assert(N == 1 && "Invalid number of operands!");
512
252
    unsigned Reg = getReg();
513
252
    switch (Reg) {
514
252
    case X86::K0:
515
58
    case X86::K1:
516
58
      Reg = X86::K0_K1;
517
58
      break;
518
58
    case X86::K2:
519
0
    case X86::K3:
520
0
      Reg = X86::K2_K3;
521
0
      break;
522
28
    case X86::K4:
523
28
    case X86::K5:
524
28
      Reg = X86::K4_K5;
525
28
      break;
526
166
    case X86::K6:
527
166
    case X86::K7:
528
166
      Reg = X86::K6_K7;
529
166
      break;
530
252
    }
531
252
    Inst.addOperand(MCOperand::createReg(Reg));
532
252
  }
533
534
90.0k
  void addMemOperands(MCInst &Inst, unsigned N) const {
535
90.0k
    assert((N == 5) && "Invalid number of operands!");
536
90.0k
    Inst.addOperand(MCOperand::createReg(getMemBaseReg()));
537
90.0k
    Inst.addOperand(MCOperand::createImm(getMemScale()));
538
90.0k
    Inst.addOperand(MCOperand::createReg(getMemIndexReg()));
539
90.0k
    addExpr(Inst, getMemDisp());
540
90.0k
    Inst.addOperand(MCOperand::createReg(getMemSegReg()));
541
90.0k
  }
542
543
1.29k
  void addAbsMemOperands(MCInst &Inst, unsigned N) const {
544
1.29k
    assert((N == 1) && "Invalid number of operands!");
545
1.29k
    // Add as immediates when possible.
546
1.29k
    if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemDisp()))
547
189
      Inst.addOperand(MCOperand::createImm(CE->getValue()));
548
1.10k
    else
549
1.10k
      Inst.addOperand(MCOperand::createExpr(getMemDisp()));
550
1.29k
  }
551
552
514
  void addSrcIdxOperands(MCInst &Inst, unsigned N) const {
553
514
    assert((N == 2) && "Invalid number of operands!");
554
514
    Inst.addOperand(MCOperand::createReg(getMemBaseReg()));
555
514
    Inst.addOperand(MCOperand::createReg(getMemSegReg()));
556
514
  }
557
558
565
  void addDstIdxOperands(MCInst &Inst, unsigned N) const {
559
565
    assert((N == 1) && "Invalid number of operands!");
560
565
    Inst.addOperand(MCOperand::createReg(getMemBaseReg()));
561
565
  }
562
563
83
  void addMemOffsOperands(MCInst &Inst, unsigned N) const {
564
83
    assert((N == 2) && "Invalid number of operands!");
565
83
    // Add as immediates when possible.
566
83
    if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemDisp()))
567
47
      Inst.addOperand(MCOperand::createImm(CE->getValue()));
568
36
    else
569
36
      Inst.addOperand(MCOperand::createExpr(getMemDisp()));
570
83
    Inst.addOperand(MCOperand::createReg(getMemSegReg()));
571
83
  }
572
573
218k
  static std::unique_ptr<X86Operand> CreateToken(StringRef Str, SMLoc Loc) {
574
218k
    SMLoc EndLoc = SMLoc::getFromPointer(Loc.getPointer() + Str.size());
575
218k
    auto Res = llvm::make_unique<X86Operand>(Token, Loc, EndLoc);
576
218k
    Res->Tok.Data = Str.data();
577
218k
    Res->Tok.Length = Str.size();
578
218k
    return Res;
579
218k
  }
580
581
  static std::unique_ptr<X86Operand>
582
  CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc,
583
            bool AddressOf = false, SMLoc OffsetOfLoc = SMLoc(),
584
247k
            StringRef SymName = StringRef(), void *OpDecl = nullptr) {
585
247k
    auto Res = llvm::make_unique<X86Operand>(Register, StartLoc, EndLoc);
586
247k
    Res->Reg.RegNo = RegNo;
587
247k
    Res->AddressOf = AddressOf;
588
247k
    Res->OffsetOfLoc = OffsetOfLoc;
589
247k
    Res->SymName = SymName;
590
247k
    Res->OpDecl = OpDecl;
591
247k
    return Res;
592
247k
  }
593
594
  static std::unique_ptr<X86Operand>
595
38
  CreateDXReg(SMLoc StartLoc, SMLoc EndLoc) {
596
38
    return llvm::make_unique<X86Operand>(DXRegister, StartLoc, EndLoc);
597
38
  }
598
599
  static std::unique_ptr<X86Operand>
600
184
  CreatePrefix(unsigned Prefixes, SMLoc StartLoc, SMLoc EndLoc) {
601
184
    auto Res = llvm::make_unique<X86Operand>(Prefix, StartLoc, EndLoc);
602
184
    Res->Pref.Prefixes = Prefixes;
603
184
    return Res;
604
184
  }
605
606
  static std::unique_ptr<X86Operand> CreateImm(const MCExpr *Val,
607
27.2k
                                               SMLoc StartLoc, SMLoc EndLoc) {
608
27.2k
    auto Res = llvm::make_unique<X86Operand>(Immediate, StartLoc, EndLoc);
609
27.2k
    Res->Imm.Val = Val;
610
27.2k
    return Res;
611
27.2k
  }
612
613
  /// Create an absolute memory operand.
614
  static std::unique_ptr<X86Operand>
615
  CreateMem(unsigned ModeSize, const MCExpr *Disp, SMLoc StartLoc, SMLoc EndLoc,
616
            unsigned Size = 0, StringRef SymName = StringRef(),
617
11.6k
            void *OpDecl = nullptr, unsigned FrontendSize = 0) {
618
11.6k
    auto Res = llvm::make_unique<X86Operand>(Memory, StartLoc, EndLoc);
619
11.6k
    Res->Mem.SegReg   = 0;
620
11.6k
    Res->Mem.Disp     = Disp;
621
11.6k
    Res->Mem.BaseReg  = 0;
622
11.6k
    Res->Mem.IndexReg = 0;
623
11.6k
    Res->Mem.Scale    = 1;
624
11.6k
    Res->Mem.Size     = Size;
625
11.6k
    Res->Mem.ModeSize = ModeSize;
626
11.6k
    Res->Mem.FrontendSize = FrontendSize;
627
11.6k
    Res->SymName      = SymName;
628
11.6k
    Res->OpDecl       = OpDecl;
629
11.6k
    Res->AddressOf    = false;
630
11.6k
    return Res;
631
11.6k
  }
632
633
  /// Create a generalized memory operand.
634
  static std::unique_ptr<X86Operand>
635
  CreateMem(unsigned ModeSize, unsigned SegReg, const MCExpr *Disp,
636
            unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc StartLoc,
637
            SMLoc EndLoc, unsigned Size = 0, StringRef SymName = StringRef(),
638
81.0k
            void *OpDecl = nullptr, unsigned FrontendSize = 0) {
639
81.0k
    // We should never just have a displacement, that should be parsed as an
640
81.0k
    // absolute memory operand.
641
81.0k
    assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
642
81.0k
643
81.0k
    // The scale should always be one of {1,2,4,8}.
644
81.0k
    assert(((Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8)) &&
645
81.0k
           "Invalid scale!");
646
81.0k
    auto Res = llvm::make_unique<X86Operand>(Memory, StartLoc, EndLoc);
647
81.0k
    Res->Mem.SegReg   = SegReg;
648
81.0k
    Res->Mem.Disp     = Disp;
649
81.0k
    Res->Mem.BaseReg  = BaseReg;
650
81.0k
    Res->Mem.IndexReg = IndexReg;
651
81.0k
    Res->Mem.Scale    = Scale;
652
81.0k
    Res->Mem.Size     = Size;
653
81.0k
    Res->Mem.ModeSize = ModeSize;
654
81.0k
    Res->Mem.FrontendSize = FrontendSize;
655
81.0k
    Res->SymName      = SymName;
656
81.0k
    Res->OpDecl       = OpDecl;
657
81.0k
    Res->AddressOf    = false;
658
81.0k
    return Res;
659
81.0k
  }
660
};
661
662
} // end namespace llvm
663
664
#endif // LLVM_LIB_TARGET_X86_ASMPARSER_X86OPERAND_H