Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp
Line
Count
Source (jump to first uncovered line)
1
//===-- X86IntelInstPrinter.cpp - Intel assembly instruction printing -----===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file includes code for rendering MCInst instances as Intel-style
10
// assembly.
11
//
12
//===----------------------------------------------------------------------===//
13
14
#include "X86IntelInstPrinter.h"
15
#include "X86BaseInfo.h"
16
#include "X86InstComments.h"
17
#include "llvm/MC/MCExpr.h"
18
#include "llvm/MC/MCInst.h"
19
#include "llvm/MC/MCInstrDesc.h"
20
#include "llvm/MC/MCInstrInfo.h"
21
#include "llvm/MC/MCSubtargetInfo.h"
22
#include "llvm/Support/Casting.h"
23
#include "llvm/Support/ErrorHandling.h"
24
#include <cassert>
25
#include <cstdint>
26
27
using namespace llvm;
28
29
#define DEBUG_TYPE "asm-printer"
30
31
// Include the auto-generated portion of the assembly writer.
32
#define PRINT_ALIAS_INSTR
33
#include "X86GenAsmWriter1.inc"
34
35
34.1k
void X86IntelInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
36
34.1k
  OS << getRegisterName(RegNo);
37
34.1k
}
38
39
void X86IntelInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
40
                                    StringRef Annot,
41
13.5k
                                    const MCSubtargetInfo &STI) {
42
13.5k
  printInstFlags(MI, OS);
43
13.5k
44
13.5k
  // In 16-bit mode, print data16 as data32.
45
13.5k
  if (MI->getOpcode() == X86::DATA16_PREFIX &&
46
13.5k
      
STI.getFeatureBits()[X86::Mode16Bit]0
) {
47
0
    OS << "\tdata32";
48
13.5k
  } else if (!printAliasInstr(MI, OS) &&
49
13.5k
             
!printVecCompareInstr(MI, OS)13.5k
)
50
13.5k
    printInstruction(MI, OS);
51
13.5k
52
13.5k
  // Next always print the annotation.
53
13.5k
  printAnnotation(OS, Annot);
54
13.5k
55
13.5k
  // If verbose assembly is enabled, we can print some informative comments.
56
13.5k
  if (CommentStream)
57
13.5k
    EmitAnyX86InstComments(MI, *CommentStream, MII);
58
13.5k
}
59
60
13.5k
bool X86IntelInstPrinter::printVecCompareInstr(const MCInst *MI, raw_ostream &OS) {
61
13.5k
  if (MI->getNumOperands() == 0 ||
62
13.5k
      
!MI->getOperand(MI->getNumOperands() - 1).isImm()13.4k
)
63
10.2k
    return false;
64
3.27k
65
3.27k
  int64_t Imm = MI->getOperand(MI->getNumOperands() - 1).getImm();
66
3.27k
67
3.27k
  const MCInstrDesc &Desc = MII.get(MI->getOpcode());
68
3.27k
69
3.27k
  // Custom print the vector compare instructions to get the immediate
70
3.27k
  // translated into the mnemonic.
71
3.27k
  switch (MI->getOpcode()) {
72
3.27k
  
case X86::CMPPDrmi: 0
case X86::CMPPDrri:
73
0
  case X86::CMPPSrmi:    case X86::CMPPSrri:
74
0
  case X86::CMPSDrm:     case X86::CMPSDrr:
75
0
  case X86::CMPSDrm_Int: case X86::CMPSDrr_Int:
76
0
  case X86::CMPSSrm:     case X86::CMPSSrr:
77
0
  case X86::CMPSSrm_Int: case X86::CMPSSrr_Int:
78
0
    if (Imm >= 0 && Imm <= 7) {
79
0
      OS << '\t';
80
0
      printCMPMnemonic(MI, /*IsVCMP*/false, OS);
81
0
      printOperand(MI, 0, OS);
82
0
      OS << ", ";
83
0
      // Skip operand 1 as its tied to the dest.
84
0
85
0
      if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) {
86
0
        if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XS)
87
0
          printdwordmem(MI, 2, OS);
88
0
        else if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XD)
89
0
          printqwordmem(MI, 2, OS);
90
0
        else
91
0
          printxmmwordmem(MI, 2, OS);
92
0
      } else
93
0
        printOperand(MI, 2, OS);
94
0
95
0
      return true;
96
0
    }
97
0
    break;
98
0
99
196
  case X86::VCMPPDrmi:      case X86::VCMPPDrri:
100
196
  case X86::VCMPPDYrmi:     case X86::VCMPPDYrri:
101
196
  case X86::VCMPPDZ128rmi:  case X86::VCMPPDZ128rri:
102
196
  case X86::VCMPPDZ256rmi:  case X86::VCMPPDZ256rri:
103
196
  case X86::VCMPPDZrmi:     case X86::VCMPPDZrri:
104
196
  case X86::VCMPPSrmi:      case X86::VCMPPSrri:
105
196
  case X86::VCMPPSYrmi:     case X86::VCMPPSYrri:
106
196
  case X86::VCMPPSZ128rmi:  case X86::VCMPPSZ128rri:
107
196
  case X86::VCMPPSZ256rmi:  case X86::VCMPPSZ256rri:
108
196
  case X86::VCMPPSZrmi:     case X86::VCMPPSZrri:
109
196
  case X86::VCMPSDrm:       case X86::VCMPSDrr:
110
196
  case X86::VCMPSDZrm:      case X86::VCMPSDZrr:
111
196
  case X86::VCMPSDrm_Int:   case X86::VCMPSDrr_Int:
112
196
  case X86::VCMPSDZrm_Int:  case X86::VCMPSDZrr_Int:
113
196
  case X86::VCMPSSrm:       case X86::VCMPSSrr:
114
196
  case X86::VCMPSSZrm:      case X86::VCMPSSZrr:
115
196
  case X86::VCMPSSrm_Int:   case X86::VCMPSSrr_Int:
116
196
  case X86::VCMPSSZrm_Int:  case X86::VCMPSSZrr_Int:
117
196
  case X86::VCMPPDZ128rmik: case X86::VCMPPDZ128rrik:
118
196
  case X86::VCMPPDZ256rmik: case X86::VCMPPDZ256rrik:
119
196
  case X86::VCMPPDZrmik:    case X86::VCMPPDZrrik:
120
196
  case X86::VCMPPSZ128rmik: case X86::VCMPPSZ128rrik:
121
196
  case X86::VCMPPSZ256rmik: case X86::VCMPPSZ256rrik:
122
196
  case X86::VCMPPSZrmik:    case X86::VCMPPSZrrik:
123
196
  case X86::VCMPSDZrm_Intk: case X86::VCMPSDZrr_Intk:
124
196
  case X86::VCMPSSZrm_Intk: case X86::VCMPSSZrr_Intk:
125
196
  case X86::VCMPPDZ128rmbi: case X86::VCMPPDZ128rmbik:
126
196
  case X86::VCMPPDZ256rmbi: case X86::VCMPPDZ256rmbik:
127
196
  case X86::VCMPPDZrmbi:    case X86::VCMPPDZrmbik:
128
196
  case X86::VCMPPSZ128rmbi: case X86::VCMPPSZ128rmbik:
129
196
  case X86::VCMPPSZ256rmbi: case X86::VCMPPSZ256rmbik:
130
196
  case X86::VCMPPSZrmbi:    case X86::VCMPPSZrmbik:
131
196
  case X86::VCMPPDZrrib:    case X86::VCMPPDZrribk:
132
196
  case X86::VCMPPSZrrib:    case X86::VCMPPSZrribk:
133
196
  case X86::VCMPSDZrrb_Int: case X86::VCMPSDZrrb_Intk:
134
196
  case X86::VCMPSSZrrb_Int: case X86::VCMPSSZrrb_Intk:
135
196
    if (Imm >= 0 && Imm <= 31) {
136
0
      OS << '\t';
137
0
      printCMPMnemonic(MI, /*IsVCMP*/true, OS);
138
0
139
0
      unsigned CurOp = 0;
140
0
      printOperand(MI, CurOp++, OS);
141
0
142
0
      if (Desc.TSFlags & X86II::EVEX_K) {
143
0
        // Print mask operand.
144
0
        OS << " {";
145
0
        printOperand(MI, CurOp++, OS);
146
0
        OS << "}";
147
0
      }
148
0
      OS << ", ";
149
0
      printOperand(MI, CurOp++, OS);
150
0
      OS << ", ";
151
0
152
0
      if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) {
153
0
        if (Desc.TSFlags & X86II::EVEX_B) {
154
0
          // Broadcast form.
155
0
          // Load size is based on W-bit.
156
0
          if (Desc.TSFlags & X86II::VEX_W)
157
0
            printqwordmem(MI, CurOp++, OS);
158
0
          else
159
0
            printdwordmem(MI, CurOp++, OS);
160
0
161
0
          // Print the number of elements broadcasted.
162
0
          unsigned NumElts;
163
0
          if (Desc.TSFlags & X86II::EVEX_L2)
164
0
            NumElts = (Desc.TSFlags & X86II::VEX_W) ? 8 : 16;
165
0
          else if (Desc.TSFlags & X86II::VEX_L)
166
0
            NumElts = (Desc.TSFlags & X86II::VEX_W) ? 4 : 8;
167
0
          else
168
0
            NumElts = (Desc.TSFlags & X86II::VEX_W) ? 2 : 4;
169
0
          OS << "{1to" << NumElts << "}";
170
0
        } else {
171
0
          if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XS)
172
0
            printdwordmem(MI, CurOp++, OS);
173
0
          else if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XD)
174
0
            printqwordmem(MI, CurOp++, OS);
175
0
          else if (Desc.TSFlags & X86II::EVEX_L2)
176
0
            printzmmwordmem(MI, CurOp++, OS);
177
0
          else if (Desc.TSFlags & X86II::VEX_L)
178
0
            printymmwordmem(MI, CurOp++, OS);
179
0
          else
180
0
            printxmmwordmem(MI, CurOp++, OS);
181
0
        }
182
0
      } else {
183
0
        printOperand(MI, CurOp++, OS);
184
0
        if (Desc.TSFlags & X86II::EVEX_B)
185
0
          OS << ", {sae}";
186
0
      }
187
0
188
0
      return true;
189
0
    }
190
196
    break;
191
196
192
196
  
case X86::VPCOMBmi: 0
case X86::VPCOMBri:
193
0
  case X86::VPCOMDmi:  case X86::VPCOMDri:
194
0
  case X86::VPCOMQmi:  case X86::VPCOMQri:
195
0
  case X86::VPCOMUBmi: case X86::VPCOMUBri:
196
0
  case X86::VPCOMUDmi: case X86::VPCOMUDri:
197
0
  case X86::VPCOMUQmi: case X86::VPCOMUQri:
198
0
  case X86::VPCOMUWmi: case X86::VPCOMUWri:
199
0
  case X86::VPCOMWmi:  case X86::VPCOMWri:
200
0
    if (Imm >= 0 && Imm <= 7) {
201
0
      OS << '\t';
202
0
      printVPCOMMnemonic(MI, OS);
203
0
      printOperand(MI, 0, OS);
204
0
      OS << ", ";
205
0
      printOperand(MI, 1, OS);
206
0
      OS << ", ";
207
0
      if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem)
208
0
        printxmmwordmem(MI, 2, OS);
209
0
      else
210
0
        printOperand(MI, 2, OS);
211
0
      return true;
212
0
    }
213
0
    break;
214
0
215
112
  case X86::VPCMPBZ128rmi:   case X86::VPCMPBZ128rri:
216
112
  case X86::VPCMPBZ256rmi:   case X86::VPCMPBZ256rri:
217
112
  case X86::VPCMPBZrmi:      case X86::VPCMPBZrri:
218
112
  case X86::VPCMPDZ128rmi:   case X86::VPCMPDZ128rri:
219
112
  case X86::VPCMPDZ256rmi:   case X86::VPCMPDZ256rri:
220
112
  case X86::VPCMPDZrmi:      case X86::VPCMPDZrri:
221
112
  case X86::VPCMPQZ128rmi:   case X86::VPCMPQZ128rri:
222
112
  case X86::VPCMPQZ256rmi:   case X86::VPCMPQZ256rri:
223
112
  case X86::VPCMPQZrmi:      case X86::VPCMPQZrri:
224
112
  case X86::VPCMPUBZ128rmi:  case X86::VPCMPUBZ128rri:
225
112
  case X86::VPCMPUBZ256rmi:  case X86::VPCMPUBZ256rri:
226
112
  case X86::VPCMPUBZrmi:     case X86::VPCMPUBZrri:
227
112
  case X86::VPCMPUDZ128rmi:  case X86::VPCMPUDZ128rri:
228
112
  case X86::VPCMPUDZ256rmi:  case X86::VPCMPUDZ256rri:
229
112
  case X86::VPCMPUDZrmi:     case X86::VPCMPUDZrri:
230
112
  case X86::VPCMPUQZ128rmi:  case X86::VPCMPUQZ128rri:
231
112
  case X86::VPCMPUQZ256rmi:  case X86::VPCMPUQZ256rri:
232
112
  case X86::VPCMPUQZrmi:     case X86::VPCMPUQZrri:
233
112
  case X86::VPCMPUWZ128rmi:  case X86::VPCMPUWZ128rri:
234
112
  case X86::VPCMPUWZ256rmi:  case X86::VPCMPUWZ256rri:
235
112
  case X86::VPCMPUWZrmi:     case X86::VPCMPUWZrri:
236
112
  case X86::VPCMPWZ128rmi:   case X86::VPCMPWZ128rri:
237
112
  case X86::VPCMPWZ256rmi:   case X86::VPCMPWZ256rri:
238
112
  case X86::VPCMPWZrmi:      case X86::VPCMPWZrri:
239
112
  case X86::VPCMPBZ128rmik:  case X86::VPCMPBZ128rrik:
240
112
  case X86::VPCMPBZ256rmik:  case X86::VPCMPBZ256rrik:
241
112
  case X86::VPCMPBZrmik:     case X86::VPCMPBZrrik:
242
112
  case X86::VPCMPDZ128rmik:  case X86::VPCMPDZ128rrik:
243
112
  case X86::VPCMPDZ256rmik:  case X86::VPCMPDZ256rrik:
244
112
  case X86::VPCMPDZrmik:     case X86::VPCMPDZrrik:
245
112
  case X86::VPCMPQZ128rmik:  case X86::VPCMPQZ128rrik:
246
112
  case X86::VPCMPQZ256rmik:  case X86::VPCMPQZ256rrik:
247
112
  case X86::VPCMPQZrmik:     case X86::VPCMPQZrrik:
248
112
  case X86::VPCMPUBZ128rmik: case X86::VPCMPUBZ128rrik:
249
112
  case X86::VPCMPUBZ256rmik: case X86::VPCMPUBZ256rrik:
250
112
  case X86::VPCMPUBZrmik:    case X86::VPCMPUBZrrik:
251
112
  case X86::VPCMPUDZ128rmik: case X86::VPCMPUDZ128rrik:
252
112
  case X86::VPCMPUDZ256rmik: case X86::VPCMPUDZ256rrik:
253
112
  case X86::VPCMPUDZrmik:    case X86::VPCMPUDZrrik:
254
112
  case X86::VPCMPUQZ128rmik: case X86::VPCMPUQZ128rrik:
255
112
  case X86::VPCMPUQZ256rmik: case X86::VPCMPUQZ256rrik:
256
112
  case X86::VPCMPUQZrmik:    case X86::VPCMPUQZrrik:
257
112
  case X86::VPCMPUWZ128rmik: case X86::VPCMPUWZ128rrik:
258
112
  case X86::VPCMPUWZ256rmik: case X86::VPCMPUWZ256rrik:
259
112
  case X86::VPCMPUWZrmik:    case X86::VPCMPUWZrrik:
260
112
  case X86::VPCMPWZ128rmik:  case X86::VPCMPWZ128rrik:
261
112
  case X86::VPCMPWZ256rmik:  case X86::VPCMPWZ256rrik:
262
112
  case X86::VPCMPWZrmik:     case X86::VPCMPWZrrik:
263
112
  case X86::VPCMPDZ128rmib:  case X86::VPCMPDZ128rmibk:
264
112
  case X86::VPCMPDZ256rmib:  case X86::VPCMPDZ256rmibk:
265
112
  case X86::VPCMPDZrmib:     case X86::VPCMPDZrmibk:
266
112
  case X86::VPCMPQZ128rmib:  case X86::VPCMPQZ128rmibk:
267
112
  case X86::VPCMPQZ256rmib:  case X86::VPCMPQZ256rmibk:
268
112
  case X86::VPCMPQZrmib:     case X86::VPCMPQZrmibk:
269
112
  case X86::VPCMPUDZ128rmib: case X86::VPCMPUDZ128rmibk:
270
112
  case X86::VPCMPUDZ256rmib: case X86::VPCMPUDZ256rmibk:
271
112
  case X86::VPCMPUDZrmib:    case X86::VPCMPUDZrmibk:
272
112
  case X86::VPCMPUQZ128rmib: case X86::VPCMPUQZ128rmibk:
273
112
  case X86::VPCMPUQZ256rmib: case X86::VPCMPUQZ256rmibk:
274
112
  case X86::VPCMPUQZrmib:    case X86::VPCMPUQZrmibk:
275
112
    if ((Imm >= 0 && Imm <= 2) || (Imm >= 4 && Imm <= 6)) {
276
0
      OS << '\t';
277
0
      printVPCMPMnemonic(MI, OS);
278
0
279
0
      unsigned CurOp = 0;
280
0
      printOperand(MI, CurOp++, OS);
281
0
282
0
      if (Desc.TSFlags & X86II::EVEX_K) {
283
0
        // Print mask operand.
284
0
        OS << " {";
285
0
        printOperand(MI, CurOp++, OS);
286
0
        OS << "}";
287
0
      }
288
0
      OS << ", ";
289
0
      printOperand(MI, CurOp++, OS);
290
0
      OS << ", ";
291
0
292
0
      if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) {
293
0
        if (Desc.TSFlags & X86II::EVEX_B) {
294
0
          // Broadcast form.
295
0
          // Load size is based on W-bit as only D and Q are supported.
296
0
          if (Desc.TSFlags & X86II::VEX_W)
297
0
            printqwordmem(MI, CurOp++, OS);
298
0
          else
299
0
            printdwordmem(MI, CurOp++, OS);
300
0
301
0
          // Print the number of elements broadcasted.
302
0
          unsigned NumElts;
303
0
          if (Desc.TSFlags & X86II::EVEX_L2)
304
0
            NumElts = (Desc.TSFlags & X86II::VEX_W) ? 8 : 16;
305
0
          else if (Desc.TSFlags & X86II::VEX_L)
306
0
            NumElts = (Desc.TSFlags & X86II::VEX_W) ? 4 : 8;
307
0
          else
308
0
            NumElts = (Desc.TSFlags & X86II::VEX_W) ? 2 : 4;
309
0
          OS << "{1to" << NumElts << "}";
310
0
        } else {
311
0
          if (Desc.TSFlags & X86II::EVEX_L2)
312
0
            printzmmwordmem(MI, CurOp++, OS);
313
0
          else if (Desc.TSFlags & X86II::VEX_L)
314
0
            printymmwordmem(MI, CurOp++, OS);
315
0
          else
316
0
            printxmmwordmem(MI, CurOp++, OS);
317
0
        }
318
0
      } else {
319
0
        printOperand(MI, CurOp++, OS);
320
0
      }
321
0
322
0
      return true;
323
0
    }
324
112
    break;
325
3.27k
  }
326
3.27k
327
3.27k
  return false;
328
3.27k
}
329
330
void X86IntelInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
331
34.0k
                                       raw_ostream &O) {
332
34.0k
  const MCOperand &Op = MI->getOperand(OpNo);
333
34.0k
  if (Op.isReg()) {
334
33.7k
    printRegName(O, Op.getReg());
335
33.7k
  } else 
if (301
Op.isImm()301
) {
336
298
    O << formatImm((int64_t)Op.getImm());
337
298
  } else {
338
3
    assert(Op.isExpr() && "unknown operand kind in printOperand");
339
3
    O << "offset ";
340
3
    Op.getExpr()->print(O, &MAI);
341
3
  }
342
34.0k
}
343
344
void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
345
9.40k
                                            raw_ostream &O) {
346
9.40k
  const MCOperand &BaseReg  = MI->getOperand(Op+X86::AddrBaseReg);
347
9.40k
  unsigned ScaleVal         = MI->getOperand(Op+X86::AddrScaleAmt).getImm();
348
9.40k
  const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg);
349
9.40k
  const MCOperand &DispSpec = MI->getOperand(Op+X86::AddrDisp);
350
9.40k
351
9.40k
  // If this has a segment register, print it.
352
9.40k
  printOptionalSegReg(MI, Op + X86::AddrSegmentReg, O);
353
9.40k
354
9.40k
  O << '[';
355
9.40k
356
9.40k
  bool NeedPlus = false;
357
9.40k
  if (BaseReg.getReg()) {
358
7.65k
    printOperand(MI, Op+X86::AddrBaseReg, O);
359
7.65k
    NeedPlus = true;
360
7.65k
  }
361
9.40k
362
9.40k
  if (IndexReg.getReg()) {
363
1.72k
    if (NeedPlus) 
O << " + "1.67k
;
364
1.72k
    if (ScaleVal != 1)
365
1.61k
      O << ScaleVal << '*';
366
1.72k
    printOperand(MI, Op+X86::AddrIndexReg, O);
367
1.72k
    NeedPlus = true;
368
1.72k
  }
369
9.40k
370
9.40k
  if (!DispSpec.isImm()) {
371
20
    if (NeedPlus) 
O << " + "3
;
372
20
    assert(DispSpec.isExpr() && "non-immediate displacement for LEA?");
373
20
    DispSpec.getExpr()->print(O, &MAI);
374
9.38k
  } else {
375
9.38k
    int64_t DispVal = DispSpec.getImm();
376
9.38k
    if (DispVal || 
(1.42k
!IndexReg.getReg()1.42k
&&
!BaseReg.getReg()1.39k
)) {
377
7.95k
      if (NeedPlus) {
378
6.26k
        if (DispVal > 0)
379
3.89k
          O << " + ";
380
2.37k
        else {
381
2.37k
          O << " - ";
382
2.37k
          DispVal = -DispVal;
383
2.37k
        }
384
6.26k
      }
385
7.95k
      O << formatImm(DispVal);
386
7.95k
    }
387
9.38k
  }
388
9.40k
389
9.40k
  O << ']';
390
9.40k
}
391
392
void X86IntelInstPrinter::printSrcIdx(const MCInst *MI, unsigned Op,
393
4
                                      raw_ostream &O) {
394
4
  // If this has a segment register, print it.
395
4
  printOptionalSegReg(MI, Op + 1, O);
396
4
  O << '[';
397
4
  printOperand(MI, Op, O);
398
4
  O << ']';
399
4
}
400
401
void X86IntelInstPrinter::printDstIdx(const MCInst *MI, unsigned Op,
402
4
                                      raw_ostream &O) {
403
4
  // DI accesses are always ES-based.
404
4
  O << "es:[";
405
4
  printOperand(MI, Op, O);
406
4
  O << ']';
407
4
}
408
409
void X86IntelInstPrinter::printMemOffset(const MCInst *MI, unsigned Op,
410
20
                                         raw_ostream &O) {
411
20
  const MCOperand &DispSpec = MI->getOperand(Op);
412
20
413
20
  // If this has a segment register, print it.
414
20
  printOptionalSegReg(MI, Op + 1, O);
415
20
416
20
  O << '[';
417
20
418
20
  if (DispSpec.isImm()) {
419
18
    O << formatImm(DispSpec.getImm());
420
18
  } else {
421
2
    assert(DispSpec.isExpr() && "non-immediate displacement?");
422
2
    DispSpec.getExpr()->print(O, &MAI);
423
2
  }
424
20
425
20
  O << ']';
426
20
}
427
428
void X86IntelInstPrinter::printU8Imm(const MCInst *MI, unsigned Op,
429
1.82k
                                     raw_ostream &O) {
430
1.82k
  if (MI->getOperand(Op).isExpr())
431
1
    return MI->getOperand(Op).getExpr()->print(O, &MAI);
432
1.82k
433
1.82k
  O << formatImm(MI->getOperand(Op).getImm() & 0xff);
434
1.82k
}
435
436
void X86IntelInstPrinter::printSTiRegOperand(const MCInst *MI, unsigned OpNo,
437
41
                                            raw_ostream &OS) {
438
41
  const MCOperand &Op = MI->getOperand(OpNo);
439
41
  unsigned Reg = Op.getReg();
440
41
  // Override the default printing to print st(0) instead st.
441
41
  if (Reg == X86::ST0)
442
0
    OS << "st(0)";
443
41
  else
444
41
    printRegName(OS, Reg);
445
41
}