Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
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Source (jump to first uncovered line)
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//===-- X86MCCodeEmitter.cpp - Convert X86 code to machine code -----------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file implements the X86MCCodeEmitter class.
10
//
11
//===----------------------------------------------------------------------===//
12
13
#include "MCTargetDesc/X86BaseInfo.h"
14
#include "MCTargetDesc/X86FixupKinds.h"
15
#include "MCTargetDesc/X86MCTargetDesc.h"
16
#include "llvm/ADT/SmallVector.h"
17
#include "llvm/MC/MCCodeEmitter.h"
18
#include "llvm/MC/MCContext.h"
19
#include "llvm/MC/MCExpr.h"
20
#include "llvm/MC/MCFixup.h"
21
#include "llvm/MC/MCInst.h"
22
#include "llvm/MC/MCInstrDesc.h"
23
#include "llvm/MC/MCInstrInfo.h"
24
#include "llvm/MC/MCRegisterInfo.h"
25
#include "llvm/MC/MCSubtargetInfo.h"
26
#include "llvm/MC/MCSymbol.h"
27
#include "llvm/Support/ErrorHandling.h"
28
#include "llvm/Support/raw_ostream.h"
29
#include <cassert>
30
#include <cstdint>
31
#include <cstdlib>
32
33
using namespace llvm;
34
35
#define DEBUG_TYPE "mccodeemitter"
36
37
namespace {
38
39
class X86MCCodeEmitter : public MCCodeEmitter {
40
  const MCInstrInfo &MCII;
41
  MCContext &Ctx;
42
43
public:
44
  X86MCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx)
45
145k
    : MCII(mcii), Ctx(ctx) {
46
145k
  }
47
  X86MCCodeEmitter(const X86MCCodeEmitter &) = delete;
48
  X86MCCodeEmitter &operator=(const X86MCCodeEmitter &) = delete;
49
145k
  ~X86MCCodeEmitter() override = default;
50
51
4.86M
  bool is64BitMode(const MCSubtargetInfo &STI) const {
52
4.86M
    return STI.getFeatureBits()[X86::Mode64Bit];
53
4.86M
  }
54
55
1.93M
  bool is32BitMode(const MCSubtargetInfo &STI) const {
56
1.93M
    return STI.getFeatureBits()[X86::Mode32Bit];
57
1.93M
  }
58
59
4.10M
  bool is16BitMode(const MCSubtargetInfo &STI) const {
60
4.10M
    return STI.getFeatureBits()[X86::Mode16Bit];
61
4.10M
  }
62
63
  /// Is16BitMemOperand - Return true if the specified instruction has
64
  /// a 16-bit memory operand. Op specifies the operand # of the memoperand.
65
  bool Is16BitMemOperand(const MCInst &MI, unsigned Op,
66
558k
                         const MCSubtargetInfo &STI) const {
67
558k
    const MCOperand &BaseReg  = MI.getOperand(Op+X86::AddrBaseReg);
68
558k
    const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
69
558k
    const MCOperand &Disp     = MI.getOperand(Op+X86::AddrDisp);
70
558k
71
558k
    if (is16BitMode(STI) && 
BaseReg.getReg() == 0111
&&
72
558k
        
Disp.isImm()34
&&
Disp.getImm() < 0x1000034
)
73
34
      return true;
74
558k
    if ((BaseReg.getReg() != 0 &&
75
558k
         
X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())542k
) ||
76
558k
        
(558k
IndexReg.getReg() != 0558k
&&
77
558k
         
X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg.getReg())90.0k
))
78
37
      return true;
79
558k
    return false;
80
558k
  }
81
82
2.39M
  unsigned GetX86RegNum(const MCOperand &MO) const {
83
2.39M
    return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()) & 0x7;
84
2.39M
  }
85
86
2.53M
  unsigned getX86RegEncoding(const MCInst &MI, unsigned OpNum) const {
87
2.53M
    return Ctx.getRegisterInfo()->getEncodingValue(
88
2.53M
                                                 MI.getOperand(OpNum).getReg());
89
2.53M
  }
90
91
  // Does this register require a bit to be set in REX prefix.
92
2.11M
  bool isREXExtendedReg(const MCInst &MI, unsigned OpNum) const {
93
2.11M
    return (getX86RegEncoding(MI, OpNum) >> 3) & 1;
94
2.11M
  }
95
96
6.99M
  void EmitByte(uint8_t C, unsigned &CurByte, raw_ostream &OS) const {
97
6.99M
    OS << (char)C;
98
6.99M
    ++CurByte;
99
6.99M
  }
100
101
  void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte,
102
1.10M
                    raw_ostream &OS) const {
103
1.10M
    // Output the constant in little endian byte order.
104
3.66M
    for (unsigned i = 0; i != Size; 
++i2.56M
) {
105
2.56M
      EmitByte(Val & 255, CurByte, OS);
106
2.56M
      Val >>= 8;
107
2.56M
    }
108
1.10M
  }
109
110
  void EmitImmediate(const MCOperand &Disp, SMLoc Loc,
111
                     unsigned ImmSize, MCFixupKind FixupKind,
112
                     unsigned &CurByte, raw_ostream &OS,
113
                     SmallVectorImpl<MCFixup> &Fixups,
114
                     int ImmOffset = 0) const;
115
116
1.25M
  static uint8_t ModRMByte(unsigned Mod, unsigned RegOpcode, unsigned RM) {
117
1.25M
    assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
118
1.25M
    return RM | (RegOpcode << 3) | (Mod << 6);
119
1.25M
  }
120
121
  void EmitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld,
122
623k
                        unsigned &CurByte, raw_ostream &OS) const {
123
623k
    EmitByte(ModRMByte(3, RegOpcodeFld, GetX86RegNum(ModRMReg)), CurByte, OS);
124
623k
  }
125
126
  void EmitSIBByte(unsigned SS, unsigned Index, unsigned Base,
127
109k
                   unsigned &CurByte, raw_ostream &OS) const {
128
109k
    // SIB byte is in the same format as the ModRMByte.
129
109k
    EmitByte(ModRMByte(SS, Index, Base), CurByte, OS);
130
109k
  }
131
132
  void emitMemModRMByte(const MCInst &MI, unsigned Op, unsigned RegOpcodeField,
133
                        uint64_t TSFlags, bool Rex, unsigned &CurByte,
134
                        raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups,
135
                        const MCSubtargetInfo &STI) const;
136
137
  void encodeInstruction(const MCInst &MI, raw_ostream &OS,
138
                         SmallVectorImpl<MCFixup> &Fixups,
139
                         const MCSubtargetInfo &STI) const override;
140
141
  void EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
142
                           const MCInst &MI, const MCInstrDesc &Desc,
143
                           raw_ostream &OS) const;
144
145
  void EmitSegmentOverridePrefix(unsigned &CurByte, unsigned SegOperand,
146
                                 const MCInst &MI, raw_ostream &OS) const;
147
148
  bool emitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
149
                        const MCInst &MI, const MCInstrDesc &Desc,
150
                        const MCSubtargetInfo &STI, raw_ostream &OS) const;
151
152
  uint8_t DetermineREXPrefix(const MCInst &MI, uint64_t TSFlags,
153
                             int MemOperand, const MCInstrDesc &Desc) const;
154
155
  bool isPCRel32Branch(const MCInst &MI) const;
156
};
157
158
} // end anonymous namespace
159
160
/// isDisp8 - Return true if this signed displacement fits in a 8-bit
161
/// sign-extended field.
162
321k
static bool isDisp8(int Value) {
163
321k
  return Value == (int8_t)Value;
164
321k
}
165
166
/// isCDisp8 - Return true if this signed displacement fits in a 8-bit
167
/// compressed dispacement field.
168
29.4k
static bool isCDisp8(uint64_t TSFlags, int Value, int& CValue) {
169
29.4k
  assert(((TSFlags & X86II::EncodingMask) == X86II::EVEX) &&
170
29.4k
         "Compressed 8-bit displacement is only valid for EVEX inst.");
171
29.4k
172
29.4k
  unsigned CD8_Scale =
173
29.4k
    (TSFlags & X86II::CD8_Scale_Mask) >> X86II::CD8_Scale_Shift;
174
29.4k
  if (CD8_Scale == 0) {
175
0
    CValue = Value;
176
0
    return isDisp8(Value);
177
0
  }
178
29.4k
179
29.4k
  unsigned Mask = CD8_Scale - 1;
180
29.4k
  assert((CD8_Scale & Mask) == 0 && "Invalid memory object size.");
181
29.4k
  if (Value & Mask) // Unaligned offset
182
4.43k
    return false;
183
24.9k
  Value /= (int)CD8_Scale;
184
24.9k
  bool Ret = (Value == (int8_t)Value);
185
24.9k
186
24.9k
  if (Ret)
187
15.1k
    CValue = Value;
188
24.9k
  return Ret;
189
24.9k
}
190
191
/// getImmFixupKind - Return the appropriate fixup kind to use for an immediate
192
/// in an instruction with the specified TSFlags.
193
664k
static MCFixupKind getImmFixupKind(uint64_t TSFlags) {
194
664k
  unsigned Size = X86II::getSizeOfImm(TSFlags);
195
664k
  bool isPCRel = X86II::isImmPCRel(TSFlags);
196
664k
197
664k
  if (X86II::isImmSigned(TSFlags)) {
198
24.9k
    switch (Size) {
199
24.9k
    
default: 0
llvm_unreachable0
("Unsupported signed fixup size!");
200
24.9k
    case 4: return MCFixupKind(X86::reloc_signed_4byte);
201
639k
    }
202
639k
  }
203
639k
  return MCFixup::getKindForSize(Size, isPCRel);
204
639k
}
205
206
/// Is32BitMemOperand - Return true if the specified instruction has
207
/// a 32-bit memory operand. Op specifies the operand # of the memoperand.
208
425k
static bool Is32BitMemOperand(const MCInst &MI, unsigned Op) {
209
425k
  const MCOperand &BaseReg  = MI.getOperand(Op+X86::AddrBaseReg);
210
425k
  const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
211
425k
212
425k
  if ((BaseReg.getReg() != 0 &&
213
425k
       
X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())419k
) ||
214
425k
      
(425k
IndexReg.getReg() != 0425k
&&
215
425k
       
X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg())60.8k
))
216
45
    return true;
217
425k
  if (BaseReg.getReg() == X86::EIP) {
218
7
    assert(IndexReg.getReg() == 0 && "Invalid eip-based address.");
219
7
    return true;
220
7
  }
221
425k
  if (IndexReg.getReg() == X86::EIZ)
222
1
    return true;
223
425k
  return false;
224
425k
}
225
226
/// Is64BitMemOperand - Return true if the specified instruction has
227
/// a 64-bit memory operand. Op specifies the operand # of the memoperand.
228
#ifndef NDEBUG
229
static bool Is64BitMemOperand(const MCInst &MI, unsigned Op) {
230
  const MCOperand &BaseReg  = MI.getOperand(Op+X86::AddrBaseReg);
231
  const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
232
233
  if ((BaseReg.getReg() != 0 &&
234
       X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.getReg())) ||
235
      (IndexReg.getReg() != 0 &&
236
       X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg.getReg())))
237
    return true;
238
  return false;
239
}
240
#endif
241
242
/// StartsWithGlobalOffsetTable - Check if this expression starts with
243
///  _GLOBAL_OFFSET_TABLE_ and if it is of the form
244
///  _GLOBAL_OFFSET_TABLE_-symbol. This is needed to support PIC on ELF
245
/// i386 as _GLOBAL_OFFSET_TABLE_ is magical. We check only simple case that
246
/// are know to be used: _GLOBAL_OFFSET_TABLE_ by itself or at the start
247
/// of a binary expression.
248
enum GlobalOffsetTableExprKind {
249
  GOT_None,
250
  GOT_Normal,
251
  GOT_SymDiff
252
};
253
static GlobalOffsetTableExprKind
254
265k
StartsWithGlobalOffsetTable(const MCExpr *Expr) {
255
265k
  const MCExpr *RHS = nullptr;
256
265k
  if (Expr->getKind() == MCExpr::Binary) {
257
12.8k
    const MCBinaryExpr *BE = static_cast<const MCBinaryExpr *>(Expr);
258
12.8k
    Expr = BE->getLHS();
259
12.8k
    RHS = BE->getRHS();
260
12.8k
  }
261
265k
262
265k
  if (Expr->getKind() != MCExpr::SymbolRef)
263
1.04k
    return GOT_None;
264
264k
265
264k
  const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr*>(Expr);
266
264k
  const MCSymbol &S = Ref->getSymbol();
267
264k
  if (S.getName() != "_GLOBAL_OFFSET_TABLE_")
268
264k
    return GOT_None;
269
25
  if (RHS && 
RHS->getKind() == MCExpr::SymbolRef10
)
270
8
    return GOT_SymDiff;
271
17
  return GOT_Normal;
272
17
}
273
274
19.0k
static bool HasSecRelSymbolRef(const MCExpr *Expr) {
275
19.0k
  if (Expr->getKind() == MCExpr::SymbolRef) {
276
16.9k
    const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr*>(Expr);
277
16.9k
    return Ref->getKind() == MCSymbolRefExpr::VK_SECREL;
278
16.9k
  }
279
2.11k
  return false;
280
2.11k
}
281
282
370k
bool X86MCCodeEmitter::isPCRel32Branch(const MCInst &MI) const {
283
370k
  unsigned Opcode = MI.getOpcode();
284
370k
  const MCInstrDesc &Desc = MCII.get(Opcode);
285
370k
  if ((Opcode != X86::CALL64pcrel32 && 
Opcode != X86::JMP_4263k
) ||
286
370k
      
getImmFixupKind(Desc.TSFlags) != FK_PCRel_4123k
)
287
246k
    return false;
288
123k
289
123k
  unsigned CurOp = X86II::getOperandBias(Desc);
290
123k
  const MCOperand &Op = MI.getOperand(CurOp);
291
123k
  if (!Op.isExpr())
292
3
    return false;
293
123k
294
123k
  const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(Op.getExpr());
295
123k
  return Ref && 
Ref->getKind() == MCSymbolRefExpr::VK_None123k
;
296
123k
}
297
298
void X86MCCodeEmitter::
299
EmitImmediate(const MCOperand &DispOp, SMLoc Loc, unsigned Size,
300
              MCFixupKind FixupKind, unsigned &CurByte, raw_ostream &OS,
301
1.10M
              SmallVectorImpl<MCFixup> &Fixups, int ImmOffset) const {
302
1.10M
  const MCExpr *Expr = nullptr;
303
1.10M
  if (DispOp.isImm()) {
304
648k
    // If this is a simple integer displacement that doesn't require a
305
648k
    // relocation, emit it now.
306
648k
    if (FixupKind != FK_PCRel_1 &&
307
648k
        
FixupKind != FK_PCRel_2648k
&&
308
648k
        
FixupKind != FK_PCRel_4648k
) {
309
648k
      EmitConstant(DispOp.getImm()+ImmOffset, Size, CurByte, OS);
310
648k
      return;
311
648k
    }
312
130
    Expr = MCConstantExpr::create(DispOp.getImm(), Ctx);
313
454k
  } else {
314
454k
    Expr = DispOp.getExpr();
315
454k
  }
316
1.10M
317
1.10M
  // If we have an immoffset, add it to the expression.
318
1.10M
  
if (454k
(454k
FixupKind == FK_Data_4454k
||
319
454k
       
FixupKind == FK_Data_8453k
||
320
454k
       
FixupKind == MCFixupKind(X86::reloc_signed_4byte)453k
)) {
321
10.2k
    GlobalOffsetTableExprKind Kind = StartsWithGlobalOffsetTable(Expr);
322
10.2k
    if (Kind != GOT_None) {
323
23
      assert(ImmOffset == 0);
324
23
325
23
      if (Size == 8) {
326
6
        FixupKind = MCFixupKind(X86::reloc_global_offset_table8);
327
17
      } else {
328
17
        assert(Size == 4);
329
17
        FixupKind = MCFixupKind(X86::reloc_global_offset_table);
330
17
      }
331
23
332
23
      if (Kind == GOT_Normal)
333
15
        ImmOffset = CurByte;
334
10.2k
    } else if (Expr->getKind() == MCExpr::SymbolRef) {
335
1.50k
      if (HasSecRelSymbolRef(Expr)) {
336
4
        FixupKind = MCFixupKind(FK_SecRel_4);
337
4
      }
338
8.76k
    } else if (Expr->getKind() == MCExpr::Binary) {
339
8.76k
      const MCBinaryExpr *Bin = static_cast<const MCBinaryExpr*>(Expr);
340
8.76k
      if (HasSecRelSymbolRef(Bin->getLHS())
341
8.76k
          || 
HasSecRelSymbolRef(Bin->getRHS())8.75k
) {
342
1
        FixupKind = MCFixupKind(FK_SecRel_4);
343
1
      }
344
8.76k
    }
345
10.2k
  }
346
454k
347
454k
  // If the fixup is pc-relative, we need to bias the value to be relative to
348
454k
  // the start of the field, not the end of the field.
349
454k
  if (FixupKind == FK_PCRel_4 ||
350
454k
      
FixupKind == MCFixupKind(X86::reloc_riprel_4byte)386k
||
351
454k
      
FixupKind == MCFixupKind(X86::reloc_riprel_4byte_movq_load)341k
||
352
454k
      
FixupKind == MCFixupKind(X86::reloc_riprel_4byte_relax)322k
||
353
454k
      
FixupKind == MCFixupKind(X86::reloc_riprel_4byte_relax_rex)322k
||
354
454k
      
FixupKind == MCFixupKind(X86::reloc_branch_4byte_pcrel)322k
) {
355
255k
    ImmOffset -= 4;
356
255k
    // If this is a pc-relative load off _GLOBAL_OFFSET_TABLE_:
357
255k
    // leaq _GLOBAL_OFFSET_TABLE_(%rip), %r15
358
255k
    // this needs to be a GOTPC32 relocation.
359
255k
    if (StartsWithGlobalOffsetTable(Expr) != GOT_None)
360
3
      FixupKind = MCFixupKind(X86::reloc_global_offset_table);
361
255k
  }
362
454k
  if (FixupKind == FK_PCRel_2)
363
6
    ImmOffset -= 2;
364
454k
  if (FixupKind == FK_PCRel_1)
365
185k
    ImmOffset -= 1;
366
454k
367
454k
  if (ImmOffset)
368
440k
    Expr = MCBinaryExpr::createAdd(Expr, MCConstantExpr::create(ImmOffset, Ctx),
369
440k
                                   Ctx);
370
454k
371
454k
  // Emit a symbolic constant as a fixup and 4 zeros.
372
454k
  Fixups.push_back(MCFixup::create(CurByte, Expr, FixupKind, Loc));
373
454k
  EmitConstant(0, Size, CurByte, OS);
374
454k
}
375
376
void X86MCCodeEmitter::emitMemModRMByte(const MCInst &MI, unsigned Op,
377
                                        unsigned RegOpcodeField,
378
                                        uint64_t TSFlags, bool Rex,
379
                                        unsigned &CurByte, raw_ostream &OS,
380
                                        SmallVectorImpl<MCFixup> &Fixups,
381
523k
                                        const MCSubtargetInfo &STI) const {
382
523k
  const MCOperand &Disp     = MI.getOperand(Op+X86::AddrDisp);
383
523k
  const MCOperand &Base     = MI.getOperand(Op+X86::AddrBaseReg);
384
523k
  const MCOperand &Scale    = MI.getOperand(Op+X86::AddrScaleAmt);
385
523k
  const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
386
523k
  unsigned BaseReg = Base.getReg();
387
523k
  bool HasEVEX = (TSFlags & X86II::EncodingMask) == X86II::EVEX;
388
523k
389
523k
  // Handle %rip relative addressing.
390
523k
  if (BaseReg == X86::RIP ||
391
523k
      
BaseReg == X86::EIP459k
) { // [disp32+rIP] in X86-64 mode
392
63.9k
    assert(is64BitMode(STI) && "Rip-relative addressing requires 64-bit mode");
393
63.9k
    assert(IndexReg.getReg() == 0 && "Invalid rip-relative address");
394
63.9k
    EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
395
63.9k
396
63.9k
    unsigned Opcode = MI.getOpcode();
397
63.9k
    // movq loads are handled with a special relocation form which allows the
398
63.9k
    // linker to eliminate some loads for GOT references which end up in the
399
63.9k
    // same linkage unit.
400
63.9k
    unsigned FixupKind = [=]() {
401
63.9k
      switch (Opcode) {
402
63.9k
      default:
403
45.0k
        return X86::reloc_riprel_4byte;
404
63.9k
      case X86::MOV64rm:
405
18.4k
        assert(Rex);
406
18.4k
        return X86::reloc_riprel_4byte_movq_load;
407
63.9k
      case X86::CALL64m:
408
412
      case X86::JMP64m:
409
412
      case X86::TAILJMPm64:
410
412
      case X86::TEST64mr:
411
412
      case X86::ADC64rm:
412
412
      case X86::ADD64rm:
413
412
      case X86::AND64rm:
414
412
      case X86::CMP64rm:
415
412
      case X86::OR64rm:
416
412
      case X86::SBB64rm:
417
412
      case X86::SUB64rm:
418
412
      case X86::XOR64rm:
419
412
        return Rex ? 
X86::reloc_riprel_4byte_relax_rex330
420
412
                   : 
X86::reloc_riprel_4byte_relax82
;
421
63.9k
      }
422
63.9k
    }();
423
63.9k
424
63.9k
    // rip-relative addressing is actually relative to the *next* instruction.
425
63.9k
    // Since an immediate can follow the mod/rm byte for an instruction, this
426
63.9k
    // means that we need to bias the displacement field of the instruction with
427
63.9k
    // the size of the immediate field. If we have this case, add it into the
428
63.9k
    // expression to emit.
429
63.9k
    // Note: rip-relative addressing using immediate displacement values should
430
63.9k
    // not be adjusted, assuming it was the user's intent.
431
63.9k
    int ImmSize = !Disp.isImm() && 
X86II::hasImm(TSFlags)63.9k
432
63.9k
                      ? 
X86II::getSizeOfImm(TSFlags)2.30k
433
63.9k
                      : 
061.6k
;
434
63.9k
435
63.9k
    EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(FixupKind),
436
63.9k
                  CurByte, OS, Fixups, -ImmSize);
437
63.9k
    return;
438
63.9k
  }
439
459k
440
459k
  unsigned BaseRegNo = BaseReg ? 
GetX86RegNum(Base)449k
:
-1U10.5k
;
441
459k
442
459k
  // 16-bit addressing forms of the ModR/M byte have a different encoding for
443
459k
  // the R/M field and are far more limited in which registers can be used.
444
459k
  if (Is16BitMemOperand(MI, Op, STI)) {
445
38
    if (BaseReg) {
446
21
      // For 32-bit addressing, the row and column values in Table 2-2 are
447
21
      // basically the same. It's AX/CX/DX/BX/SP/BP/SI/DI in that order, with
448
21
      // some special cases. And GetX86RegNum reflects that numbering.
449
21
      // For 16-bit addressing it's more fun, as shown in the SDM Vol 2A,
450
21
      // Table 2-1 "16-Bit Addressing Forms with the ModR/M byte". We can only
451
21
      // use SI/DI/BP/BX, which have "row" values 4-7 in no particular order,
452
21
      // while values 0-3 indicate the allowed combinations (base+index) of
453
21
      // those: 0 for BX+SI, 1 for BX+DI, 2 for BP+SI, 3 for BP+DI.
454
21
      //
455
21
      // R16Table[] is a lookup from the normal RegNo, to the row values from
456
21
      // Table 2-1 for 16-bit addressing modes. Where zero means disallowed.
457
21
      static const unsigned R16Table[] = { 0, 0, 0, 7, 0, 6, 4, 5 };
458
21
      unsigned RMfield = R16Table[BaseRegNo];
459
21
460
21
      assert(RMfield && "invalid 16-bit base register");
461
21
462
21
      if (IndexReg.getReg()) {
463
7
        unsigned IndexReg16 = R16Table[GetX86RegNum(IndexReg)];
464
7
465
7
        assert(IndexReg16 && "invalid 16-bit index register");
466
7
        // We must have one of SI/DI (4,5), and one of BP/BX (6,7).
467
7
        assert(((IndexReg16 ^ RMfield) & 2) &&
468
7
               "invalid 16-bit base/index register combination");
469
7
        assert(Scale.getImm() == 1 &&
470
7
               "invalid scale for 16-bit memory reference");
471
7
472
7
        // Allow base/index to appear in either order (although GAS doesn't).
473
7
        if (IndexReg16 & 2)
474
0
          RMfield = (RMfield & 1) | ((7 - IndexReg16) << 1);
475
7
        else
476
7
          RMfield = (IndexReg16 & 1) | ((7 - RMfield) << 1);
477
7
      }
478
21
479
21
      if (Disp.isImm() && isDisp8(Disp.getImm())) {
480
14
        if (Disp.getImm() == 0 && RMfield != 6) {
481
14
          // There is no displacement; just the register.
482
14
          EmitByte(ModRMByte(0, RegOpcodeField, RMfield), CurByte, OS);
483
14
          return;
484
14
        }
485
0
        // Use the [REG]+disp8 form, including for [BP] which cannot be encoded.
486
0
        EmitByte(ModRMByte(1, RegOpcodeField, RMfield), CurByte, OS);
487
0
        EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups);
488
0
        return;
489
0
      }
490
7
      // This is the [REG]+disp16 case.
491
7
      EmitByte(ModRMByte(2, RegOpcodeField, RMfield), CurByte, OS);
492
17
    } else {
493
17
      // There is no BaseReg; this is the plain [disp16] case.
494
17
      EmitByte(ModRMByte(0, RegOpcodeField, 6), CurByte, OS);
495
17
    }
496
38
497
38
    // Emit 16-bit displacement for plain disp16 or [REG]+disp16 cases.
498
38
    EmitImmediate(Disp, MI.getLoc(), 2, FK_Data_2, CurByte, OS, Fixups);
499
24
    return;
500
459k
  }
501
459k
502
459k
  // Determine whether a SIB byte is needed.
503
459k
  // If no BaseReg, issue a RIP relative instruction only if the MCE can
504
459k
  // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table
505
459k
  // 2-7) and absolute references.
506
459k
507
459k
  if (// The SIB byte must be used if there is an index register.
508
459k
      IndexReg.getReg() == 0 &&
509
459k
      // The SIB byte must be used if the base is ESP/RSP/R12, all of which
510
459k
      // encode to an R/M value of 4, which indicates that a SIB byte is
511
459k
      // present.
512
459k
      
BaseRegNo != N86::ESP384k
&&
513
459k
      // If there is no base register and we're in 64-bit mode, we need a SIB
514
459k
      // byte to emit an addr that is just 'disp32' (the non-RIP relative form).
515
459k
      
(354k
!is64BitMode(STI)354k
||
BaseReg != 0282k
)) {
516
350k
517
350k
    if (BaseReg == 0) {          // [disp32]     in X86-32 mode
518
4.78k
      EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
519
4.78k
      EmitImmediate(Disp, MI.getLoc(), 4, FK_Data_4, CurByte, OS, Fixups);
520
4.78k
      return;
521
4.78k
    }
522
345k
523
345k
    // If the base is not EBP/ESP and there is no displacement, use simple
524
345k
    // indirect register encoding, this handles addresses like [EAX].  The
525
345k
    // encoding for [EBP] with no displacement means [disp32] so we handle it
526
345k
    // by emitting a displacement of 0 below.
527
345k
    if (BaseRegNo != N86::EBP) {
528
197k
      if (Disp.isImm() && 
Disp.getImm() == 0186k
) {
529
59.6k
        EmitByte(ModRMByte(0, RegOpcodeField, BaseRegNo), CurByte, OS);
530
59.6k
        return;
531
59.6k
      }
532
138k
533
138k
      // If the displacement is @tlscall, treat it as a zero.
534
138k
      if (Disp.isExpr()) {
535
11.6k
        auto *Sym = dyn_cast<MCSymbolRefExpr>(Disp.getExpr());
536
11.6k
        if (Sym && 
Sym->getKind() == MCSymbolRefExpr::VK_TLSCALL117
) {
537
6
          // This is exclusively used by call *a@tlscall(base). The relocation
538
6
          // (R_386_TLSCALL or R_X86_64_TLSCALL) applies to the beginning.
539
6
          Fixups.push_back(MCFixup::create(0, Sym, FK_NONE, MI.getLoc()));
540
6
          EmitByte(ModRMByte(0, RegOpcodeField, BaseRegNo), CurByte, OS);
541
6
          return;
542
6
        }
543
286k
      }
544
138k
    }
545
286k
546
286k
    // Otherwise, if the displacement fits in a byte, encode as [REG+disp8].
547
286k
    if (Disp.isImm()) {
548
274k
      if (!HasEVEX && 
isDisp8(Disp.getImm())258k
) {
549
188k
        EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS);
550
188k
        EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups);
551
188k
        return;
552
188k
      }
553
86.3k
      // Try EVEX compressed 8-bit displacement first; if failed, fall back to
554
86.3k
      // 32-bit displacement.
555
86.3k
      int CDisp8 = 0;
556
86.3k
      if (HasEVEX && 
isCDisp8(TSFlags, Disp.getImm(), CDisp8)16.1k
) {
557
8.26k
        EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS);
558
8.26k
        EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups,
559
8.26k
                      CDisp8 - Disp.getImm());
560
8.26k
        return;
561
8.26k
      }
562
89.7k
    }
563
89.7k
564
89.7k
    // Otherwise, emit the most general non-SIB encoding: [REG+disp32]
565
89.7k
    EmitByte(ModRMByte(2, RegOpcodeField, BaseRegNo), CurByte, OS);
566
89.7k
    unsigned Opcode = MI.getOpcode();
567
89.7k
    unsigned FixupKind = Opcode == X86::MOV32rm ? 
X86::reloc_signed_4byte_relax4.04k
568
89.7k
                                                : 
X86::reloc_signed_4byte85.6k
;
569
89.7k
    EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(FixupKind), CurByte, OS,
570
89.7k
                  Fixups);
571
89.7k
    return;
572
89.7k
  }
573
109k
574
109k
  // We need a SIB byte, so start by outputting the ModR/M byte first
575
109k
  assert(IndexReg.getReg() != X86::ESP &&
576
109k
         IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
577
109k
578
109k
  bool ForceDisp32 = false;
579
109k
  bool ForceDisp8  = false;
580
109k
  int CDisp8 = 0;
581
109k
  int ImmOffset = 0;
582
109k
  if (BaseReg == 0) {
583
5.70k
    // If there is no base register, we emit the special case SIB byte with
584
5.70k
    // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
585
5.70k
    EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
586
5.70k
    ForceDisp32 = true;
587
103k
  } else if (!Disp.isImm()) {
588
272
    // Emit the normal disp32 encoding.
589
272
    EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
590
272
    ForceDisp32 = true;
591
103k
  } else if (Disp.getImm() == 0 &&
592
103k
             // Base reg can't be anything that ends up with '5' as the base
593
103k
             // reg, it is the magic [*] nomenclature that indicates no base.
594
103k
             
BaseRegNo != N86::EBP27.4k
) {
595
26.9k
    // Emit no displacement ModR/M byte
596
26.9k
    EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
597
76.5k
  } else if (!HasEVEX && 
isDisp8(Disp.getImm())63.2k
) {
598
47.1k
    // Emit the disp8 encoding.
599
47.1k
    EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS);
600
47.1k
    ForceDisp8 = true;           // Make sure to force 8 bit disp if Base=EBP
601
47.1k
  } else 
if (29.3k
HasEVEX29.3k
&&
isCDisp8(TSFlags, Disp.getImm(), CDisp8)13.2k
) {
602
6.88k
    // Emit the disp8 encoding.
603
6.88k
    EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS);
604
6.88k
    ForceDisp8 = true;           // Make sure to force 8 bit disp if Base=EBP
605
6.88k
    ImmOffset = CDisp8 - Disp.getImm();
606
22.5k
  } else {
607
22.5k
    // Emit the normal disp32 encoding.
608
22.5k
    EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
609
22.5k
  }
610
109k
611
109k
  // Calculate what the SS field value should be...
612
109k
  static const unsigned SSTable[] = { ~0U, 0, 1, ~0U, 2, ~0U, ~0U, ~0U, 3 };
613
109k
  unsigned SS = SSTable[Scale.getImm()];
614
109k
615
109k
  if (BaseReg == 0) {
616
5.70k
    // Handle the SIB byte for the case where there is no base, see Intel
617
5.70k
    // Manual 2A, table 2-7. The displacement has already been output.
618
5.70k
    unsigned IndexRegNo;
619
5.70k
    if (IndexReg.getReg())
620
1.58k
      IndexRegNo = GetX86RegNum(IndexReg);
621
4.12k
    else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5)
622
4.12k
      IndexRegNo = 4;
623
5.70k
    EmitSIBByte(SS, IndexRegNo, 5, CurByte, OS);
624
103k
  } else {
625
103k
    unsigned IndexRegNo;
626
103k
    if (IndexReg.getReg())
627
73.8k
      IndexRegNo = GetX86RegNum(IndexReg);
628
29.8k
    else
629
29.8k
      IndexRegNo = 4;   // For example [ESP+1*<noreg>+4]
630
103k
    EmitSIBByte(SS, IndexRegNo, GetX86RegNum(Base), CurByte, OS);
631
103k
  }
632
109k
633
109k
  // Do we need to output a displacement?
634
109k
  if (ForceDisp8)
635
53.9k
    EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups, ImmOffset);
636
55.4k
  else if (ForceDisp32 || 
Disp.getImm() != 049.4k
)
637
28.4k
    EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(X86::reloc_signed_4byte),
638
28.4k
                  CurByte, OS, Fixups);
639
109k
}
640
641
/// EmitVEXOpcodePrefix - AVX instructions are encoded using a opcode prefix
642
/// called VEX.
643
void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
644
                                           int MemOperand, const MCInst &MI,
645
                                           const MCInstrDesc &Desc,
646
124k
                                           raw_ostream &OS) const {
647
124k
  assert(!(TSFlags & X86II::LOCK) && "Can't have LOCK VEX.");
648
124k
649
124k
  uint64_t Encoding = TSFlags & X86II::EncodingMask;
650
124k
  bool HasEVEX_K = TSFlags & X86II::EVEX_K;
651
124k
  bool HasVEX_4V = TSFlags & X86II::VEX_4V;
652
124k
  bool HasEVEX_RC = TSFlags & X86II::EVEX_RC;
653
124k
654
124k
  // VEX_R: opcode externsion equivalent to REX.R in
655
124k
  // 1's complement (inverted) form
656
124k
  //
657
124k
  //  1: Same as REX_R=0 (must be 1 in 32-bit mode)
658
124k
  //  0: Same as REX_R=1 (64 bit mode only)
659
124k
  //
660
124k
  uint8_t VEX_R = 0x1;
661
124k
  uint8_t EVEX_R2 = 0x1;
662
124k
663
124k
  // VEX_X: equivalent to REX.X, only used when a
664
124k
  // register is used for index in SIB Byte.
665
124k
  //
666
124k
  //  1: Same as REX.X=0 (must be 1 in 32-bit mode)
667
124k
  //  0: Same as REX.X=1 (64-bit mode only)
668
124k
  uint8_t VEX_X = 0x1;
669
124k
670
124k
  // VEX_B:
671
124k
  //
672
124k
  //  1: Same as REX_B=0 (ignored in 32-bit mode)
673
124k
  //  0: Same as REX_B=1 (64 bit mode only)
674
124k
  //
675
124k
  uint8_t VEX_B = 0x1;
676
124k
677
124k
  // VEX_W: opcode specific (use like REX.W, or used for
678
124k
  // opcode extension, or ignored, depending on the opcode byte)
679
124k
  uint8_t VEX_W = (TSFlags & X86II::VEX_W) ? 
135.2k
:
089.3k
;
680
124k
681
124k
  // VEX_5M (VEX m-mmmmm field):
682
124k
  //
683
124k
  //  0b00000: Reserved for future use
684
124k
  //  0b00001: implied 0F leading opcode
685
124k
  //  0b00010: implied 0F 38 leading opcode bytes
686
124k
  //  0b00011: implied 0F 3A leading opcode bytes
687
124k
  //  0b00100-0b11111: Reserved for future use
688
124k
  //  0b01000: XOP map select - 08h instructions with imm byte
689
124k
  //  0b01001: XOP map select - 09h instructions with no imm byte
690
124k
  //  0b01010: XOP map select - 0Ah instructions with imm dword
691
124k
  uint8_t VEX_5M;
692
124k
  switch (TSFlags & X86II::OpMapMask) {
693
124k
  
default: 0
llvm_unreachable0
("Invalid prefix!");
694
124k
  
case X86II::TB: VEX_5M = 0x1; break68.0k
; // 0F
695
124k
  
case X86II::T8: VEX_5M = 0x2; break42.4k
; // 0F 38
696
124k
  
case X86II::TA: VEX_5M = 0x3; break12.2k
; // 0F 3A
697
124k
  
case X86II::XOP8: VEX_5M = 0x8; break717
;
698
124k
  
case X86II::XOP9: VEX_5M = 0x9; break1.04k
;
699
124k
  
case X86II::XOPA: VEX_5M = 0xA; break73
;
700
124k
  }
701
124k
702
124k
  // VEX_4V (VEX vvvv field): a register specifier
703
124k
  // (in 1's complement form) or 1111 if unused.
704
124k
  uint8_t VEX_4V = 0xf;
705
124k
  uint8_t EVEX_V2 = 0x1;
706
124k
707
124k
  // EVEX_L2/VEX_L (Vector Length):
708
124k
  //
709
124k
  // L2 L
710
124k
  //  0 0: scalar or 128-bit vector
711
124k
  //  0 1: 256-bit vector
712
124k
  //  1 0: 512-bit vector
713
124k
  //
714
124k
  uint8_t VEX_L = (TSFlags & X86II::VEX_L) ? 
129.5k
:
095.1k
;
715
124k
  uint8_t EVEX_L2 = (TSFlags & X86II::EVEX_L2) ? 
137.2k
:
087.4k
;
716
124k
717
124k
  // VEX_PP: opcode extension providing equivalent
718
124k
  // functionality of a SIMD prefix
719
124k
  //
720
124k
  //  0b00: None
721
124k
  //  0b01: 66
722
124k
  //  0b10: F3
723
124k
  //  0b11: F2
724
124k
  //
725
124k
  uint8_t VEX_PP = 0;
726
124k
  switch (TSFlags & X86II::OpPrefixMask) {
727
124k
  
case X86II::PD: VEX_PP = 0x1; break79.9k
; // 66
728
124k
  
case X86II::XS: VEX_PP = 0x2; break8.85k
; // F3
729
124k
  
case X86II::XD: VEX_PP = 0x3; break7.63k
; // F2
730
124k
  }
731
124k
732
124k
  // EVEX_U
733
124k
  uint8_t EVEX_U = 1; // Always '1' so far
734
124k
735
124k
  // EVEX_z
736
124k
  uint8_t EVEX_z = (HasEVEX_K && 
(TSFlags & X86II::EVEX_Z)28.1k
) ?
111.7k
:
0112k
;
737
124k
738
124k
  // EVEX_b
739
124k
  uint8_t EVEX_b = (TSFlags & X86II::EVEX_B) ? 
117.6k
:
0107k
;
740
124k
741
124k
  // EVEX_rc
742
124k
  uint8_t EVEX_rc = 0;
743
124k
744
124k
  // EVEX_aaa
745
124k
  uint8_t EVEX_aaa = 0;
746
124k
747
124k
  bool EncodeRC = false;
748
124k
749
124k
  // Classify VEX_B, VEX_4V, VEX_R, VEX_X
750
124k
  unsigned NumOps = Desc.getNumOperands();
751
124k
  unsigned CurOp = X86II::getOperandBias(Desc);
752
124k
753
124k
  switch (TSFlags & X86II::FormMask) {
754
124k
  
default: 0
llvm_unreachable0
("Unexpected form in EmitVEXOpcodePrefix!");
755
124k
  case X86II::RawFrm:
756
1.32k
    break;
757
124k
  case X86II::MRMDestMem: {
758
11.8k
    // MRMDestMem instructions forms:
759
11.8k
    //  MemAddr, src1(ModR/M)
760
11.8k
    //  MemAddr, src1(VEX_4V), src2(ModR/M)
761
11.8k
    //  MemAddr, src1(ModR/M), imm8
762
11.8k
    //
763
11.8k
    unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg);
764
11.8k
    VEX_B = ~(BaseRegEnc >> 3) & 1;
765
11.8k
    unsigned IndexRegEnc = getX86RegEncoding(MI, MemOperand+X86::AddrIndexReg);
766
11.8k
    VEX_X = ~(IndexRegEnc >> 3) & 1;
767
11.8k
    if (!HasVEX_4V) // Only needed with VSIB which don't use VVVV.
768
11.5k
      EVEX_V2 = ~(IndexRegEnc >> 4) & 1;
769
11.8k
770
11.8k
    CurOp += X86::AddrNumOperands;
771
11.8k
772
11.8k
    if (HasEVEX_K)
773
1.24k
      EVEX_aaa = getX86RegEncoding(MI, CurOp++);
774
11.8k
775
11.8k
    if (HasVEX_4V) {
776
220
      unsigned VRegEnc = getX86RegEncoding(MI, CurOp++);
777
220
      VEX_4V = ~VRegEnc & 0xf;
778
220
      EVEX_V2 = ~(VRegEnc >> 4) & 1;
779
220
    }
780
11.8k
781
11.8k
    unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
782
11.8k
    VEX_R = ~(RegEnc >> 3) & 1;
783
11.8k
    EVEX_R2 = ~(RegEnc >> 4) & 1;
784
11.8k
    break;
785
124k
  }
786
124k
  case X86II::MRMSrcMem: {
787
58.4k
    // MRMSrcMem instructions forms:
788
58.4k
    //  src1(ModR/M), MemAddr
789
58.4k
    //  src1(ModR/M), src2(VEX_4V), MemAddr
790
58.4k
    //  src1(ModR/M), MemAddr, imm8
791
58.4k
    //  src1(ModR/M), MemAddr, src2(Imm[7:4])
792
58.4k
    //
793
58.4k
    //  FMA4:
794
58.4k
    //  dst(ModR/M.reg), src1(VEX_4V), src2(ModR/M), src3(Imm[7:4])
795
58.4k
    unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
796
58.4k
    VEX_R = ~(RegEnc >> 3) & 1;
797
58.4k
    EVEX_R2 = ~(RegEnc >> 4) & 1;
798
58.4k
799
58.4k
    if (HasEVEX_K)
800
13.8k
      EVEX_aaa = getX86RegEncoding(MI, CurOp++);
801
58.4k
802
58.4k
    if (HasVEX_4V) {
803
37.9k
      unsigned VRegEnc = getX86RegEncoding(MI, CurOp++);
804
37.9k
      VEX_4V = ~VRegEnc & 0xf;
805
37.9k
      EVEX_V2 = ~(VRegEnc >> 4) & 1;
806
37.9k
    }
807
58.4k
808
58.4k
    unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg);
809
58.4k
    VEX_B = ~(BaseRegEnc >> 3) & 1;
810
58.4k
    unsigned IndexRegEnc = getX86RegEncoding(MI, MemOperand+X86::AddrIndexReg);
811
58.4k
    VEX_X = ~(IndexRegEnc >> 3) & 1;
812
58.4k
    if (!HasVEX_4V) // Only needed with VSIB which don't use VVVV.
813
20.5k
      EVEX_V2 = ~(IndexRegEnc >> 4) & 1;
814
58.4k
815
58.4k
    break;
816
124k
  }
817
124k
  case X86II::MRMSrcMem4VOp3: {
818
479
    // Instruction format for 4VOp3:
819
479
    //   src1(ModR/M), MemAddr, src3(VEX_4V)
820
479
    unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
821
479
    VEX_R = ~(RegEnc >> 3) & 1;
822
479
823
479
    unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg);
824
479
    VEX_B = ~(BaseRegEnc >> 3) & 1;
825
479
    unsigned IndexRegEnc = getX86RegEncoding(MI, MemOperand+X86::AddrIndexReg);
826
479
    VEX_X = ~(IndexRegEnc >> 3) & 1;
827
479
828
479
    VEX_4V = ~getX86RegEncoding(MI, CurOp + X86::AddrNumOperands) & 0xf;
829
479
    break;
830
124k
  }
831
124k
  case X86II::MRMSrcMemOp4: {
832
176
    //  dst(ModR/M.reg), src1(VEX_4V), src2(Imm[7:4]), src3(ModR/M),
833
176
    unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
834
176
    VEX_R = ~(RegEnc >> 3) & 1;
835
176
836
176
    unsigned VRegEnc = getX86RegEncoding(MI, CurOp++);
837
176
    VEX_4V = ~VRegEnc & 0xf;
838
176
839
176
    unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg);
840
176
    VEX_B = ~(BaseRegEnc >> 3) & 1;
841
176
    unsigned IndexRegEnc = getX86RegEncoding(MI, MemOperand+X86::AddrIndexReg);
842
176
    VEX_X = ~(IndexRegEnc >> 3) & 1;
843
176
    break;
844
124k
  }
845
124k
  
case X86II::MRM0m: 1.45k
case X86II::MRM1m:
846
1.45k
  case X86II::MRM2m: case X86II::MRM3m:
847
1.45k
  case X86II::MRM4m: case X86II::MRM5m:
848
1.45k
  case X86II::MRM6m: case X86II::MRM7m: {
849
1.45k
    // MRM[0-9]m instructions forms:
850
1.45k
    //  MemAddr
851
1.45k
    //  src1(VEX_4V), MemAddr
852
1.45k
    if (HasVEX_4V) {
853
1.36k
      unsigned VRegEnc = getX86RegEncoding(MI, CurOp++);
854
1.36k
      VEX_4V = ~VRegEnc & 0xf;
855
1.36k
      EVEX_V2 = ~(VRegEnc >> 4) & 1;
856
1.36k
    }
857
1.45k
858
1.45k
    if (HasEVEX_K)
859
480
      EVEX_aaa = getX86RegEncoding(MI, CurOp++);
860
1.45k
861
1.45k
    unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg);
862
1.45k
    VEX_B = ~(BaseRegEnc >> 3) & 1;
863
1.45k
    unsigned IndexRegEnc = getX86RegEncoding(MI, MemOperand+X86::AddrIndexReg);
864
1.45k
    VEX_X = ~(IndexRegEnc >> 3) & 1;
865
1.45k
    break;
866
1.45k
  }
867
45.2k
  case X86II::MRMSrcReg: {
868
45.2k
    // MRMSrcReg instructions forms:
869
45.2k
    //  dst(ModR/M), src1(VEX_4V), src2(ModR/M), src3(Imm[7:4])
870
45.2k
    //  dst(ModR/M), src1(ModR/M)
871
45.2k
    //  dst(ModR/M), src1(ModR/M), imm8
872
45.2k
    //
873
45.2k
    //  FMA4:
874
45.2k
    //  dst(ModR/M.reg), src1(VEX_4V), src2(Imm[7:4]), src3(ModR/M),
875
45.2k
    unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
876
45.2k
    VEX_R = ~(RegEnc >> 3) & 1;
877
45.2k
    EVEX_R2 = ~(RegEnc >> 4) & 1;
878
45.2k
879
45.2k
    if (HasEVEX_K)
880
11.1k
      EVEX_aaa = getX86RegEncoding(MI, CurOp++);
881
45.2k
882
45.2k
    if (HasVEX_4V) {
883
29.9k
      unsigned VRegEnc = getX86RegEncoding(MI, CurOp++);
884
29.9k
      VEX_4V = ~VRegEnc & 0xf;
885
29.9k
      EVEX_V2 = ~(VRegEnc >> 4) & 1;
886
29.9k
    }
887
45.2k
888
45.2k
    RegEnc = getX86RegEncoding(MI, CurOp++);
889
45.2k
    VEX_B = ~(RegEnc >> 3) & 1;
890
45.2k
    VEX_X = ~(RegEnc >> 4) & 1;
891
45.2k
892
45.2k
    if (EVEX_b) {
893
5.26k
      if (HasEVEX_RC) {
894
4.64k
        unsigned RcOperand = NumOps-1;
895
4.64k
        assert(RcOperand >= CurOp);
896
4.64k
        EVEX_rc = MI.getOperand(RcOperand).getImm();
897
4.64k
        assert(EVEX_rc <= 3 && "Invalid rounding control!");
898
4.64k
      }
899
5.26k
      EncodeRC = true;
900
5.26k
    }
901
45.2k
    break;
902
1.45k
  }
903
1.77k
  case X86II::MRMSrcReg4VOp3: {
904
1.77k
    // Instruction format for 4VOp3:
905
1.77k
    //   src1(ModR/M), src2(ModR/M), src3(VEX_4V)
906
1.77k
    unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
907
1.77k
    VEX_R = ~(RegEnc >> 3) & 1;
908
1.77k
909
1.77k
    RegEnc = getX86RegEncoding(MI, CurOp++);
910
1.77k
    VEX_B = ~(RegEnc >> 3) & 1;
911
1.77k
912
1.77k
    VEX_4V = ~getX86RegEncoding(MI, CurOp++) & 0xf;
913
1.77k
    break;
914
1.45k
  }
915
1.45k
  case X86II::MRMSrcRegOp4: {
916
154
    //  dst(ModR/M.reg), src1(VEX_4V), src2(Imm[7:4]), src3(ModR/M),
917
154
    unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
918
154
    VEX_R = ~(RegEnc >> 3) & 1;
919
154
920
154
    unsigned VRegEnc = getX86RegEncoding(MI, CurOp++);
921
154
    VEX_4V = ~VRegEnc & 0xf;
922
154
923
154
    // Skip second register source (encoded in Imm[7:4])
924
154
    ++CurOp;
925
154
926
154
    RegEnc = getX86RegEncoding(MI, CurOp++);
927
154
    VEX_B = ~(RegEnc >> 3) & 1;
928
154
    VEX_X = ~(RegEnc >> 4) & 1;
929
154
    break;
930
1.45k
  }
931
2.24k
  case X86II::MRMDestReg: {
932
2.24k
    // MRMDestReg instructions forms:
933
2.24k
    //  dst(ModR/M), src(ModR/M)
934
2.24k
    //  dst(ModR/M), src(ModR/M), imm8
935
2.24k
    //  dst(ModR/M), src1(VEX_4V), src2(ModR/M)
936
2.24k
    unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
937
2.24k
    VEX_B = ~(RegEnc >> 3) & 1;
938
2.24k
    VEX_X = ~(RegEnc >> 4) & 1;
939
2.24k
940
2.24k
    if (HasEVEX_K)
941
1.01k
      EVEX_aaa = getX86RegEncoding(MI, CurOp++);
942
2.24k
943
2.24k
    if (HasVEX_4V) {
944
44
      unsigned VRegEnc = getX86RegEncoding(MI, CurOp++);
945
44
      VEX_4V = ~VRegEnc & 0xf;
946
44
      EVEX_V2 = ~(VRegEnc >> 4) & 1;
947
44
    }
948
2.24k
949
2.24k
    RegEnc = getX86RegEncoding(MI, CurOp++);
950
2.24k
    VEX_R = ~(RegEnc >> 3) & 1;
951
2.24k
    EVEX_R2 = ~(RegEnc >> 4) & 1;
952
2.24k
    if (EVEX_b)
953
12
      EncodeRC = true;
954
2.24k
    break;
955
1.45k
  }
956
1.55k
  case X86II::MRM0r: case X86II::MRM1r:
957
1.55k
  case X86II::MRM2r: case X86II::MRM3r:
958
1.55k
  case X86II::MRM4r: case X86II::MRM5r:
959
1.55k
  case X86II::MRM6r: case X86II::MRM7r: {
960
1.55k
    // MRM0r-MRM7r instructions forms:
961
1.55k
    //  dst(VEX_4V), src(ModR/M), imm8
962
1.55k
    if (HasVEX_4V) {
963
1.53k
      unsigned VRegEnc = getX86RegEncoding(MI, CurOp++);
964
1.53k
      VEX_4V = ~VRegEnc & 0xf;
965
1.53k
      EVEX_V2 = ~(VRegEnc >> 4) & 1;
966
1.53k
    }
967
1.55k
    if (HasEVEX_K)
968
360
      EVEX_aaa = getX86RegEncoding(MI, CurOp++);
969
1.55k
970
1.55k
    unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
971
1.55k
    VEX_B = ~(RegEnc >> 3) & 1;
972
1.55k
    VEX_X = ~(RegEnc >> 4) & 1;
973
1.55k
    break;
974
124k
  }
975
124k
  }
976
124k
977
124k
  if (Encoding == X86II::VEX || 
Encoding == X86II::XOP66.9k
) {
978
59.5k
    // VEX opcode prefix can have 2 or 3 bytes
979
59.5k
    //
980
59.5k
    //  3 bytes:
981
59.5k
    //    +-----+ +--------------+ +-------------------+
982
59.5k
    //    | C4h | | RXB | m-mmmm | | W | vvvv | L | pp |
983
59.5k
    //    +-----+ +--------------+ +-------------------+
984
59.5k
    //  2 bytes:
985
59.5k
    //    +-----+ +-------------------+
986
59.5k
    //    | C5h | | R | vvvv | L | pp |
987
59.5k
    //    +-----+ +-------------------+
988
59.5k
    //
989
59.5k
    //  XOP uses a similar prefix:
990
59.5k
    //    +-----+ +--------------+ +-------------------+
991
59.5k
    //    | 8Fh | | RXB | m-mmmm | | W | vvvv | L | pp |
992
59.5k
    //    +-----+ +--------------+ +-------------------+
993
59.5k
    uint8_t LastByte = VEX_PP | (VEX_L << 2) | (VEX_4V << 3);
994
59.5k
995
59.5k
    // Can we use the 2 byte VEX prefix?
996
59.5k
    if (!(MI.getFlags() & X86::IP_USE_VEX3) &&
997
59.5k
        
Encoding == X86II::VEX59.5k
&&
VEX_B57.7k
&&
VEX_X53.6k
&&
!VEX_W53.3k
&&
(VEX_5M == 1)47.9k
) {
998
37.7k
      EmitByte(0xC5, CurByte, OS);
999
37.7k
      EmitByte(LastByte | (VEX_R << 7), CurByte, OS);
1000
37.7k
      return;
1001
37.7k
    }
1002
21.8k
1003
21.8k
    // 3 byte VEX prefix
1004
21.8k
    EmitByte(Encoding == X86II::XOP ? 
0x8F1.83k
:
0xC420.0k
, CurByte, OS);
1005
21.8k
    EmitByte(VEX_R << 7 | VEX_X << 6 | VEX_B << 5 | VEX_5M, CurByte, OS);
1006
21.8k
    EmitByte(LastByte | (VEX_W << 7), CurByte, OS);
1007
65.0k
  } else {
1008
65.0k
    assert(Encoding == X86II::EVEX && "unknown encoding!");
1009
65.0k
    // EVEX opcode prefix can have 4 bytes
1010
65.0k
    //
1011
65.0k
    // +-----+ +--------------+ +-------------------+ +------------------------+
1012
65.0k
    // | 62h | | RXBR' | 00mm | | W | vvvv | U | pp | | z | L'L | b | v' | aaa |
1013
65.0k
    // +-----+ +--------------+ +-------------------+ +------------------------+
1014
65.0k
    assert((VEX_5M & 0x3) == VEX_5M
1015
65.0k
           && "More than 2 significant bits in VEX.m-mmmm fields for EVEX!");
1016
65.0k
1017
65.0k
    EmitByte(0x62, CurByte, OS);
1018
65.0k
    EmitByte((VEX_R   << 7) |
1019
65.0k
             (VEX_X   << 6) |
1020
65.0k
             (VEX_B   << 5) |
1021
65.0k
             (EVEX_R2 << 4) |
1022
65.0k
             VEX_5M, CurByte, OS);
1023
65.0k
    EmitByte((VEX_W   << 7) |
1024
65.0k
             (VEX_4V  << 3) |
1025
65.0k
             (EVEX_U  << 2) |
1026
65.0k
             VEX_PP, CurByte, OS);
1027
65.0k
    if (EncodeRC)
1028
5.27k
      EmitByte((EVEX_z  << 7) |
1029
5.27k
               (EVEX_rc << 5) |
1030
5.27k
               (EVEX_b  << 4) |
1031
5.27k
               (EVEX_V2 << 3) |
1032
5.27k
               EVEX_aaa, CurByte, OS);
1033
59.7k
    else
1034
59.7k
      EmitByte((EVEX_z  << 7) |
1035
59.7k
               (EVEX_L2 << 6) |
1036
59.7k
               (VEX_L   << 5) |
1037
59.7k
               (EVEX_b  << 4) |
1038
59.7k
               (EVEX_V2 << 3) |
1039
59.7k
               EVEX_aaa, CurByte, OS);
1040
65.0k
  }
1041
124k
}
1042
1043
/// DetermineREXPrefix - Determine if the MCInst has to be encoded with a X86-64
1044
/// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
1045
/// size, and 3) use of X86-64 extended registers.
1046
uint8_t X86MCCodeEmitter::DetermineREXPrefix(const MCInst &MI, uint64_t TSFlags,
1047
                                             int MemOperand,
1048
1.43M
                                             const MCInstrDesc &Desc) const {
1049
1.43M
  uint8_t REX = 0;
1050
1.43M
  bool UsesHighByteReg = false;
1051
1.43M
1052
1.43M
  if (TSFlags & X86II::REX_W)
1053
640k
    REX |= 1 << 3; // set REX.W
1054
1.43M
1055
1.43M
  if (MI.getNumOperands() == 0) 
return REX15.7k
;
1056
1.41M
1057
1.41M
  unsigned NumOps = MI.getNumOperands();
1058
1.41M
  unsigned CurOp = X86II::getOperandBias(Desc);
1059
1.41M
1060
1.41M
  // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
1061
5.38M
  for (unsigned i = CurOp; i != NumOps; 
++i3.96M
) {
1062
3.96M
    const MCOperand &MO = MI.getOperand(i);
1063
3.96M
    if (!MO.isReg()) 
continue1.46M
;
1064
2.50M
    unsigned Reg = MO.getReg();
1065
2.50M
    if (
Reg == X86::AH2.50M
|| Reg == X86::BH || Reg == X86::CH ||
Reg == X86::DH2.50M
)
1066
2
      UsesHighByteReg = true;
1067
2.50M
    if (X86II::isX86_64NonExtLowByteReg(Reg))
1068
1.77k
      // FIXME: The caller of DetermineREXPrefix slaps this prefix onto anything
1069
1.77k
      // that returns non-zero.
1070
1.77k
      REX |= 0x40; // REX fixed encoding prefix
1071
2.50M
  }
1072
1.41M
1073
1.41M
  switch (TSFlags & X86II::FormMask) {
1074
1.41M
  case X86II::AddRegFrm:
1075
193k
    REX |= isREXExtendedReg(MI, CurOp++) << 0; // REX.B
1076
193k
    break;
1077
1.41M
  case X86II::MRMSrcReg:
1078
23.6k
  case X86II::MRMSrcRegCC:
1079
23.6k
    REX |= isREXExtendedReg(MI, CurOp++) << 2; // REX.R
1080
23.6k
    REX |= isREXExtendedReg(MI, CurOp++) << 0; // REX.B
1081
23.6k
    break;
1082
225k
  case X86II::MRMSrcMem:
1083
225k
  case X86II::MRMSrcMemCC:
1084
225k
    REX |= isREXExtendedReg(MI, CurOp++) << 2; // REX.R
1085
225k
    REX |= isREXExtendedReg(MI, MemOperand+X86::AddrBaseReg) << 0; // REX.B
1086
225k
    REX |= isREXExtendedReg(MI, MemOperand+X86::AddrIndexReg) << 1; // REX.X
1087
225k
    CurOp += X86::AddrNumOperands;
1088
225k
    break;
1089
357k
  case X86II::MRMDestReg:
1090
357k
    REX |= isREXExtendedReg(MI, CurOp++) << 0; // REX.B
1091
357k
    REX |= isREXExtendedReg(MI, CurOp++) << 2; // REX.R
1092
357k
    break;
1093
225k
  case X86II::MRMDestMem:
1094
75.0k
    REX |= isREXExtendedReg(MI, MemOperand+X86::AddrBaseReg) << 0; // REX.B
1095
75.0k
    REX |= isREXExtendedReg(MI, MemOperand+X86::AddrIndexReg) << 1; // REX.X
1096
75.0k
    CurOp += X86::AddrNumOperands;
1097
75.0k
    REX |= isREXExtendedReg(MI, CurOp++) << 2; // REX.R
1098
75.0k
    break;
1099
225k
  
case X86II::MRMXmCC: 68.9k
case X86II::MRMXm:
1100
68.9k
  case X86II::MRM0m: case X86II::MRM1m:
1101
68.9k
  case X86II::MRM2m: case X86II::MRM3m:
1102
68.9k
  case X86II::MRM4m: case X86II::MRM5m:
1103
68.9k
  case X86II::MRM6m: case X86II::MRM7m:
1104
68.9k
    REX |= isREXExtendedReg(MI, MemOperand+X86::AddrBaseReg) << 0; // REX.B
1105
68.9k
    REX |= isREXExtendedReg(MI, MemOperand+X86::AddrIndexReg) << 1; // REX.X
1106
68.9k
    break;
1107
120k
  case X86II::MRMXrCC: case X86II::MRMXr:
1108
120k
  case X86II::MRM0r: case X86II::MRM1r:
1109
120k
  case X86II::MRM2r: case X86II::MRM3r:
1110
120k
  case X86II::MRM4r: case X86II::MRM5r:
1111
120k
  case X86II::MRM6r: case X86II::MRM7r:
1112
120k
    REX |= isREXExtendedReg(MI, CurOp++) << 0; // REX.B
1113
120k
    break;
1114
1.41M
  }
1115
1.41M
  if (REX && 
UsesHighByteReg778k
)
1116
1
    report_fatal_error("Cannot encode high byte register in REX-prefixed instruction");
1117
1.41M
1118
1.41M
  return REX;
1119
1.41M
}
1120
1121
/// EmitSegmentOverridePrefix - Emit segment override opcode prefix as needed
1122
void X86MCCodeEmitter::EmitSegmentOverridePrefix(unsigned &CurByte,
1123
                                                 unsigned SegOperand,
1124
                                                 const MCInst &MI,
1125
524k
                                                 raw_ostream &OS) const {
1126
524k
  // Check for explicit segment override on memory operand.
1127
524k
  switch (MI.getOperand(SegOperand).getReg()) {
1128
524k
  
default: 0
llvm_unreachable0
("Unknown segment register!");
1129
524k
  
case 0: break523k
;
1130
524k
  
case X86::CS: EmitByte(0x2E, CurByte, OS); break14
;
1131
524k
  
case X86::SS: EmitByte(0x36, CurByte, OS); break4
;
1132
524k
  
case X86::DS: EmitByte(0x3E, CurByte, OS); break0
;
1133
524k
  
case X86::ES: EmitByte(0x26, CurByte, OS); break71
;
1134
524k
  
case X86::FS: EmitByte(0x64, CurByte, OS); break141
;
1135
524k
  
case X86::GS: EmitByte(0x65, CurByte, OS); break202
;
1136
524k
  }
1137
524k
}
1138
1139
/// Emit all instruction prefixes prior to the opcode.
1140
///
1141
/// MemOperand is the operand # of the start of a memory operand if present.  If
1142
/// Not present, it is -1.
1143
///
1144
/// Returns true if a REX prefix was used.
1145
bool X86MCCodeEmitter::emitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
1146
                                        int MemOperand, const MCInst &MI,
1147
                                        const MCInstrDesc &Desc,
1148
                                        const MCSubtargetInfo &STI,
1149
1.71M
                                        raw_ostream &OS) const {
1150
1.71M
  bool Ret = false;
1151
1.71M
  // Emit the operand size opcode prefix as needed.
1152
1.71M
  if ((TSFlags & X86II::OpSizeMask) == (is16BitMode(STI) ? 
X86II::OpSize32500
1153
1.71M
                                                         : 
X86II::OpSize161.71M
))
1154
3.36k
    EmitByte(0x66, CurByte, OS);
1155
1.71M
1156
1.71M
  // Emit the LOCK opcode prefix.
1157
1.71M
  if (TSFlags & X86II::LOCK || 
MI.getFlags() & X86::IP_HAS_LOCK1.70M
)
1158
1.50k
    EmitByte(0xF0, CurByte, OS);
1159
1.71M
1160
1.71M
  // Emit the NOTRACK opcode prefix.
1161
1.71M
  if (
TSFlags & X86II::NOTRACK1.71M
|| MI.getFlags() & X86::IP_HAS_NOTRACK)
1162
3
    EmitByte(0x3E, CurByte, OS);
1163
1.71M
1164
1.71M
  switch (TSFlags & X86II::OpPrefixMask) {
1165
1.71M
  case X86II::PD:   // 66
1166
12.6k
    EmitByte(0x66, CurByte, OS);
1167
12.6k
    break;
1168
1.71M
  case X86II::XS:   // F3
1169
7.29k
    EmitByte(0xF3, CurByte, OS);
1170
7.29k
    break;
1171
1.71M
  case X86II::XD:   // F2
1172
3.59k
    EmitByte(0xF2, CurByte, OS);
1173
3.59k
    break;
1174
1.71M
  }
1175
1.71M
1176
1.71M
  // Handle REX prefix.
1177
1.71M
  // FIXME: Can this come before F2 etc to simplify emission?
1178
1.71M
  if (is64BitMode(STI)) {
1179
1.43M
    if (uint8_t REX = DetermineREXPrefix(MI, TSFlags, MemOperand, Desc)) {
1180
779k
      EmitByte(0x40 | REX, CurByte, OS);
1181
779k
      Ret = true;
1182
779k
    }
1183
1.43M
  } else {
1184
275k
    assert(!(TSFlags & X86II::REX_W) && "REX.W requires 64bit mode.");
1185
275k
  }
1186
1.71M
1187
1.71M
  // 0x0F escape code must be emitted just before the opcode.
1188
1.71M
  switch (TSFlags & X86II::OpMapMask) {
1189
1.71M
  case X86II::TB:         // Two-byte opcode map
1190
119k
  case X86II::T8:         // 0F 38
1191
119k
  case X86II::TA:         // 0F 3A
1192
119k
  case X86II::ThreeDNow:  // 0F 0F, second 0F emitted by caller.
1193
119k
    EmitByte(0x0F, CurByte, OS);
1194
119k
    break;
1195
1.71M
  }
1196
1.71M
1197
1.71M
  switch (TSFlags & X86II::OpMapMask) {
1198
1.71M
  case X86II::T8:    // 0F 38
1199
1.96k
    EmitByte(0x38, CurByte, OS);
1200
1.96k
    break;
1201
1.71M
  case X86II::TA:    // 0F 3A
1202
641
    EmitByte(0x3A, CurByte, OS);
1203
641
    break;
1204
1.71M
  }
1205
1.71M
  return Ret;
1206
1.71M
}
1207
1208
void X86MCCodeEmitter::
1209
encodeInstruction(const MCInst &MI, raw_ostream &OS,
1210
                  SmallVectorImpl<MCFixup> &Fixups,
1211
1.83M
                  const MCSubtargetInfo &STI) const {
1212
1.83M
  unsigned Opcode = MI.getOpcode();
1213
1.83M
  const MCInstrDesc &Desc = MCII.get(Opcode);
1214
1.83M
  uint64_t TSFlags = Desc.TSFlags;
1215
1.83M
  unsigned Flags = MI.getFlags();
1216
1.83M
1217
1.83M
  // Pseudo instructions don't get encoded.
1218
1.83M
  if ((TSFlags & X86II::FormMask) == X86II::Pseudo)
1219
0
    return;
1220
1.83M
1221
1.83M
  unsigned NumOps = Desc.getNumOperands();
1222
1.83M
  unsigned CurOp = X86II::getOperandBias(Desc);
1223
1.83M
1224
1.83M
  // Keep track of the current byte being emitted.
1225
1.83M
  unsigned CurByte = 0;
1226
1.83M
1227
1.83M
  // Encoding type for this instruction.
1228
1.83M
  uint64_t Encoding = TSFlags & X86II::EncodingMask;
1229
1.83M
1230
1.83M
  // It uses the VEX.VVVV field?
1231
1.83M
  bool HasVEX_4V = TSFlags & X86II::VEX_4V;
1232
1.83M
  bool HasVEX_I8Reg = (TSFlags & X86II::ImmMask) == X86II::Imm8Reg;
1233
1.83M
1234
1.83M
  // It uses the EVEX.aaa field?
1235
1.83M
  bool HasEVEX_K = TSFlags & X86II::EVEX_K;
1236
1.83M
  bool HasEVEX_RC = TSFlags & X86II::EVEX_RC;
1237
1.83M
1238
1.83M
  // Used if a register is encoded in 7:4 of immediate.
1239
1.83M
  unsigned I8RegNum = 0;
1240
1.83M
1241
1.83M
  // Determine where the memory operand starts, if present.
1242
1.83M
  int MemoryOperand = X86II::getMemoryOperandNo(TSFlags);
1243
1.83M
  if (MemoryOperand != -1) 
MemoryOperand += CurOp523k
;
1244
1.83M
1245
1.83M
  // Emit segment override opcode prefix as needed.
1246
1.83M
  if (MemoryOperand >= 0)
1247
523k
    EmitSegmentOverridePrefix(CurByte, MemoryOperand+X86::AddrSegmentReg,
1248
523k
                              MI, OS);
1249
1.83M
1250
1.83M
  // Emit the repeat opcode prefix as needed.
1251
1.83M
  if (TSFlags & X86II::REP || 
Flags & X86::IP_HAS_REPEAT1.83M
)
1252
270
    EmitByte(0xF3, CurByte, OS);
1253
1.83M
  if (Flags & X86::IP_HAS_REPEAT_NE)
1254
70
    EmitByte(0xF2, CurByte, OS);
1255
1.83M
1256
1.83M
  // Emit the address size opcode prefix as needed.
1257
1.83M
  bool need_address_override;
1258
1.83M
  uint64_t AdSize = TSFlags & X86II::AdSizeMask;
1259
1.83M
  if ((is16BitMode(STI) && 
AdSize == X86II::AdSize32500
) ||
1260
1.83M
      
(1.83M
is32BitMode(STI)1.83M
&&
AdSize == X86II::AdSize16306k
) ||
1261
1.83M
      
(1.83M
is64BitMode(STI)1.83M
&&
AdSize == X86II::AdSize321.52M
)) {
1262
59
    need_address_override = true;
1263
1.83M
  } else if (MemoryOperand < 0) {
1264
1.31M
    need_address_override = false;
1265
1.31M
  } else 
if (523k
is64BitMode(STI)523k
) {
1266
425k
    assert(!Is16BitMemOperand(MI, MemoryOperand, STI));
1267
425k
    need_address_override = Is32BitMemOperand(MI, MemoryOperand);
1268
425k
  } else 
if (98.3k
is32BitMode(STI)98.3k
) {
1269
98.3k
    assert(!Is64BitMemOperand(MI, MemoryOperand));
1270
98.3k
    need_address_override = Is16BitMemOperand(MI, MemoryOperand, STI);
1271
98.3k
  } else {
1272
58
    assert(is16BitMode(STI));
1273
58
    assert(!Is64BitMemOperand(MI, MemoryOperand));
1274
58
    need_address_override = !Is16BitMemOperand(MI, MemoryOperand, STI);
1275
58
  }
1276
1.83M
1277
1.83M
  if (need_address_override)
1278
145
    EmitByte(0x67, CurByte, OS);
1279
1.83M
1280
1.83M
  bool Rex = false;
1281
1.83M
  if (Encoding == 0)
1282
1.71M
    Rex = emitOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, STI, OS);
1283
124k
  else
1284
124k
    EmitVEXOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS);
1285
1.83M
1286
1.83M
  uint8_t BaseOpcode = X86II::getBaseOpcodeFor(TSFlags);
1287
1.83M
1288
1.83M
  if ((TSFlags & X86II::OpMapMask) == X86II::ThreeDNow)
1289
27
    BaseOpcode = 0x0F;   // Weird 3DNow! encoding.
1290
1.83M
1291
1.83M
  unsigned OpcodeOffset = 0;
1292
1.83M
1293
1.83M
  uint64_t Form = TSFlags & X86II::FormMask;
1294
1.83M
  switch (Form) {
1295
1.83M
  default: errs() << "FORM: " << Form << "\n";
1296
0
    llvm_unreachable("Unknown FormMask value in X86MCCodeEmitter!");
1297
1.83M
  case X86II::Pseudo:
1298
0
    llvm_unreachable("Pseudo instruction shouldn't be emitted");
1299
1.83M
  case X86II::RawFrmDstSrc: {
1300
155
    unsigned siReg = MI.getOperand(1).getReg();
1301
155
    assert(((siReg == X86::SI && MI.getOperand(0).getReg() == X86::DI) ||
1302
155
            (siReg == X86::ESI && MI.getOperand(0).getReg() == X86::EDI) ||
1303
155
            (siReg == X86::RSI && MI.getOperand(0).getReg() == X86::RDI)) &&
1304
155
           "SI and DI register sizes do not match");
1305
155
    // Emit segment override opcode prefix as needed (not for %ds).
1306
155
    if (MI.getOperand(2).getReg() != X86::DS)
1307
145
      EmitSegmentOverridePrefix(CurByte, 2, MI, OS);
1308
155
    // Emit AdSize prefix as needed.
1309
155
    if ((!is32BitMode(STI) && 
siReg == X86::ESI102
) ||
1310
155
        
(142
is32BitMode(STI)142
&&
siReg == X86::SI53
))
1311
13
      EmitByte(0x67, CurByte, OS);
1312
155
    CurOp += 3; // Consume operands.
1313
155
    EmitByte(BaseOpcode, CurByte, OS);
1314
155
    break;
1315
1.83M
  }
1316
1.83M
  case X86II::RawFrmSrc: {
1317
167
    unsigned siReg = MI.getOperand(0).getReg();
1318
167
    // Emit segment override opcode prefix as needed (not for %ds).
1319
167
    if (MI.getOperand(1).getReg() != X86::DS)
1320
138
      EmitSegmentOverridePrefix(CurByte, 1, MI, OS);
1321
167
    // Emit AdSize prefix as needed.
1322
167
    if ((!is32BitMode(STI) && 
siReg == X86::ESI106
) ||
1323
167
        
(153
is32BitMode(STI)153
&&
siReg == X86::SI61
))
1324
15
      EmitByte(0x67, CurByte, OS);
1325
167
    CurOp += 2; // Consume operands.
1326
167
    EmitByte(BaseOpcode, CurByte, OS);
1327
167
    break;
1328
1.83M
  }
1329
1.83M
  case X86II::RawFrmDst: {
1330
169
    unsigned siReg = MI.getOperand(0).getReg();
1331
169
    // Emit AdSize prefix as needed.
1332
169
    if ((!is32BitMode(STI) && 
siReg == X86::EDI105
) ||
1333
169
        
(153
is32BitMode(STI)153
&&
siReg == X86::DI64
))
1334
18
      EmitByte(0x67, CurByte, OS);
1335
169
    ++CurOp; // Consume operand.
1336
169
    EmitByte(BaseOpcode, CurByte, OS);
1337
169
    break;
1338
1.83M
  }
1339
1.83M
  case X86II::AddCCFrm: {
1340
196k
    // This will be added to the opcode in the fallthrough.
1341
196k
    OpcodeOffset = MI.getOperand(NumOps - 1).getImm();
1342
196k
    assert(OpcodeOffset < 16 && "Unexpected opcode offset!");
1343
196k
    --NumOps; // Drop the operand from the end.
1344
196k
    LLVM_FALLTHROUGH;
1345
439k
  case X86II::RawFrm:
1346
439k
    EmitByte(BaseOpcode + OpcodeOffset, CurByte, OS);
1347
439k
1348
439k
    if (!is64BitMode(STI) || 
!isPCRel32Branch(MI)370k
)
1349
316k
      break;
1350
122k
1351
122k
    const MCOperand &Op = MI.getOperand(CurOp++);
1352
122k
    EmitImmediate(Op, MI.getLoc(), X86II::getSizeOfImm(TSFlags),
1353
122k
                  MCFixupKind(X86::reloc_branch_4byte_pcrel), CurByte, OS,
1354
122k
                  Fixups);
1355
122k
    break;
1356
122k
  }
1357
122k
  case X86II::RawFrmMemOffs:
1358
188
    // Emit segment override opcode prefix as needed.
1359
188
    EmitSegmentOverridePrefix(CurByte, 1, MI, OS);
1360
188
    EmitByte(BaseOpcode, CurByte, OS);
1361
188
    EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
1362
188
                  X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
1363
188
                  CurByte, OS, Fixups);
1364
188
    ++CurOp; // skip segment operand
1365
188
    break;
1366
122k
  case X86II::RawFrmImm8:
1367
7
    EmitByte(BaseOpcode, CurByte, OS);
1368
7
    EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
1369
7
                  X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
1370
7
                  CurByte, OS, Fixups);
1371
7
    EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1, FK_Data_1, CurByte,
1372
7
                  OS, Fixups);
1373
7
    break;
1374
122k
  case X86II::RawFrmImm16:
1375
27
    EmitByte(BaseOpcode, CurByte, OS);
1376
27
    EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
1377
27
                  X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
1378
27
                  CurByte, OS, Fixups);
1379
27
    EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 2, FK_Data_2, CurByte,
1380
27
                  OS, Fixups);
1381
27
    break;
1382
122k
1383
245k
  case X86II::AddRegFrm:
1384
245k
    EmitByte(BaseOpcode + GetX86RegNum(MI.getOperand(CurOp++)), CurByte, OS);
1385
245k
    break;
1386
122k
1387
389k
  case X86II::MRMDestReg: {
1388
389k
    EmitByte(BaseOpcode, CurByte, OS);
1389
389k
    unsigned SrcRegNum = CurOp + 1;
1390
389k
1391
389k
    if (HasEVEX_K) // Skip writemask
1392
1.01k
      ++SrcRegNum;
1393
389k
1394
389k
    if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
1395
44
      ++SrcRegNum;
1396
389k
1397
389k
    EmitRegModRMByte(MI.getOperand(CurOp),
1398
389k
                     GetX86RegNum(MI.getOperand(SrcRegNum)), CurByte, OS);
1399
389k
    CurOp = SrcRegNum + 1;
1400
389k
    break;
1401
122k
  }
1402
122k
  case X86II::MRMDestMem: {
1403
102k
    EmitByte(BaseOpcode, CurByte, OS);
1404
102k
    unsigned SrcRegNum = CurOp + X86::AddrNumOperands;
1405
102k
1406
102k
    if (HasEVEX_K) // Skip writemask
1407
1.24k
      ++SrcRegNum;
1408
102k
1409
102k
    if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
1410
220
      ++SrcRegNum;
1411
102k
1412
102k
    emitMemModRMByte(MI, CurOp, GetX86RegNum(MI.getOperand(SrcRegNum)), TSFlags,
1413
102k
                     Rex, CurByte, OS, Fixups, STI);
1414
102k
    CurOp = SrcRegNum + 1;
1415
102k
    break;
1416
122k
  }
1417
122k
  case X86II::MRMSrcReg: {
1418
66.2k
    EmitByte(BaseOpcode, CurByte, OS);
1419
66.2k
    unsigned SrcRegNum = CurOp + 1;
1420
66.2k
1421
66.2k
    if (HasEVEX_K) // Skip writemask
1422
11.1k
      ++SrcRegNum;
1423
66.2k
1424
66.2k
    if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
1425
29.9k
      ++SrcRegNum;
1426
66.2k
1427
66.2k
    EmitRegModRMByte(MI.getOperand(SrcRegNum),
1428
66.2k
                     GetX86RegNum(MI.getOperand(CurOp)), CurByte, OS);
1429
66.2k
    CurOp = SrcRegNum + 1;
1430
66.2k
    if (HasVEX_I8Reg)
1431
229
      I8RegNum = getX86RegEncoding(MI, CurOp++);
1432
66.2k
    // do not count the rounding control operand
1433
66.2k
    if (HasEVEX_RC)
1434
4.64k
      --NumOps;
1435
66.2k
    break;
1436
122k
  }
1437
122k
  case X86II::MRMSrcReg4VOp3: {
1438
1.77k
    EmitByte(BaseOpcode, CurByte, OS);
1439
1.77k
    unsigned SrcRegNum = CurOp + 1;
1440
1.77k
1441
1.77k
    EmitRegModRMByte(MI.getOperand(SrcRegNum),
1442
1.77k
                     GetX86RegNum(MI.getOperand(CurOp)), CurByte, OS);
1443
1.77k
    CurOp = SrcRegNum + 1;
1444
1.77k
    ++CurOp; // Encoded in VEX.VVVV
1445
1.77k
    break;
1446
122k
  }
1447
122k
  case X86II::MRMSrcRegOp4: {
1448
154
    EmitByte(BaseOpcode, CurByte, OS);
1449
154
    unsigned SrcRegNum = CurOp + 1;
1450
154
1451
154
    // Skip 1st src (which is encoded in VEX_VVVV)
1452
154
    ++SrcRegNum;
1453
154
1454
154
    // Capture 2nd src (which is encoded in Imm[7:4])
1455
154
    assert(HasVEX_I8Reg && "MRMSrcRegOp4 should imply VEX_I8Reg");
1456
154
    I8RegNum = getX86RegEncoding(MI, SrcRegNum++);
1457
154
1458
154
    EmitRegModRMByte(MI.getOperand(SrcRegNum),
1459
154
                     GetX86RegNum(MI.getOperand(CurOp)), CurByte, OS);
1460
154
    CurOp = SrcRegNum + 1;
1461
154
    break;
1462
122k
  }
1463
122k
  case X86II::MRMSrcRegCC: {
1464
6.96k
    unsigned FirstOp = CurOp++;
1465
6.96k
    unsigned SecondOp = CurOp++;
1466
6.96k
1467
6.96k
    unsigned CC = MI.getOperand(CurOp++).getImm();
1468
6.96k
    EmitByte(BaseOpcode + CC, CurByte, OS);
1469
6.96k
1470
6.96k
    EmitRegModRMByte(MI.getOperand(SecondOp),
1471
6.96k
                     GetX86RegNum(MI.getOperand(FirstOp)), CurByte, OS);
1472
6.96k
    break;
1473
122k
  }
1474
332k
  case X86II::MRMSrcMem: {
1475
332k
    unsigned FirstMemOp = CurOp+1;
1476
332k
1477
332k
    if (HasEVEX_K) // Skip writemask
1478
13.8k
      ++FirstMemOp;
1479
332k
1480
332k
    if (HasVEX_4V)
1481
37.9k
      ++FirstMemOp;  // Skip the register source (which is encoded in VEX_VVVV).
1482
332k
1483
332k
    EmitByte(BaseOpcode, CurByte, OS);
1484
332k
1485
332k
    emitMemModRMByte(MI, FirstMemOp, GetX86RegNum(MI.getOperand(CurOp)),
1486
332k
                     TSFlags, Rex, CurByte, OS, Fixups, STI);
1487
332k
    CurOp = FirstMemOp + X86::AddrNumOperands;
1488
332k
    if (HasVEX_I8Reg)
1489
524
      I8RegNum = getX86RegEncoding(MI, CurOp++);
1490
332k
    break;
1491
122k
  }
1492
122k
  case X86II::MRMSrcMem4VOp3: {
1493
479
    unsigned FirstMemOp = CurOp+1;
1494
479
1495
479
    EmitByte(BaseOpcode, CurByte, OS);
1496
479
1497
479
    emitMemModRMByte(MI, FirstMemOp, GetX86RegNum(MI.getOperand(CurOp)),
1498
479
                     TSFlags, Rex, CurByte, OS, Fixups, STI);
1499
479
    CurOp = FirstMemOp + X86::AddrNumOperands;
1500
479
    ++CurOp; // Encoded in VEX.VVVV.
1501
479
    break;
1502
122k
  }
1503
122k
  case X86II::MRMSrcMemOp4: {
1504
176
    unsigned FirstMemOp = CurOp+1;
1505
176
1506
176
    ++FirstMemOp;  // Skip the register source (which is encoded in VEX_VVVV).
1507
176
1508
176
    // Capture second register source (encoded in Imm[7:4])
1509
176
    assert(HasVEX_I8Reg && "MRMSrcRegOp4 should imply VEX_I8Reg");
1510
176
    I8RegNum = getX86RegEncoding(MI, FirstMemOp++);
1511
176
1512
176
    EmitByte(BaseOpcode, CurByte, OS);
1513
176
1514
176
    emitMemModRMByte(MI, FirstMemOp, GetX86RegNum(MI.getOperand(CurOp)),
1515
176
                     TSFlags, Rex, CurByte, OS, Fixups, STI);
1516
176
    CurOp = FirstMemOp + X86::AddrNumOperands;
1517
176
    break;
1518
122k
  }
1519
122k
  case X86II::MRMSrcMemCC: {
1520
71
    unsigned RegOp = CurOp++;
1521
71
    unsigned FirstMemOp = CurOp;
1522
71
    CurOp = FirstMemOp + X86::AddrNumOperands;
1523
71
1524
71
    unsigned CC = MI.getOperand(CurOp++).getImm();
1525
71
    EmitByte(BaseOpcode + CC, CurByte, OS);
1526
71
1527
71
    emitMemModRMByte(MI, FirstMemOp, GetX86RegNum(MI.getOperand(RegOp)),
1528
71
                     TSFlags, Rex, CurByte, OS, Fixups, STI);
1529
71
    break;
1530
122k
  }
1531
122k
1532
122k
  case X86II::MRMXrCC: {
1533
3.15k
    unsigned RegOp = CurOp++;
1534
3.15k
1535
3.15k
    unsigned CC = MI.getOperand(CurOp++).getImm();
1536
3.15k
    EmitByte(BaseOpcode + CC, CurByte, OS);
1537
3.15k
    EmitRegModRMByte(MI.getOperand(RegOp), 0, CurByte, OS);
1538
3.15k
    break;
1539
122k
  }
1540
122k
1541
156k
  case X86II::MRMXr:
1542
156k
  case X86II::MRM0r: case X86II::MRM1r:
1543
156k
  case X86II::MRM2r: case X86II::MRM3r:
1544
156k
  case X86II::MRM4r: case X86II::MRM5r:
1545
156k
  case X86II::MRM6r: case X86II::MRM7r:
1546
156k
    if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
1547
1.53k
      ++CurOp;
1548
156k
    if (HasEVEX_K) // Skip writemask
1549
360
      ++CurOp;
1550
156k
    EmitByte(BaseOpcode, CurByte, OS);
1551
156k
    EmitRegModRMByte(MI.getOperand(CurOp++),
1552
156k
                     (Form == X86II::MRMXr) ? 
026
:
Form-X86II::MRM0r156k
,
1553
156k
                     CurByte, OS);
1554
156k
    break;
1555
156k
1556
156k
  case X86II::MRMXmCC: {
1557
468
    unsigned FirstMemOp = CurOp;
1558
468
    CurOp = FirstMemOp + X86::AddrNumOperands;
1559
468
1560
468
    unsigned CC = MI.getOperand(CurOp++).getImm();
1561
468
    EmitByte(BaseOpcode + CC, CurByte, OS);
1562
468
1563
468
    emitMemModRMByte(MI, FirstMemOp, 0, TSFlags, Rex, CurByte, OS, Fixups, STI);
1564
468
    break;
1565
156k
  }
1566
156k
1567
156k
  case X86II::MRMXm:
1568
87.5k
  case X86II::MRM0m: case X86II::MRM1m:
1569
87.5k
  case X86II::MRM2m: case X86II::MRM3m:
1570
87.5k
  case X86II::MRM4m: case X86II::MRM5m:
1571
87.5k
  case X86II::MRM6m: case X86II::MRM7m:
1572
87.5k
    if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
1573
1.36k
      ++CurOp;
1574
87.5k
    if (HasEVEX_K) // Skip writemask
1575
480
      ++CurOp;
1576
87.5k
    EmitByte(BaseOpcode, CurByte, OS);
1577
87.5k
    emitMemModRMByte(MI, CurOp,
1578
87.5k
                     (Form == X86II::MRMXm) ? 
036
:
Form - X86II::MRM0m87.5k
, TSFlags,
1579
87.5k
                     Rex, CurByte, OS, Fixups, STI);
1580
87.5k
    CurOp += X86::AddrNumOperands;
1581
87.5k
    break;
1582
87.5k
1583
87.5k
  
case X86II::MRM_C0: 1.98k
case X86II::MRM_C1: 1.98k
case X86II::MRM_C2:
1584
1.98k
  case X86II::MRM_C3: case X86II::MRM_C4: case X86II::MRM_C5:
1585
1.98k
  case X86II::MRM_C6: case X86II::MRM_C7: case X86II::MRM_C8:
1586
1.98k
  case X86II::MRM_C9: case X86II::MRM_CA: case X86II::MRM_CB:
1587
1.98k
  case X86II::MRM_CC: case X86II::MRM_CD: case X86II::MRM_CE:
1588
1.98k
  case X86II::MRM_CF: case X86II::MRM_D0: case X86II::MRM_D1:
1589
1.98k
  case X86II::MRM_D2: case X86II::MRM_D3: case X86II::MRM_D4:
1590
1.98k
  case X86II::MRM_D5: case X86II::MRM_D6: case X86II::MRM_D7:
1591
1.98k
  case X86II::MRM_D8: case X86II::MRM_D9: case X86II::MRM_DA:
1592
1.98k
  case X86II::MRM_DB: case X86II::MRM_DC: case X86II::MRM_DD:
1593
1.98k
  case X86II::MRM_DE: case X86II::MRM_DF: case X86II::MRM_E0:
1594
1.98k
  case X86II::MRM_E1: case X86II::MRM_E2: case X86II::MRM_E3:
1595
1.98k
  case X86II::MRM_E4: case X86II::MRM_E5: case X86II::MRM_E6:
1596
1.98k
  case X86II::MRM_E7: case X86II::MRM_E8: case X86II::MRM_E9:
1597
1.98k
  case X86II::MRM_EA: case X86II::MRM_EB: case X86II::MRM_EC:
1598
1.98k
  case X86II::MRM_ED: case X86II::MRM_EE: case X86II::MRM_EF:
1599
1.98k
  case X86II::MRM_F0: case X86II::MRM_F1: case X86II::MRM_F2:
1600
1.98k
  case X86II::MRM_F3: case X86II::MRM_F4: case X86II::MRM_F5:
1601
1.98k
  case X86II::MRM_F6: case X86II::MRM_F7: case X86II::MRM_F8:
1602
1.98k
  case X86II::MRM_F9: case X86II::MRM_FA: case X86II::MRM_FB:
1603
1.98k
  case X86II::MRM_FC: case X86II::MRM_FD: case X86II::MRM_FE:
1604
1.98k
  case X86II::MRM_FF:
1605
1.98k
    EmitByte(BaseOpcode, CurByte, OS);
1606
1.98k
    EmitByte(0xC0 + Form - X86II::MRM_C0, CurByte, OS);
1607
1.98k
    break;
1608
1.83M
  }
1609
1.83M
1610
1.83M
  if (HasVEX_I8Reg) {
1611
1.08k
    // The last source register of a 4 operand instruction in AVX is encoded
1612
1.08k
    // in bits[7:4] of a immediate byte.
1613
1.08k
    assert(I8RegNum < 16 && "Register encoding out of range");
1614
1.08k
    I8RegNum <<= 4;
1615
1.08k
    if (CurOp != NumOps) {
1616
170
      unsigned Val = MI.getOperand(CurOp++).getImm();
1617
170
      assert(Val < 16 && "Immediate operand value out of range");
1618
170
      I8RegNum |= Val;
1619
170
    }
1620
1.08k
    EmitImmediate(MCOperand::createImm(I8RegNum), MI.getLoc(), 1, FK_Data_1,
1621
1.08k
                  CurByte, OS, Fixups);
1622
1.83M
  } else {
1623
1.83M
    // If there is a remaining operand, it must be a trailing immediate. Emit it
1624
1.83M
    // according to the right size for the instruction. Some instructions
1625
1.83M
    // (SSE4a extrq and insertq) have two trailing immediates.
1626
2.37M
    while (CurOp != NumOps && 
NumOps - CurOp <= 2541k
) {
1627
541k
      EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
1628
541k
                    X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
1629
541k
                    CurByte, OS, Fixups);
1630
541k
    }
1631
1.83M
  }
1632
1.83M
1633
1.83M
  if ((TSFlags & X86II::OpMapMask) == X86II::ThreeDNow)
1634
27
    EmitByte(X86II::getBaseOpcodeFor(TSFlags), CurByte, OS);
1635
1.83M
1636
#ifndef NDEBUG
1637
  // FIXME: Verify.
1638
  if (/*!Desc.isVariadic() &&*/ CurOp != NumOps) {
1639
    errs() << "Cannot encode all operands of: ";
1640
    MI.dump();
1641
    errs() << '\n';
1642
    abort();
1643
  }
1644
#endif
1645
}
1646
1647
MCCodeEmitter *llvm::createX86MCCodeEmitter(const MCInstrInfo &MCII,
1648
                                            const MCRegisterInfo &MRI,
1649
145k
                                            MCContext &Ctx) {
1650
145k
  return new X86MCCodeEmitter(MCII, Ctx);
1651
145k
}