Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
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Count
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//===-- X86MCTargetDesc.cpp - X86 Target Descriptions ---------------------===//
2
//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file provides X86 specific target descriptions.
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//
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//===----------------------------------------------------------------------===//
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#include "X86MCTargetDesc.h"
14
#include "TargetInfo/X86TargetInfo.h"
15
#include "X86ATTInstPrinter.h"
16
#include "X86BaseInfo.h"
17
#include "X86IntelInstPrinter.h"
18
#include "X86MCAsmInfo.h"
19
#include "llvm/ADT/APInt.h"
20
#include "llvm/ADT/Triple.h"
21
#include "llvm/DebugInfo/CodeView/CodeView.h"
22
#include "llvm/MC/MCDwarf.h"
23
#include "llvm/MC/MCInstrAnalysis.h"
24
#include "llvm/MC/MCInstrInfo.h"
25
#include "llvm/MC/MCRegisterInfo.h"
26
#include "llvm/MC/MCStreamer.h"
27
#include "llvm/MC/MCSubtargetInfo.h"
28
#include "llvm/MC/MachineLocation.h"
29
#include "llvm/Support/ErrorHandling.h"
30
#include "llvm/Support/Host.h"
31
#include "llvm/Support/TargetRegistry.h"
32
33
#if _MSC_VER
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#include <intrin.h>
35
#endif
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37
using namespace llvm;
38
39
#define GET_REGINFO_MC_DESC
40
#include "X86GenRegisterInfo.inc"
41
42
#define GET_INSTRINFO_MC_DESC
43
#define GET_INSTRINFO_MC_HELPERS
44
#include "X86GenInstrInfo.inc"
45
46
#define GET_SUBTARGETINFO_MC_DESC
47
#include "X86GenSubtargetInfo.inc"
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28.1k
std::string X86_MC::ParseX86Triple(const Triple &TT) {
50
28.1k
  std::string FS;
51
28.1k
  if (TT.getArch() == Triple::x86_64)
52
21.5k
    FS = "+64bit-mode,-32bit-mode,-16bit-mode";
53
6.55k
  else if (TT.getEnvironment() != Triple::CODE16)
54
6.54k
    FS = "-64bit-mode,+32bit-mode,-16bit-mode";
55
8
  else
56
8
    FS = "-64bit-mode,-32bit-mode,+16bit-mode";
57
28.1k
58
28.1k
  return FS;
59
28.1k
}
60
61
86.9k
unsigned X86_MC::getDwarfRegFlavour(const Triple &TT, bool isEH) {
62
86.9k
  if (TT.getArch() == Triple::x86_64)
63
67.5k
    return DWARFFlavour::X86_64;
64
19.3k
65
19.3k
  if (TT.isOSDarwin())
66
5.24k
    return isEH ? 
DWARFFlavour::X86_32_DarwinEH2.62k
:
DWARFFlavour::X86_32_Generic2.62k
;
67
14.1k
  if (TT.isOSCygMing())
68
424
    // Unsupported by now, just quick fallback
69
424
    return DWARFFlavour::X86_32_Generic;
70
13.7k
  return DWARFFlavour::X86_32_Generic;
71
13.7k
}
72
73
43.4k
void X86_MC::initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI) {
74
43.4k
  // FIXME: TableGen these.
75
12.2M
  for (unsigned Reg = X86::NoRegister + 1; Reg < X86::NUM_TARGET_REGS; 
++Reg12.2M
) {
76
12.2M
    unsigned SEH = MRI->getEncodingValue(Reg);
77
12.2M
    MRI->mapLLVMRegToSEHReg(Reg, SEH);
78
12.2M
  }
79
43.4k
80
43.4k
  // Mapping from CodeView to MC register id.
81
43.4k
  static const struct {
82
43.4k
    codeview::RegisterId CVReg;
83
43.4k
    MCPhysReg Reg;
84
43.4k
  } RegMap[] = {
85
43.4k
      {codeview::RegisterId::AL, X86::AL},
86
43.4k
      {codeview::RegisterId::CL, X86::CL},
87
43.4k
      {codeview::RegisterId::DL, X86::DL},
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43.4k
      {codeview::RegisterId::BL, X86::BL},
89
43.4k
      {codeview::RegisterId::AH, X86::AH},
90
43.4k
      {codeview::RegisterId::CH, X86::CH},
91
43.4k
      {codeview::RegisterId::DH, X86::DH},
92
43.4k
      {codeview::RegisterId::BH, X86::BH},
93
43.4k
      {codeview::RegisterId::AX, X86::AX},
94
43.4k
      {codeview::RegisterId::CX, X86::CX},
95
43.4k
      {codeview::RegisterId::DX, X86::DX},
96
43.4k
      {codeview::RegisterId::BX, X86::BX},
97
43.4k
      {codeview::RegisterId::SP, X86::SP},
98
43.4k
      {codeview::RegisterId::BP, X86::BP},
99
43.4k
      {codeview::RegisterId::SI, X86::SI},
100
43.4k
      {codeview::RegisterId::DI, X86::DI},
101
43.4k
      {codeview::RegisterId::EAX, X86::EAX},
102
43.4k
      {codeview::RegisterId::ECX, X86::ECX},
103
43.4k
      {codeview::RegisterId::EDX, X86::EDX},
104
43.4k
      {codeview::RegisterId::EBX, X86::EBX},
105
43.4k
      {codeview::RegisterId::ESP, X86::ESP},
106
43.4k
      {codeview::RegisterId::EBP, X86::EBP},
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43.4k
      {codeview::RegisterId::ESI, X86::ESI},
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43.4k
      {codeview::RegisterId::EDI, X86::EDI},
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43.4k
110
43.4k
      {codeview::RegisterId::EFLAGS, X86::EFLAGS},
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43.4k
112
43.4k
      {codeview::RegisterId::ST0, X86::FP0},
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43.4k
      {codeview::RegisterId::ST1, X86::FP1},
114
43.4k
      {codeview::RegisterId::ST2, X86::FP2},
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43.4k
      {codeview::RegisterId::ST3, X86::FP3},
116
43.4k
      {codeview::RegisterId::ST4, X86::FP4},
117
43.4k
      {codeview::RegisterId::ST5, X86::FP5},
118
43.4k
      {codeview::RegisterId::ST6, X86::FP6},
119
43.4k
      {codeview::RegisterId::ST7, X86::FP7},
120
43.4k
121
43.4k
      {codeview::RegisterId::MM0, X86::MM0},
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43.4k
      {codeview::RegisterId::MM1, X86::MM1},
123
43.4k
      {codeview::RegisterId::MM2, X86::MM2},
124
43.4k
      {codeview::RegisterId::MM3, X86::MM3},
125
43.4k
      {codeview::RegisterId::MM4, X86::MM4},
126
43.4k
      {codeview::RegisterId::MM5, X86::MM5},
127
43.4k
      {codeview::RegisterId::MM6, X86::MM6},
128
43.4k
      {codeview::RegisterId::MM7, X86::MM7},
129
43.4k
130
43.4k
      {codeview::RegisterId::XMM0, X86::XMM0},
131
43.4k
      {codeview::RegisterId::XMM1, X86::XMM1},
132
43.4k
      {codeview::RegisterId::XMM2, X86::XMM2},
133
43.4k
      {codeview::RegisterId::XMM3, X86::XMM3},
134
43.4k
      {codeview::RegisterId::XMM4, X86::XMM4},
135
43.4k
      {codeview::RegisterId::XMM5, X86::XMM5},
136
43.4k
      {codeview::RegisterId::XMM6, X86::XMM6},
137
43.4k
      {codeview::RegisterId::XMM7, X86::XMM7},
138
43.4k
139
43.4k
      {codeview::RegisterId::XMM8, X86::XMM8},
140
43.4k
      {codeview::RegisterId::XMM9, X86::XMM9},
141
43.4k
      {codeview::RegisterId::XMM10, X86::XMM10},
142
43.4k
      {codeview::RegisterId::XMM11, X86::XMM11},
143
43.4k
      {codeview::RegisterId::XMM12, X86::XMM12},
144
43.4k
      {codeview::RegisterId::XMM13, X86::XMM13},
145
43.4k
      {codeview::RegisterId::XMM14, X86::XMM14},
146
43.4k
      {codeview::RegisterId::XMM15, X86::XMM15},
147
43.4k
148
43.4k
      {codeview::RegisterId::SIL, X86::SIL},
149
43.4k
      {codeview::RegisterId::DIL, X86::DIL},
150
43.4k
      {codeview::RegisterId::BPL, X86::BPL},
151
43.4k
      {codeview::RegisterId::SPL, X86::SPL},
152
43.4k
      {codeview::RegisterId::RAX, X86::RAX},
153
43.4k
      {codeview::RegisterId::RBX, X86::RBX},
154
43.4k
      {codeview::RegisterId::RCX, X86::RCX},
155
43.4k
      {codeview::RegisterId::RDX, X86::RDX},
156
43.4k
      {codeview::RegisterId::RSI, X86::RSI},
157
43.4k
      {codeview::RegisterId::RDI, X86::RDI},
158
43.4k
      {codeview::RegisterId::RBP, X86::RBP},
159
43.4k
      {codeview::RegisterId::RSP, X86::RSP},
160
43.4k
      {codeview::RegisterId::R8, X86::R8},
161
43.4k
      {codeview::RegisterId::R9, X86::R9},
162
43.4k
      {codeview::RegisterId::R10, X86::R10},
163
43.4k
      {codeview::RegisterId::R11, X86::R11},
164
43.4k
      {codeview::RegisterId::R12, X86::R12},
165
43.4k
      {codeview::RegisterId::R13, X86::R13},
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43.4k
      {codeview::RegisterId::R14, X86::R14},
167
43.4k
      {codeview::RegisterId::R15, X86::R15},
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43.4k
      {codeview::RegisterId::R8B, X86::R8B},
169
43.4k
      {codeview::RegisterId::R9B, X86::R9B},
170
43.4k
      {codeview::RegisterId::R10B, X86::R10B},
171
43.4k
      {codeview::RegisterId::R11B, X86::R11B},
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43.4k
      {codeview::RegisterId::R12B, X86::R12B},
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43.4k
      {codeview::RegisterId::R13B, X86::R13B},
174
43.4k
      {codeview::RegisterId::R14B, X86::R14B},
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43.4k
      {codeview::RegisterId::R15B, X86::R15B},
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43.4k
      {codeview::RegisterId::R8W, X86::R8W},
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43.4k
      {codeview::RegisterId::R9W, X86::R9W},
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43.4k
      {codeview::RegisterId::R10W, X86::R10W},
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43.4k
      {codeview::RegisterId::R11W, X86::R11W},
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43.4k
      {codeview::RegisterId::R12W, X86::R12W},
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43.4k
      {codeview::RegisterId::R13W, X86::R13W},
182
43.4k
      {codeview::RegisterId::R14W, X86::R14W},
183
43.4k
      {codeview::RegisterId::R15W, X86::R15W},
184
43.4k
      {codeview::RegisterId::R8D, X86::R8D},
185
43.4k
      {codeview::RegisterId::R9D, X86::R9D},
186
43.4k
      {codeview::RegisterId::R10D, X86::R10D},
187
43.4k
      {codeview::RegisterId::R11D, X86::R11D},
188
43.4k
      {codeview::RegisterId::R12D, X86::R12D},
189
43.4k
      {codeview::RegisterId::R13D, X86::R13D},
190
43.4k
      {codeview::RegisterId::R14D, X86::R14D},
191
43.4k
      {codeview::RegisterId::R15D, X86::R15D},
192
43.4k
      {codeview::RegisterId::AMD64_YMM0, X86::YMM0},
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43.4k
      {codeview::RegisterId::AMD64_YMM1, X86::YMM1},
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43.4k
      {codeview::RegisterId::AMD64_YMM2, X86::YMM2},
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43.4k
      {codeview::RegisterId::AMD64_YMM3, X86::YMM3},
196
43.4k
      {codeview::RegisterId::AMD64_YMM4, X86::YMM4},
197
43.4k
      {codeview::RegisterId::AMD64_YMM5, X86::YMM5},
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43.4k
      {codeview::RegisterId::AMD64_YMM6, X86::YMM6},
199
43.4k
      {codeview::RegisterId::AMD64_YMM7, X86::YMM7},
200
43.4k
      {codeview::RegisterId::AMD64_YMM8, X86::YMM8},
201
43.4k
      {codeview::RegisterId::AMD64_YMM9, X86::YMM9},
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43.4k
      {codeview::RegisterId::AMD64_YMM10, X86::YMM10},
203
43.4k
      {codeview::RegisterId::AMD64_YMM11, X86::YMM11},
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43.4k
      {codeview::RegisterId::AMD64_YMM12, X86::YMM12},
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43.4k
      {codeview::RegisterId::AMD64_YMM13, X86::YMM13},
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43.4k
      {codeview::RegisterId::AMD64_YMM14, X86::YMM14},
207
43.4k
      {codeview::RegisterId::AMD64_YMM15, X86::YMM15},
208
43.4k
      {codeview::RegisterId::AMD64_YMM16, X86::YMM16},
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43.4k
      {codeview::RegisterId::AMD64_YMM17, X86::YMM17},
210
43.4k
      {codeview::RegisterId::AMD64_YMM18, X86::YMM18},
211
43.4k
      {codeview::RegisterId::AMD64_YMM19, X86::YMM19},
212
43.4k
      {codeview::RegisterId::AMD64_YMM20, X86::YMM20},
213
43.4k
      {codeview::RegisterId::AMD64_YMM21, X86::YMM21},
214
43.4k
      {codeview::RegisterId::AMD64_YMM22, X86::YMM22},
215
43.4k
      {codeview::RegisterId::AMD64_YMM23, X86::YMM23},
216
43.4k
      {codeview::RegisterId::AMD64_YMM24, X86::YMM24},
217
43.4k
      {codeview::RegisterId::AMD64_YMM25, X86::YMM25},
218
43.4k
      {codeview::RegisterId::AMD64_YMM26, X86::YMM26},
219
43.4k
      {codeview::RegisterId::AMD64_YMM27, X86::YMM27},
220
43.4k
      {codeview::RegisterId::AMD64_YMM28, X86::YMM28},
221
43.4k
      {codeview::RegisterId::AMD64_YMM29, X86::YMM29},
222
43.4k
      {codeview::RegisterId::AMD64_YMM30, X86::YMM30},
223
43.4k
      {codeview::RegisterId::AMD64_YMM31, X86::YMM31},
224
43.4k
      {codeview::RegisterId::AMD64_ZMM0, X86::ZMM0},
225
43.4k
      {codeview::RegisterId::AMD64_ZMM1, X86::ZMM1},
226
43.4k
      {codeview::RegisterId::AMD64_ZMM2, X86::ZMM2},
227
43.4k
      {codeview::RegisterId::AMD64_ZMM3, X86::ZMM3},
228
43.4k
      {codeview::RegisterId::AMD64_ZMM4, X86::ZMM4},
229
43.4k
      {codeview::RegisterId::AMD64_ZMM5, X86::ZMM5},
230
43.4k
      {codeview::RegisterId::AMD64_ZMM6, X86::ZMM6},
231
43.4k
      {codeview::RegisterId::AMD64_ZMM7, X86::ZMM7},
232
43.4k
      {codeview::RegisterId::AMD64_ZMM8, X86::ZMM8},
233
43.4k
      {codeview::RegisterId::AMD64_ZMM9, X86::ZMM9},
234
43.4k
      {codeview::RegisterId::AMD64_ZMM10, X86::ZMM10},
235
43.4k
      {codeview::RegisterId::AMD64_ZMM11, X86::ZMM11},
236
43.4k
      {codeview::RegisterId::AMD64_ZMM12, X86::ZMM12},
237
43.4k
      {codeview::RegisterId::AMD64_ZMM13, X86::ZMM13},
238
43.4k
      {codeview::RegisterId::AMD64_ZMM14, X86::ZMM14},
239
43.4k
      {codeview::RegisterId::AMD64_ZMM15, X86::ZMM15},
240
43.4k
      {codeview::RegisterId::AMD64_ZMM16, X86::ZMM16},
241
43.4k
      {codeview::RegisterId::AMD64_ZMM17, X86::ZMM17},
242
43.4k
      {codeview::RegisterId::AMD64_ZMM18, X86::ZMM18},
243
43.4k
      {codeview::RegisterId::AMD64_ZMM19, X86::ZMM19},
244
43.4k
      {codeview::RegisterId::AMD64_ZMM20, X86::ZMM20},
245
43.4k
      {codeview::RegisterId::AMD64_ZMM21, X86::ZMM21},
246
43.4k
      {codeview::RegisterId::AMD64_ZMM22, X86::ZMM22},
247
43.4k
      {codeview::RegisterId::AMD64_ZMM23, X86::ZMM23},
248
43.4k
      {codeview::RegisterId::AMD64_ZMM24, X86::ZMM24},
249
43.4k
      {codeview::RegisterId::AMD64_ZMM25, X86::ZMM25},
250
43.4k
      {codeview::RegisterId::AMD64_ZMM26, X86::ZMM26},
251
43.4k
      {codeview::RegisterId::AMD64_ZMM27, X86::ZMM27},
252
43.4k
      {codeview::RegisterId::AMD64_ZMM28, X86::ZMM28},
253
43.4k
      {codeview::RegisterId::AMD64_ZMM29, X86::ZMM29},
254
43.4k
      {codeview::RegisterId::AMD64_ZMM30, X86::ZMM30},
255
43.4k
      {codeview::RegisterId::AMD64_ZMM31, X86::ZMM31},
256
43.4k
      {codeview::RegisterId::AMD64_K0, X86::K0},
257
43.4k
      {codeview::RegisterId::AMD64_K1, X86::K1},
258
43.4k
      {codeview::RegisterId::AMD64_K2, X86::K2},
259
43.4k
      {codeview::RegisterId::AMD64_K3, X86::K3},
260
43.4k
      {codeview::RegisterId::AMD64_K4, X86::K4},
261
43.4k
      {codeview::RegisterId::AMD64_K5, X86::K5},
262
43.4k
      {codeview::RegisterId::AMD64_K6, X86::K6},
263
43.4k
      {codeview::RegisterId::AMD64_K7, X86::K7},
264
43.4k
      {codeview::RegisterId::AMD64_XMM16, X86::XMM16},
265
43.4k
      {codeview::RegisterId::AMD64_XMM17, X86::XMM17},
266
43.4k
      {codeview::RegisterId::AMD64_XMM18, X86::XMM18},
267
43.4k
      {codeview::RegisterId::AMD64_XMM19, X86::XMM19},
268
43.4k
      {codeview::RegisterId::AMD64_XMM20, X86::XMM20},
269
43.4k
      {codeview::RegisterId::AMD64_XMM21, X86::XMM21},
270
43.4k
      {codeview::RegisterId::AMD64_XMM22, X86::XMM22},
271
43.4k
      {codeview::RegisterId::AMD64_XMM23, X86::XMM23},
272
43.4k
      {codeview::RegisterId::AMD64_XMM24, X86::XMM24},
273
43.4k
      {codeview::RegisterId::AMD64_XMM25, X86::XMM25},
274
43.4k
      {codeview::RegisterId::AMD64_XMM26, X86::XMM26},
275
43.4k
      {codeview::RegisterId::AMD64_XMM27, X86::XMM27},
276
43.4k
      {codeview::RegisterId::AMD64_XMM28, X86::XMM28},
277
43.4k
      {codeview::RegisterId::AMD64_XMM29, X86::XMM29},
278
43.4k
      {codeview::RegisterId::AMD64_XMM30, X86::XMM30},
279
43.4k
      {codeview::RegisterId::AMD64_XMM31, X86::XMM31},
280
43.4k
281
43.4k
  };
282
8.26M
  for (unsigned I = 0; I < array_lengthof(RegMap); 
++I8.21M
)
283
8.21M
    MRI->mapLLVMRegToCVReg(RegMap[I].Reg, static_cast<int>(RegMap[I].CVReg));
284
43.4k
}
285
286
MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(const Triple &TT,
287
28.1k
                                                  StringRef CPU, StringRef FS) {
288
28.1k
  std::string ArchFS = X86_MC::ParseX86Triple(TT);
289
28.1k
  if (!FS.empty()) {
290
14.5k
    if (!ArchFS.empty())
291
14.5k
      ArchFS = (Twine(ArchFS) + "," + FS).str();
292
0
    else
293
0
      ArchFS = FS;
294
14.5k
  }
295
28.1k
296
28.1k
  std::string CPUName = CPU;
297
28.1k
  if (CPUName.empty())
298
21.9k
    CPUName = "generic";
299
28.1k
300
28.1k
  return createX86MCSubtargetInfoImpl(TT, CPUName, ArchFS);
301
28.1k
}
302
303
33.5k
static MCInstrInfo *createX86MCInstrInfo() {
304
33.5k
  MCInstrInfo *X = new MCInstrInfo();
305
33.5k
  InitX86MCInstrInfo(X);
306
33.5k
  return X;
307
33.5k
}
308
309
28.2k
static MCRegisterInfo *createX86MCRegisterInfo(const Triple &TT) {
310
28.2k
  unsigned RA = (TT.getArch() == Triple::x86_64)
311
28.2k
                    ? 
X86::RIP21.6k
// Should have dwarf #16.
312
28.2k
                    : 
X86::EIP6.53k
; // Should have dwarf #8.
313
28.2k
314
28.2k
  MCRegisterInfo *X = new MCRegisterInfo();
315
28.2k
  InitX86MCRegisterInfo(X, RA, X86_MC::getDwarfRegFlavour(TT, false),
316
28.2k
                        X86_MC::getDwarfRegFlavour(TT, true), RA);
317
28.2k
  X86_MC::initLLVMToSEHAndCVRegMapping(X);
318
28.2k
  return X;
319
28.2k
}
320
321
static MCAsmInfo *createX86MCAsmInfo(const MCRegisterInfo &MRI,
322
27.5k
                                     const Triple &TheTriple) {
323
27.5k
  bool is64Bit = TheTriple.getArch() == Triple::x86_64;
324
27.5k
325
27.5k
  MCAsmInfo *MAI;
326
27.5k
  if (TheTriple.isOSBinFormatMachO()) {
327
10.0k
    if (is64Bit)
328
8.47k
      MAI = new X86_64MCAsmInfoDarwin(TheTriple);
329
1.56k
    else
330
1.56k
      MAI = new X86MCAsmInfoDarwin(TheTriple);
331
17.4k
  } else if (TheTriple.isOSBinFormatELF()) {
332
15.5k
    // Force the use of an ELF container.
333
15.5k
    MAI = new X86ELFMCAsmInfo(TheTriple);
334
15.5k
  } else 
if (1.96k
TheTriple.isWindowsMSVCEnvironment()1.96k
||
335
1.96k
             
TheTriple.isWindowsCoreCLREnvironment()321
) {
336
1.65k
    MAI = new X86MCAsmInfoMicrosoft(TheTriple);
337
1.65k
  } else 
if (313
TheTriple.isOSCygMing()313
||
338
315
             
TheTriple.isWindowsItaniumEnvironment()38
) {
339
315
    MAI = new X86MCAsmInfoGNUCOFF(TheTriple);
340
18.4E
  } else {
341
18.4E
    // The default is ELF.
342
18.4E
    MAI = new X86ELFMCAsmInfo(TheTriple);
343
18.4E
  }
344
27.5k
345
27.5k
  // Initialize initial frame state.
346
27.5k
  // Calculate amount of bytes used for return address storing
347
27.5k
  int stackGrowth = is64Bit ? 
-821.0k
:
-46.47k
;
348
27.5k
349
27.5k
  // Initial state of the frame pointer is esp+stackGrowth.
350
27.5k
  unsigned StackPtr = is64Bit ? 
X86::RSP21.0k
:
X86::ESP6.47k
;
351
27.5k
  MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(
352
27.5k
      nullptr, MRI.getDwarfRegNum(StackPtr, true), -stackGrowth);
353
27.5k
  MAI->addInitialFrameState(Inst);
354
27.5k
355
27.5k
  // Add return address to move list
356
27.5k
  unsigned InstPtr = is64Bit ? 
X86::RIP21.0k
:
X86::EIP6.47k
;
357
27.5k
  MCCFIInstruction Inst2 = MCCFIInstruction::createOffset(
358
27.5k
      nullptr, MRI.getDwarfRegNum(InstPtr, true), stackGrowth);
359
27.5k
  MAI->addInitialFrameState(Inst2);
360
27.5k
361
27.5k
  return MAI;
362
27.5k
}
363
364
static MCInstPrinter *createX86MCInstPrinter(const Triple &T,
365
                                             unsigned SyntaxVariant,
366
                                             const MCAsmInfo &MAI,
367
                                             const MCInstrInfo &MII,
368
9.69k
                                             const MCRegisterInfo &MRI) {
369
9.69k
  if (SyntaxVariant == 0)
370
9.42k
    return new X86ATTInstPrinter(MAI, MII, MRI);
371
270
  if (SyntaxVariant == 1)
372
269
    return new X86IntelInstPrinter(MAI, MII, MRI);
373
1
  return nullptr;
374
1
}
375
376
static MCRelocationInfo *createX86MCRelocationInfo(const Triple &TheTriple,
377
40
                                                   MCContext &Ctx) {
378
40
  // Default to the stock relocation info.
379
40
  return llvm::createMCRelocationInfo(TheTriple, Ctx);
380
40
}
381
382
namespace llvm {
383
namespace X86_MC {
384
385
class X86MCInstrAnalysis : public MCInstrAnalysis {
386
  X86MCInstrAnalysis(const X86MCInstrAnalysis &) = delete;
387
  X86MCInstrAnalysis &operator=(const X86MCInstrAnalysis &) = delete;
388
1.11k
  virtual ~X86MCInstrAnalysis() = default;
389
390
public:
391
1.11k
  X86MCInstrAnalysis(const MCInstrInfo *MCII) : MCInstrAnalysis(MCII) {}
392
393
#define GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
394
#include "X86GenSubtargetInfo.inc"
395
396
  bool clearsSuperRegisters(const MCRegisterInfo &MRI, const MCInst &Inst,
397
                            APInt &Mask) const override;
398
  std::vector<std::pair<uint64_t, uint64_t>>
399
  findPltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents,
400
                 uint64_t GotSectionVA,
401
                 const Triple &TargetTriple) const override;
402
};
403
404
#define GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
405
#include "X86GenSubtargetInfo.inc"
406
407
bool X86MCInstrAnalysis::clearsSuperRegisters(const MCRegisterInfo &MRI,
408
                                              const MCInst &Inst,
409
36.6k
                                              APInt &Mask) const {
410
36.6k
  const MCInstrDesc &Desc = Info->get(Inst.getOpcode());
411
36.6k
  unsigned NumDefs = Desc.getNumDefs();
412
36.6k
  unsigned NumImplicitDefs = Desc.getNumImplicitDefs();
413
36.6k
  assert(Mask.getBitWidth() == NumDefs + NumImplicitDefs &&
414
36.6k
         "Unexpected number of bits in the mask!");
415
36.6k
416
36.6k
  bool HasVEX = (Desc.TSFlags & X86II::EncodingMask) == X86II::VEX;
417
36.6k
  bool HasEVEX = (Desc.TSFlags & X86II::EncodingMask) == X86II::EVEX;
418
36.6k
  bool HasXOP = (Desc.TSFlags & X86II::EncodingMask) == X86II::XOP;
419
36.6k
420
36.6k
  const MCRegisterClass &GR32RC = MRI.getRegClass(X86::GR32RegClassID);
421
36.6k
  const MCRegisterClass &VR128XRC = MRI.getRegClass(X86::VR128XRegClassID);
422
36.6k
  const MCRegisterClass &VR256XRC = MRI.getRegClass(X86::VR256XRegClassID);
423
36.6k
424
43.6k
  auto ClearsSuperReg = [=](unsigned RegID) {
425
43.6k
    // On X86-64, a general purpose integer register is viewed as a 64-bit
426
43.6k
    // register internal to the processor.
427
43.6k
    // An update to the lower 32 bits of a 64 bit integer register is
428
43.6k
    // architecturally defined to zero extend the upper 32 bits.
429
43.6k
    if (GR32RC.contains(RegID))
430
4.12k
      return true;
431
39.5k
432
39.5k
    // Early exit if this instruction has no vex/evex/xop prefix.
433
39.5k
    if (!HasEVEX && 
!HasVEX36.1k
&&
!HasXOP25.5k
)
434
25.1k
      return false;
435
14.4k
436
14.4k
    // All VEX and EVEX encoded instructions are defined to zero the high bits
437
14.4k
    // of the destination register up to VLMAX (i.e. the maximum vector register
438
14.4k
    // width pertaining to the instruction).
439
14.4k
    // We assume the same behavior for XOP instructions too.
440
14.4k
    return VR128XRC.contains(RegID) || 
VR256XRC.contains(RegID)7.28k
;
441
14.4k
  };
442
36.6k
443
36.6k
  Mask.clearAllBits();
444
66.4k
  for (unsigned I = 0, E = NumDefs; I < E; 
++I29.8k
) {
445
29.8k
    const MCOperand &Op = Inst.getOperand(I);
446
29.8k
    if (ClearsSuperReg(Op.getReg()))
447
15.0k
      Mask.setBit(I);
448
29.8k
  }
449
36.6k
450
50.5k
  for (unsigned I = 0, E = NumImplicitDefs; I < E; 
++I13.8k
) {
451
13.8k
    const MCPhysReg Reg = Desc.getImplicitDefs()[I];
452
13.8k
    if (ClearsSuperReg(Reg))
453
1.32k
      Mask.setBit(NumDefs + I);
454
13.8k
  }
455
36.6k
456
36.6k
  return Mask.getBoolValue();
457
36.6k
}
458
459
static std::vector<std::pair<uint64_t, uint64_t>>
460
findX86PltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents,
461
15
                  uint64_t GotPltSectionVA) {
462
15
  // Do a lightweight parsing of PLT entries.
463
15
  std::vector<std::pair<uint64_t, uint64_t>> Result;
464
714
  for (uint64_t Byte = 0, End = PltContents.size(); Byte + 6 < End; ) {
465
699
    // Recognize a jmp.
466
699
    if (PltContents[Byte] == 0xff && 
PltContents[Byte + 1] == 0xa3145
) {
467
13
      // The jmp instruction at the beginning of each PLT entry jumps to the
468
13
      // address of the base of the .got.plt section plus the immediate.
469
13
      uint32_t Imm = support::endian::read32le(PltContents.data() + Byte + 2);
470
13
      Result.push_back(
471
13
          std::make_pair(PltSectionVA + Byte, GotPltSectionVA + Imm));
472
13
      Byte += 6;
473
686
    } else if (PltContents[Byte] == 0xff && 
PltContents[Byte + 1] == 0x25132
) {
474
18
      // The jmp instruction at the beginning of each PLT entry jumps to the
475
18
      // immediate.
476
18
      uint32_t Imm = support::endian::read32le(PltContents.data() + Byte + 2);
477
18
      Result.push_back(std::make_pair(PltSectionVA + Byte, Imm));
478
18
      Byte += 6;
479
18
    } else
480
668
      Byte++;
481
699
  }
482
15
  return Result;
483
15
}
484
485
static std::vector<std::pair<uint64_t, uint64_t>>
486
22
findX86_64PltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents) {
487
22
  // Do a lightweight parsing of PLT entries.
488
22
  std::vector<std::pair<uint64_t, uint64_t>> Result;
489
807
  for (uint64_t Byte = 0, End = PltContents.size(); Byte + 6 < End; ) {
490
785
    // Recognize a jmp.
491
785
    if (PltContents[Byte] == 0xff && 
PltContents[Byte + 1] == 0x25152
) {
492
47
      // The jmp instruction at the beginning of each PLT entry jumps to the
493
47
      // address of the next instruction plus the immediate.
494
47
      uint32_t Imm = support::endian::read32le(PltContents.data() + Byte + 2);
495
47
      Result.push_back(
496
47
          std::make_pair(PltSectionVA + Byte, PltSectionVA + Byte + 6 + Imm));
497
47
      Byte += 6;
498
47
    } else
499
738
      Byte++;
500
785
  }
501
22
  return Result;
502
22
}
503
504
std::vector<std::pair<uint64_t, uint64_t>> X86MCInstrAnalysis::findPltEntries(
505
    uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents,
506
37
    uint64_t GotPltSectionVA, const Triple &TargetTriple) const {
507
37
  switch (TargetTriple.getArch()) {
508
37
    case Triple::x86:
509
15
      return findX86PltEntries(PltSectionVA, PltContents, GotPltSectionVA);
510
37
    case Triple::x86_64:
511
22
      return findX86_64PltEntries(PltSectionVA, PltContents);
512
37
    default:
513
0
      return {};
514
37
  }
515
37
}
516
517
} // end of namespace X86_MC
518
519
} // end of namespace llvm
520
521
1.11k
static MCInstrAnalysis *createX86MCInstrAnalysis(const MCInstrInfo *Info) {
522
1.11k
  return new X86_MC::X86MCInstrAnalysis(Info);
523
1.11k
}
524
525
// Force static initialization.
526
96.7k
extern "C" void LLVMInitializeX86TargetMC() {
527
193k
  for (Target *T : {&getTheX86_32Target(), &getTheX86_64Target()}) {
528
193k
    // Register the MC asm info.
529
193k
    RegisterMCAsmInfoFn X(*T, createX86MCAsmInfo);
530
193k
531
193k
    // Register the MC instruction info.
532
193k
    TargetRegistry::RegisterMCInstrInfo(*T, createX86MCInstrInfo);
533
193k
534
193k
    // Register the MC register info.
535
193k
    TargetRegistry::RegisterMCRegInfo(*T, createX86MCRegisterInfo);
536
193k
537
193k
    // Register the MC subtarget info.
538
193k
    TargetRegistry::RegisterMCSubtargetInfo(*T,
539
193k
                                            X86_MC::createX86MCSubtargetInfo);
540
193k
541
193k
    // Register the MC instruction analyzer.
542
193k
    TargetRegistry::RegisterMCInstrAnalysis(*T, createX86MCInstrAnalysis);
543
193k
544
193k
    // Register the code emitter.
545
193k
    TargetRegistry::RegisterMCCodeEmitter(*T, createX86MCCodeEmitter);
546
193k
547
193k
    // Register the obj target streamer.
548
193k
    TargetRegistry::RegisterObjectTargetStreamer(*T,
549
193k
                                                 createX86ObjectTargetStreamer);
550
193k
551
193k
    // Register the asm target streamer.
552
193k
    TargetRegistry::RegisterAsmTargetStreamer(*T, createX86AsmTargetStreamer);
553
193k
554
193k
    TargetRegistry::RegisterCOFFStreamer(*T, createX86WinCOFFStreamer);
555
193k
556
193k
    // Register the MCInstPrinter.
557
193k
    TargetRegistry::RegisterMCInstPrinter(*T, createX86MCInstPrinter);
558
193k
559
193k
    // Register the MC relocation info.
560
193k
    TargetRegistry::RegisterMCRelocationInfo(*T, createX86MCRelocationInfo);
561
193k
  }
562
96.7k
563
96.7k
  // Register the asm backend.
564
96.7k
  TargetRegistry::RegisterMCAsmBackend(getTheX86_32Target(),
565
96.7k
                                       createX86_32AsmBackend);
566
96.7k
  TargetRegistry::RegisterMCAsmBackend(getTheX86_64Target(),
567
96.7k
                                       createX86_64AsmBackend);
568
96.7k
}
569
570
unsigned llvm::getX86SubSuperRegisterOrZero(unsigned Reg, unsigned Size,
571
20.2k
                                            bool High) {
572
20.2k
  switch (Size) {
573
20.2k
  
default: return 01
;
574
20.2k
  case 8:
575
4.30k
    if (High) {
576
4.27k
      switch (Reg) {
577
4.27k
      
default: return getX86SubSuperRegisterOrZero(Reg, 64)278
;
578
4.27k
      
case X86::SIL: 1
case X86::SI: 1
case X86::ESI: 1
case X86::RSI:
579
1
        return X86::SI;
580
4
      case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
581
4
        return X86::DI;
582
4
      
case X86::BPL: 0
case X86::BP: 0
case X86::EBP: 0
case X86::RBP:
583
0
        return X86::BP;
584
0
      case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
585
0
        return X86::SP;
586
1.01k
      case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
587
1.01k
        return X86::AH;
588
1.01k
      
case X86::DH: 462
case X86::DL: 462
case X86::DX: 462
case X86::EDX: 462
case X86::RDX:
589
462
        return X86::DH;
590
2.07k
      case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
591
2.07k
        return X86::CH;
592
2.07k
      
case X86::BH: 430
case X86::BL: 430
case X86::BX: 430
case X86::EBX: 430
case X86::RBX:
593
430
        return X86::BH;
594
28
      }
595
28
    } else {
596
28
      switch (Reg) {
597
28
      
default: return 00
;
598
28
      
case X86::AH: 16
case X86::AL: 16
case X86::AX: 16
case X86::EAX: 16
case X86::RAX:
599
16
        return X86::AL;
600
16
      
case X86::DH: 2
case X86::DL: 2
case X86::DX: 2
case X86::EDX: 2
case X86::RDX:
601
2
        return X86::DL;
602
4
      case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
603
4
        return X86::CL;
604
4
      
case X86::BH: 2
case X86::BL: 2
case X86::BX: 2
case X86::EBX: 2
case X86::RBX:
605
2
        return X86::BL;
606
2
      
case X86::SIL: 1
case X86::SI: 1
case X86::ESI: 1
case X86::RSI:
607
1
        return X86::SIL;
608
1
      case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
609
1
        return X86::DIL;
610
1
      case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
611
1
        return X86::BPL;
612
1
      
case X86::SPL: 0
case X86::SP: 0
case X86::ESP: 0
case X86::RSP:
613
0
        return X86::SPL;
614
0
      case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
615
0
        return X86::R8B;
616
0
      case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
617
0
        return X86::R9B;
618
0
      case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
619
0
        return X86::R10B;
620
0
      case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
621
0
        return X86::R11B;
622
1
      case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
623
1
        return X86::R12B;
624
1
      
case X86::R13B: 0
case X86::R13W: 0
case X86::R13D: 0
case X86::R13:
625
0
        return X86::R13B;
626
0
      case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
627
0
        return X86::R14B;
628
0
      case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
629
0
        return X86::R15B;
630
0
      }
631
0
    }
632
4.29k
  case 16:
633
4.29k
    switch (Reg) {
634
4.29k
    
default: return 00
;
635
4.29k
    
case X86::AH: 1.02k
case X86::AL: 1.02k
case X86::AX: 1.02k
case X86::EAX: 1.02k
case X86::RAX:
636
1.02k
      return X86::AX;
637
1.02k
    
case X86::DH: 472
case X86::DL: 472
case X86::DX: 472
case X86::EDX: 472
case X86::RDX:
638
472
      return X86::DX;
639
2.07k
    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
640
2.07k
      return X86::CX;
641
2.07k
    
case X86::BH: 430
case X86::BL: 430
case X86::BX: 430
case X86::EBX: 430
case X86::RBX:
642
430
      return X86::BX;
643
430
    
case X86::SIL: 1
case X86::SI: 1
case X86::ESI: 1
case X86::RSI:
644
1
      return X86::SI;
645
5
    case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
646
5
      return X86::DI;
647
5
    
case X86::BPL: 0
case X86::BP: 0
case X86::EBP: 0
case X86::RBP:
648
0
      return X86::BP;
649
0
    case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
650
0
      return X86::SP;
651
25
    case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
652
25
      return X86::R8W;
653
25
    
case X86::R9B: 3
case X86::R9W: 3
case X86::R9D: 3
case X86::R9:
654
3
      return X86::R9W;
655
3
    
case X86::R10B: 0
case X86::R10W: 0
case X86::R10D: 0
case X86::R10:
656
0
      return X86::R10W;
657
9
    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
658
9
      return X86::R11W;
659
49
    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
660
49
      return X86::R12W;
661
49
    
case X86::R13B: 28
case X86::R13W: 28
case X86::R13D: 28
case X86::R13:
662
28
      return X86::R13W;
663
108
    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
664
108
      return X86::R14W;
665
108
    
case X86::R15B: 59
case X86::R15W: 59
case X86::R15D: 59
case X86::R15:
666
59
      return X86::R15W;
667
0
    }
668
10.1k
  case 32:
669
10.1k
    switch (Reg) {
670
10.1k
    
default: return 00
;
671
10.1k
    
case X86::AH: 3.49k
case X86::AL: 3.49k
case X86::AX: 3.49k
case X86::EAX: 3.49k
case X86::RAX:
672
3.49k
      return X86::EAX;
673
3.49k
    
case X86::DH: 1.12k
case X86::DL: 1.12k
case X86::DX: 1.12k
case X86::EDX: 1.12k
case X86::RDX:
674
1.12k
      return X86::EDX;
675
2.79k
    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
676
2.79k
      return X86::ECX;
677
2.79k
    
case X86::BH: 1.42k
case X86::BL: 1.42k
case X86::BX: 1.42k
case X86::EBX: 1.42k
case X86::RBX:
678
1.42k
      return X86::EBX;
679
1.42k
    
case X86::SIL: 214
case X86::SI: 214
case X86::ESI: 214
case X86::RSI:
680
214
      return X86::ESI;
681
214
    
case X86::DIL: 156
case X86::DI: 156
case X86::EDI: 156
case X86::RDI:
682
156
      return X86::EDI;
683
156
    
case X86::BPL: 46
case X86::BP: 46
case X86::EBP: 46
case X86::RBP:
684
46
      return X86::EBP;
685
46
    
case X86::SPL: 12
case X86::SP: 12
case X86::ESP: 12
case X86::RSP:
686
12
      return X86::ESP;
687
103
    case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
688
103
      return X86::R8D;
689
103
    
case X86::R9B: 52
case X86::R9W: 52
case X86::R9D: 52
case X86::R9:
690
52
      return X86::R9D;
691
52
    
case X86::R10B: 42
case X86::R10W: 42
case X86::R10D: 42
case X86::R10:
692
42
      return X86::R10D;
693
55
    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
694
55
      return X86::R11D;
695
129
    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
696
129
      return X86::R12D;
697
129
    
case X86::R13B: 78
case X86::R13W: 78
case X86::R13D: 78
case X86::R13:
698
78
      return X86::R13D;
699
285
    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
700
285
      return X86::R14D;
701
285
    
case X86::R15B: 176
case X86::R15W: 176
case X86::R15D: 176
case X86::R15:
702
176
      return X86::R15D;
703
0
    }
704
1.48k
  case 64:
705
1.48k
    switch (Reg) {
706
1.48k
    
default: return 00
;
707
1.48k
    
case X86::AH: 125
case X86::AL: 125
case X86::AX: 125
case X86::EAX: 125
case X86::RAX:
708
125
      return X86::RAX;
709
125
    
case X86::DH: 87
case X86::DL: 87
case X86::DX: 87
case X86::EDX: 87
case X86::RDX:
710
87
      return X86::RDX;
711
116
    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
712
116
      return X86::RCX;
713
146
    case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
714
146
      return X86::RBX;
715
225
    case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
716
225
      return X86::RSI;
717
225
    
case X86::DIL: 34
case X86::DI: 34
case X86::EDI: 34
case X86::RDI:
718
34
      return X86::RDI;
719
54
    case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
720
54
      return X86::RBP;
721
396
    case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
722
396
      return X86::RSP;
723
396
    
case X86::R8B: 30
case X86::R8W: 30
case X86::R8D: 30
case X86::R8:
724
30
      return X86::R8;
725
30
    
case X86::R9B: 6
case X86::R9W: 6
case X86::R9D: 6
case X86::R9:
726
6
      return X86::R9;
727
6
    
case X86::R10B: 2
case X86::R10W: 2
case X86::R10D: 2
case X86::R10:
728
2
      return X86::R10;
729
9
    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
730
9
      return X86::R11;
731
50
    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
732
50
      return X86::R12;
733
50
    
case X86::R13B: 30
case X86::R13W: 30
case X86::R13D: 30
case X86::R13:
734
30
      return X86::R13;
735
113
    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
736
113
      return X86::R14;
737
113
    
case X86::R15B: 58
case X86::R15W: 58
case X86::R15D: 58
case X86::R15:
738
58
      return X86::R15;
739
1.48k
    }
740
20.2k
  }
741
20.2k
}
742
743
19.4k
unsigned llvm::getX86SubSuperRegister(unsigned Reg, unsigned Size, bool High) {
744
19.4k
  unsigned Res = getX86SubSuperRegisterOrZero(Reg, Size, High);
745
19.4k
  assert(Res != 0 && "Unexpected register or VT");
746
19.4k
  return Res;
747
19.4k
}
748
749