Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/X86/X86CallLowering.cpp
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//===- llvm/lib/Target/X86/X86CallLowering.cpp - Call lowering ------------===//
2
//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// This file implements the lowering of LLVM calls to machine code calls for
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/// GlobalISel.
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//
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//===----------------------------------------------------------------------===//
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#include "X86CallLowering.h"
16
#include "X86CallingConv.h"
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#include "X86ISelLowering.h"
18
#include "X86InstrInfo.h"
19
#include "X86RegisterInfo.h"
20
#include "X86Subtarget.h"
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/Analysis.h"
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#include "llvm/CodeGen/CallingConvLower.h"
25
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
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#include "llvm/CodeGen/GlobalISel/Utils.h"
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#include "llvm/CodeGen/LowLevelType.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
29
#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
33
#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/CodeGen/ValueTypes.h"
38
#include "llvm/IR/Attributes.h"
39
#include "llvm/IR/DataLayout.h"
40
#include "llvm/IR/Function.h"
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#include "llvm/IR/Value.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/Support/LowLevelTypeImpl.h"
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#include "llvm/Support/MachineValueType.h"
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#include <cassert>
46
#include <cstdint>
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48
using namespace llvm;
49
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X86CallLowering::X86CallLowering(const X86TargetLowering &TLI)
51
15.2k
    : CallLowering(&TLI) {}
52
53
bool X86CallLowering::splitToValueTypes(const ArgInfo &OrigArg,
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                                        SmallVectorImpl<ArgInfo> &SplitArgs,
55
                                        const DataLayout &DL,
56
                                        MachineRegisterInfo &MRI,
57
1.30k
                                        SplitArgTy PerformArgSplit) const {
58
1.30k
  const X86TargetLowering &TLI = *getTLI<X86TargetLowering>();
59
1.30k
  LLVMContext &Context = OrigArg.Ty->getContext();
60
1.30k
61
1.30k
  SmallVector<EVT, 4> SplitVTs;
62
1.30k
  SmallVector<uint64_t, 4> Offsets;
63
1.30k
  ComputeValueVTs(TLI, DL, OrigArg.Ty, SplitVTs, &Offsets, 0);
64
1.30k
  assert(OrigArg.Regs.size() == 1 && "Can't handle multple regs yet");
65
1.30k
66
1.30k
  if (OrigArg.Ty->isVoidTy())
67
0
    return true;
68
1.30k
69
1.30k
  EVT VT = SplitVTs[0];
70
1.30k
  unsigned NumParts = TLI.getNumRegisters(Context, VT);
71
1.30k
72
1.30k
  if (NumParts == 1) {
73
1.23k
    // replace the original type ( pointer -> GPR ).
74
1.23k
    SplitArgs.emplace_back(OrigArg.Regs[0], VT.getTypeForEVT(Context),
75
1.23k
                           OrigArg.Flags, OrigArg.IsFixed);
76
1.23k
    return true;
77
1.23k
  }
78
78
79
78
  SmallVector<Register, 8> SplitRegs;
80
78
81
78
  EVT PartVT = TLI.getRegisterType(Context, VT);
82
78
  Type *PartTy = PartVT.getTypeForEVT(Context);
83
78
84
234
  for (unsigned i = 0; i < NumParts; 
++i156
) {
85
156
    ArgInfo Info =
86
156
        ArgInfo{MRI.createGenericVirtualRegister(getLLTForType(*PartTy, DL)),
87
156
                PartTy, OrigArg.Flags};
88
156
    SplitArgs.push_back(Info);
89
156
    SplitRegs.push_back(Info.Regs[0]);
90
156
  }
91
78
92
78
  PerformArgSplit(SplitRegs);
93
78
  return true;
94
78
}
95
96
namespace {
97
98
struct OutgoingValueHandler : public CallLowering::ValueHandler {
99
  OutgoingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
100
                       MachineInstrBuilder &MIB, CCAssignFn *AssignFn)
101
      : ValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB),
102
        DL(MIRBuilder.getMF().getDataLayout()),
103
473
        STI(MIRBuilder.getMF().getSubtarget<X86Subtarget>()) {}
104
105
  Register getStackAddress(uint64_t Size, int64_t Offset,
106
40
                           MachinePointerInfo &MPO) override {
107
40
    LLT p0 = LLT::pointer(0, DL.getPointerSizeInBits(0));
108
40
    LLT SType = LLT::scalar(DL.getPointerSizeInBits(0));
109
40
    Register SPReg = MRI.createGenericVirtualRegister(p0);
110
40
    MIRBuilder.buildCopy(SPReg, STI.getRegisterInfo()->getStackRegister());
111
40
112
40
    Register OffsetReg = MRI.createGenericVirtualRegister(SType);
113
40
    MIRBuilder.buildConstant(OffsetReg, Offset);
114
40
115
40
    Register AddrReg = MRI.createGenericVirtualRegister(p0);
116
40
    MIRBuilder.buildGEP(AddrReg, SPReg, OffsetReg);
117
40
118
40
    MPO = MachinePointerInfo::getStack(MIRBuilder.getMF(), Offset);
119
40
    return AddrReg;
120
40
  }
121
122
  void assignValueToReg(Register ValVReg, Register PhysReg,
123
491
                        CCValAssign &VA) override {
124
491
    MIB.addUse(PhysReg, RegState::Implicit);
125
491
126
491
    Register ExtReg;
127
491
    // If we are copying the value to a physical register with the
128
491
    // size larger than the size of the value itself - build AnyExt
129
491
    // to the size of the register first and only then do the copy.
130
491
    // The example of that would be copying from s32 to xmm0, for which
131
491
    // case ValVT == LocVT == MVT::f32. If LocSize and ValSize are not equal
132
491
    // we expect normal extendRegister mechanism to work.
133
491
    unsigned PhysRegSize =
134
491
        MRI.getTargetRegisterInfo()->getRegSizeInBits(PhysReg, MRI);
135
491
    unsigned ValSize = VA.getValVT().getSizeInBits();
136
491
    unsigned LocSize = VA.getLocVT().getSizeInBits();
137
491
    if (PhysRegSize > ValSize && 
LocSize == ValSize68
) {
138
48
      assert((PhysRegSize == 128 || PhysRegSize == 80)  && "We expect that to be 128 bit");
139
48
      auto MIB = MIRBuilder.buildAnyExt(LLT::scalar(PhysRegSize), ValVReg);
140
48
      ExtReg = MIB->getOperand(0).getReg();
141
48
    } else
142
443
      ExtReg = extendRegister(ValVReg, VA);
143
491
144
491
    MIRBuilder.buildCopy(PhysReg, ExtReg);
145
491
  }
146
147
  void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
148
40
                            MachinePointerInfo &MPO, CCValAssign &VA) override {
149
40
    Register ExtReg = extendRegister(ValVReg, VA);
150
40
    auto MMO = MIRBuilder.getMF().getMachineMemOperand(
151
40
        MPO, MachineMemOperand::MOStore, VA.getLocVT().getStoreSize(),
152
40
        /* Alignment */ 1);
153
40
    MIRBuilder.buildStore(ExtReg, Addr, *MMO);
154
40
  }
155
156
  bool assignArg(unsigned ValNo, MVT ValVT, MVT LocVT,
157
                 CCValAssign::LocInfo LocInfo,
158
531
                 const CallLowering::ArgInfo &Info, CCState &State) override {
159
531
    bool Res = AssignFn(ValNo, ValVT, LocVT, LocInfo, Info.Flags, State);
160
531
    StackSize = State.getNextStackOffset();
161
531
162
531
    static const MCPhysReg XMMArgRegs[] = {X86::XMM0, X86::XMM1, X86::XMM2,
163
531
                                           X86::XMM3, X86::XMM4, X86::XMM5,
164
531
                                           X86::XMM6, X86::XMM7};
165
531
    if (!Info.IsFixed)
166
8
      NumXMMRegs = State.getFirstUnallocated(XMMArgRegs);
167
531
168
531
    return Res;
169
531
  }
170
171
92
  uint64_t getStackSize() { return StackSize; }
172
4
  uint64_t getNumXmmRegs() { return NumXMMRegs; }
173
174
protected:
175
  MachineInstrBuilder &MIB;
176
  uint64_t StackSize = 0;
177
  const DataLayout &DL;
178
  const X86Subtarget &STI;
179
  unsigned NumXMMRegs = 0;
180
};
181
182
} // end anonymous namespace
183
184
bool X86CallLowering::lowerReturn(
185
    MachineIRBuilder &MIRBuilder, const Value *Val,
186
483
    ArrayRef<Register> VRegs) const {
187
483
  assert(((Val && !VRegs.empty()) || (!Val && VRegs.empty())) &&
188
483
         "Return value without a vreg");
189
483
  auto MIB = MIRBuilder.buildInstrNoInsert(X86::RET).addImm(0);
190
483
191
483
  if (!VRegs.empty()) {
192
427
    MachineFunction &MF = MIRBuilder.getMF();
193
427
    const Function &F = MF.getFunction();
194
427
    MachineRegisterInfo &MRI = MF.getRegInfo();
195
427
    auto &DL = MF.getDataLayout();
196
427
    LLVMContext &Ctx = Val->getType()->getContext();
197
427
    const X86TargetLowering &TLI = *getTLI<X86TargetLowering>();
198
427
199
427
    SmallVector<EVT, 4> SplitEVTs;
200
427
    ComputeValueVTs(TLI, DL, Val->getType(), SplitEVTs);
201
427
    assert(VRegs.size() == SplitEVTs.size() &&
202
427
           "For each split Type there should be exactly one VReg.");
203
427
204
427
    SmallVector<ArgInfo, 8> SplitArgs;
205
857
    for (unsigned i = 0; i < SplitEVTs.size(); 
++i430
) {
206
430
      ArgInfo CurArgInfo = ArgInfo{VRegs[i], SplitEVTs[i].getTypeForEVT(Ctx)};
207
430
      setArgFlags(CurArgInfo, AttributeList::ReturnIndex, DL, F);
208
430
      if (!splitToValueTypes(CurArgInfo, SplitArgs, DL, MRI,
209
430
                             [&](ArrayRef<Register> Regs) {
210
21
                               MIRBuilder.buildUnmerge(Regs, VRegs[i]);
211
21
                             }))
212
0
        return false;
213
430
    }
214
427
215
427
    OutgoingValueHandler Handler(MIRBuilder, MRI, MIB, RetCC_X86);
216
427
    if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
217
0
      return false;
218
483
  }
219
483
220
483
  MIRBuilder.insertInstr(MIB);
221
483
  return true;
222
483
}
223
224
namespace {
225
226
struct IncomingValueHandler : public CallLowering::ValueHandler {
227
  IncomingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
228
                       CCAssignFn *AssignFn)
229
      : ValueHandler(MIRBuilder, MRI, AssignFn),
230
456
        DL(MIRBuilder.getMF().getDataLayout()) {}
231
232
710
  bool isArgumentHandler() const override { return true; }
233
234
  Register getStackAddress(uint64_t Size, int64_t Offset,
235
145
                           MachinePointerInfo &MPO) override {
236
145
    auto &MFI = MIRBuilder.getMF().getFrameInfo();
237
145
    int FI = MFI.CreateFixedObject(Size, Offset, true);
238
145
    MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
239
145
240
145
    unsigned AddrReg = MRI.createGenericVirtualRegister(
241
145
        LLT::pointer(0, DL.getPointerSizeInBits(0)));
242
145
    MIRBuilder.buildFrameIndex(AddrReg, FI);
243
145
    return AddrReg;
244
145
  }
245
246
  void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
247
145
                            MachinePointerInfo &MPO, CCValAssign &VA) override {
248
145
    auto MMO = MIRBuilder.getMF().getMachineMemOperand(
249
145
        MPO, MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant, Size,
250
145
        1);
251
145
    MIRBuilder.buildLoad(ValVReg, Addr, *MMO);
252
145
  }
253
254
  void assignValueToReg(Register ValVReg, Register PhysReg,
255
710
                        CCValAssign &VA) override {
256
710
    markPhysRegUsed(PhysReg);
257
710
258
710
    switch (VA.getLocInfo()) {
259
710
    default: {
260
630
      // If we are copying the value from a physical register with the
261
630
      // size larger than the size of the value itself - build the copy
262
630
      // of the phys reg first and then build the truncation of that copy.
263
630
      // The example of that would be copying from xmm0 to s32, for which
264
630
      // case ValVT == LocVT == MVT::f32. If LocSize and ValSize are not equal
265
630
      // we expect this to be handled in SExt/ZExt/AExt case.
266
630
      unsigned PhysRegSize =
267
630
          MRI.getTargetRegisterInfo()->getRegSizeInBits(PhysReg, MRI);
268
630
      unsigned ValSize = VA.getValVT().getSizeInBits();
269
630
      unsigned LocSize = VA.getLocVT().getSizeInBits();
270
630
      if (PhysRegSize > ValSize && 
LocSize == ValSize74
) {
271
74
        auto Copy = MIRBuilder.buildCopy(LLT::scalar(PhysRegSize), PhysReg);
272
74
        MIRBuilder.buildTrunc(ValVReg, Copy);
273
74
        return;
274
74
      }
275
556
276
556
      MIRBuilder.buildCopy(ValVReg, PhysReg);
277
556
      break;
278
556
    }
279
556
    case CCValAssign::LocInfo::SExt:
280
80
    case CCValAssign::LocInfo::ZExt:
281
80
    case CCValAssign::LocInfo::AExt: {
282
80
      auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg);
283
80
      MIRBuilder.buildTrunc(ValVReg, Copy);
284
80
      break;
285
80
    }
286
710
    }
287
710
  }
288
289
  /// How the physical register gets marked varies between formal
290
  /// parameters (it's a basic-block live-in), and a call instruction
291
  /// (it's an implicit-def of the BL).
292
  virtual void markPhysRegUsed(unsigned PhysReg) = 0;
293
294
protected:
295
  const DataLayout &DL;
296
};
297
298
struct FormalArgHandler : public IncomingValueHandler {
299
  FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
300
                   CCAssignFn *AssignFn)
301
446
      : IncomingValueHandler(MIRBuilder, MRI, AssignFn) {}
302
303
696
  void markPhysRegUsed(unsigned PhysReg) override {
304
696
    MIRBuilder.getMBB().addLiveIn(PhysReg);
305
696
  }
306
};
307
308
struct CallReturnHandler : public IncomingValueHandler {
309
  CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
310
                    CCAssignFn *AssignFn, MachineInstrBuilder &MIB)
311
10
      : IncomingValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {}
312
313
14
  void markPhysRegUsed(unsigned PhysReg) override {
314
14
    MIB.addDef(PhysReg, RegState::Implicit);
315
14
  }
316
317
protected:
318
  MachineInstrBuilder &MIB;
319
};
320
321
} // end anonymous namespace
322
323
bool X86CallLowering::lowerFormalArguments(
324
    MachineIRBuilder &MIRBuilder, const Function &F,
325
481
    ArrayRef<ArrayRef<Register>> VRegs) const {
326
481
  if (F.arg_empty())
327
35
    return true;
328
446
329
446
  // TODO: handle variadic function
330
446
  if (F.isVarArg())
331
0
    return false;
332
446
333
446
  MachineFunction &MF = MIRBuilder.getMF();
334
446
  MachineRegisterInfo &MRI = MF.getRegInfo();
335
446
  auto DL = MF.getDataLayout();
336
446
337
446
  SmallVector<ArgInfo, 8> SplitArgs;
338
446
  unsigned Idx = 0;
339
792
  for (auto &Arg : F.args()) {
340
792
341
792
    // TODO: handle not simple cases.
342
792
    if (Arg.hasAttribute(Attribute::ByVal) ||
343
792
        Arg.hasAttribute(Attribute::InReg) ||
344
792
        Arg.hasAttribute(Attribute::StructRet) ||
345
792
        Arg.hasAttribute(Attribute::SwiftSelf) ||
346
792
        Arg.hasAttribute(Attribute::SwiftError) ||
347
792
        Arg.hasAttribute(Attribute::Nest) || VRegs[Idx].size() > 1)
348
0
      return false;
349
792
350
792
    ArgInfo OrigArg(VRegs[Idx], Arg.getType());
351
792
    setArgFlags(OrigArg, Idx + AttributeList::FirstArgIndex, DL, F);
352
792
    if (!splitToValueTypes(OrigArg, SplitArgs, DL, MRI,
353
792
                           [&](ArrayRef<Register> Regs) {
354
49
                             MIRBuilder.buildMerge(VRegs[Idx][0], Regs);
355
49
                           }))
356
0
      return false;
357
792
    Idx++;
358
792
  }
359
446
360
446
  MachineBasicBlock &MBB = MIRBuilder.getMBB();
361
446
  if (!MBB.empty())
362
20
    MIRBuilder.setInstr(*MBB.begin());
363
446
364
446
  FormalArgHandler Handler(MIRBuilder, MRI, CC_X86);
365
446
  if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
366
0
    return false;
367
446
368
446
  // Move back to the end of the basic block.
369
446
  MIRBuilder.setMBB(MBB);
370
446
371
446
  return true;
372
446
}
373
374
bool X86CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
375
                                CallingConv::ID CallConv,
376
                                const MachineOperand &Callee,
377
                                const ArgInfo &OrigRet,
378
47
                                ArrayRef<ArgInfo> OrigArgs) const {
379
47
  MachineFunction &MF = MIRBuilder.getMF();
380
47
  const Function &F = MF.getFunction();
381
47
  MachineRegisterInfo &MRI = MF.getRegInfo();
382
47
  auto &DL = F.getParent()->getDataLayout();
383
47
  const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
384
47
  const TargetInstrInfo &TII = *STI.getInstrInfo();
385
47
  auto TRI = STI.getRegisterInfo();
386
47
387
47
  // Handle only Linux C, X86_64_SysV calling conventions for now.
388
47
  if (!STI.isTargetLinux() ||
389
47
      !(CallConv == CallingConv::C || 
CallConv == CallingConv::X86_64_SysV0
))
390
0
    return false;
391
47
392
47
  unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
393
47
  auto CallSeqStart = MIRBuilder.buildInstr(AdjStackDown);
394
47
395
47
  // Create a temporarily-floating call instruction so we can add the implicit
396
47
  // uses of arg registers.
397
47
  bool Is64Bit = STI.is64Bit();
398
47
  unsigned CallOpc = Callee.isReg()
399
47
                         ? 
(Is64Bit 4
?
X86::CALL64r2
:
X86::CALL32r2
)
400
47
                         : 
(Is64Bit 43
?
X86::CALL64pcrel3223
:
X86::CALLpcrel3220
);
401
47
402
47
  auto MIB = MIRBuilder.buildInstrNoInsert(CallOpc).add(Callee).addRegMask(
403
47
      TRI->getCallPreservedMask(MF, CallConv));
404
47
405
47
  SmallVector<ArgInfo, 8> SplitArgs;
406
78
  for (const auto &OrigArg : OrigArgs) {
407
78
408
78
    // TODO: handle not simple cases.
409
78
    if (OrigArg.Flags.isByVal())
410
1
      return false;
411
77
412
77
    if (OrigArg.Regs.size() > 1)
413
0
      return false;
414
77
415
77
    if (!splitToValueTypes(OrigArg, SplitArgs, DL, MRI,
416
77
                           [&](ArrayRef<Register> Regs) {
417
4
                             MIRBuilder.buildUnmerge(Regs, OrigArg.Regs[0]);
418
4
                           }))
419
0
      return false;
420
77
  }
421
47
  // Do the actual argument marshalling.
422
47
  OutgoingValueHandler Handler(MIRBuilder, MRI, MIB, CC_X86);
423
46
  if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
424
0
    return false;
425
46
426
46
  bool IsFixed = OrigArgs.empty() ? 
true10
:
OrigArgs.back().IsFixed36
;
427
46
  if (STI.is64Bit() && 
!IsFixed24
&&
!STI.isCallingConvWin64(CallConv)4
) {
428
4
    // From AMD64 ABI document:
429
4
    // For calls that may call functions that use varargs or stdargs
430
4
    // (prototype-less calls or calls to functions containing ellipsis (...) in
431
4
    // the declaration) %al is used as hidden argument to specify the number
432
4
    // of SSE registers used. The contents of %al do not need to match exactly
433
4
    // the number of registers, but must be an ubound on the number of SSE
434
4
    // registers used and is in the range 0 - 8 inclusive.
435
4
436
4
    MIRBuilder.buildInstr(X86::MOV8ri)
437
4
        .addDef(X86::AL)
438
4
        .addImm(Handler.getNumXmmRegs());
439
4
    MIB.addUse(X86::AL, RegState::Implicit);
440
4
  }
441
46
442
46
  // Now we can add the actual call instruction to the correct basic block.
443
46
  MIRBuilder.insertInstr(MIB);
444
46
445
46
  // If Callee is a reg, since it is used by a target specific
446
46
  // instruction, it must have a register class matching the
447
46
  // constraint of that instruction.
448
46
  if (Callee.isReg())
449
4
    MIB->getOperand(0).setReg(constrainOperandRegClass(
450
4
        MF, *TRI, MRI, *MF.getSubtarget().getInstrInfo(),
451
4
        *MF.getSubtarget().getRegBankInfo(), *MIB, MIB->getDesc(), Callee, 0));
452
46
453
46
  // Finally we can copy the returned value back into its virtual-register. In
454
46
  // symmetry with the arguments, the physical register must be an
455
46
  // implicit-define of the call instruction.
456
46
457
46
  if (!OrigRet.Ty->isVoidTy()) {
458
10
    if (OrigRet.Regs.size() > 1)
459
0
      return false;
460
10
461
10
    SplitArgs.clear();
462
10
    SmallVector<Register, 8> NewRegs;
463
10
464
10
    if (!splitToValueTypes(OrigRet, SplitArgs, DL, MRI,
465
10
                           [&](ArrayRef<Register> Regs) {
466
4
                             NewRegs.assign(Regs.begin(), Regs.end());
467
4
                           }))
468
0
      return false;
469
10
470
10
    CallReturnHandler Handler(MIRBuilder, MRI, RetCC_X86, MIB);
471
10
    if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
472
0
      return false;
473
10
474
10
    if (!NewRegs.empty())
475
4
      MIRBuilder.buildMerge(OrigRet.Regs[0], NewRegs);
476
10
  }
477
46
478
46
  CallSeqStart.addImm(Handler.getStackSize())
479
46
      .addImm(0 /* see getFrameTotalSize */)
480
46
      .addImm(0 /* see getFrameAdjustment */);
481
46
482
46
  unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
483
46
  MIRBuilder.buildInstr(AdjStackUp)
484
46
      .addImm(Handler.getStackSize())
485
46
      .addImm(0 /* NumBytesForCalleeToPop */);
486
46
487
46
  return true;
488
46
}