Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/X86/X86FixupLEAs.cpp
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Source (jump to first uncovered line)
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//===-- X86FixupLEAs.cpp - use or replace LEA instructions -----------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file defines the pass that finds instructions that can be
10
// re-written as LEA instructions in order to reduce pipeline delays.
11
// It replaces LEAs with ADD/INC/DEC when that is better for size/speed.
12
//
13
//===----------------------------------------------------------------------===//
14
15
#include "X86.h"
16
#include "X86InstrInfo.h"
17
#include "X86Subtarget.h"
18
#include "llvm/ADT/Statistic.h"
19
#include "llvm/CodeGen/MachineFunctionPass.h"
20
#include "llvm/CodeGen/MachineInstrBuilder.h"
21
#include "llvm/CodeGen/Passes.h"
22
#include "llvm/CodeGen/TargetSchedule.h"
23
#include "llvm/Support/Debug.h"
24
#include "llvm/Support/raw_ostream.h"
25
using namespace llvm;
26
27
146k
#define FIXUPLEA_DESC "X86 LEA Fixup"
28
#define FIXUPLEA_NAME "x86-fixup-LEAs"
29
30
#define DEBUG_TYPE FIXUPLEA_NAME
31
32
STATISTIC(NumLEAs, "Number of LEA instructions created");
33
34
namespace {
35
class FixupLEAPass : public MachineFunctionPass {
36
  enum RegUsageState { RU_NotUsed, RU_Write, RU_Read };
37
38
  /// Given a machine register, look for the instruction
39
  /// which writes it in the current basic block. If found,
40
  /// try to replace it with an equivalent LEA instruction.
41
  /// If replacement succeeds, then also process the newly created
42
  /// instruction.
43
  void seekLEAFixup(MachineOperand &p, MachineBasicBlock::iterator &I,
44
                    MachineBasicBlock &MBB);
45
46
  /// Given a memory access or LEA instruction
47
  /// whose address mode uses a base and/or index register, look for
48
  /// an opportunity to replace the instruction which sets the base or index
49
  /// register with an equivalent LEA instruction.
50
  void processInstruction(MachineBasicBlock::iterator &I,
51
                          MachineBasicBlock &MBB);
52
53
  /// Given a LEA instruction which is unprofitable
54
  /// on SlowLEA targets try to replace it with an equivalent ADD instruction.
55
  void processInstructionForSlowLEA(MachineBasicBlock::iterator &I,
56
                                    MachineBasicBlock &MBB);
57
58
  /// Given a LEA instruction which is unprofitable
59
  /// on SNB+ try to replace it with other instructions.
60
  /// According to Intel's Optimization Reference Manual:
61
  /// " For LEA instructions with three source operands and some specific
62
  ///   situations, instruction latency has increased to 3 cycles, and must
63
  ///   dispatch via port 1:
64
  /// - LEA that has all three source operands: base, index, and offset
65
  /// - LEA that uses base and index registers where the base is EBP, RBP,
66
  ///   or R13
67
  /// - LEA that uses RIP relative addressing mode
68
  /// - LEA that uses 16-bit addressing mode "
69
  /// This function currently handles the first 2 cases only.
70
  MachineInstr *processInstrForSlow3OpLEA(MachineInstr &MI,
71
                                          MachineBasicBlock &MBB);
72
73
  /// Look for LEAs that are really two address LEAs that we might be able to
74
  /// turn into regular ADD instructions.
75
  bool optTwoAddrLEA(MachineBasicBlock::iterator &I,
76
                     MachineBasicBlock &MBB, bool OptIncDec,
77
                     bool UseLEAForSP) const;
78
79
  /// Determine if an instruction references a machine register
80
  /// and, if so, whether it reads or writes the register.
81
  RegUsageState usesRegister(MachineOperand &p, MachineBasicBlock::iterator I);
82
83
  /// Step backwards through a basic block, looking
84
  /// for an instruction which writes a register within
85
  /// a maximum of INSTR_DISTANCE_THRESHOLD instruction latency cycles.
86
  MachineBasicBlock::iterator searchBackwards(MachineOperand &p,
87
                                              MachineBasicBlock::iterator &I,
88
                                              MachineBasicBlock &MBB);
89
90
  /// if an instruction can be converted to an
91
  /// equivalent LEA, insert the new instruction into the basic block
92
  /// and return a pointer to it. Otherwise, return zero.
93
  MachineInstr *postRAConvertToLEA(MachineBasicBlock &MBB,
94
                                   MachineBasicBlock::iterator &MBBI) const;
95
96
public:
97
  static char ID;
98
99
146k
  StringRef getPassName() const override { return FIXUPLEA_DESC; }
100
101
11.4k
  FixupLEAPass() : MachineFunctionPass(ID) { }
102
103
  /// Loop over all of the basic blocks,
104
  /// replacing instructions by equivalent LEA instructions
105
  /// if needed and when possible.
106
  bool runOnMachineFunction(MachineFunction &MF) override;
107
108
  // This pass runs after regalloc and doesn't support VReg operands.
109
11.3k
  MachineFunctionProperties getRequiredProperties() const override {
110
11.3k
    return MachineFunctionProperties().set(
111
11.3k
        MachineFunctionProperties::Property::NoVRegs);
112
11.3k
  }
113
114
private:
115
  TargetSchedModel TSM;
116
  const X86InstrInfo *TII;
117
  const X86RegisterInfo *TRI;
118
};
119
}
120
121
char FixupLEAPass::ID = 0;
122
123
INITIALIZE_PASS(FixupLEAPass, FIXUPLEA_NAME, FIXUPLEA_DESC, false, false)
124
125
MachineInstr *
126
FixupLEAPass::postRAConvertToLEA(MachineBasicBlock &MBB,
127
64
                                 MachineBasicBlock::iterator &MBBI) const {
128
64
  MachineInstr &MI = *MBBI;
129
64
  switch (MI.getOpcode()) {
130
64
  case X86::MOV32rr:
131
1
  case X86::MOV64rr: {
132
1
    const MachineOperand &Src = MI.getOperand(1);
133
1
    const MachineOperand &Dest = MI.getOperand(0);
134
1
    MachineInstr *NewMI =
135
1
        BuildMI(MBB, MBBI, MI.getDebugLoc(),
136
1
                TII->get(MI.getOpcode() == X86::MOV32rr ? 
X86::LEA32r0
137
1
                                                        : X86::LEA64r))
138
1
            .add(Dest)
139
1
            .add(Src)
140
1
            .addImm(1)
141
1
            .addReg(0)
142
1
            .addImm(0)
143
1
            .addReg(0);
144
1
    return NewMI;
145
63
  }
146
63
  }
147
63
148
63
  if (!MI.isConvertibleTo3Addr())
149
50
    return nullptr;
150
13
151
13
  switch (MI.getOpcode()) {
152
13
  default:
153
3
    // Only convert instructions that we've verified are safe.
154
3
    return nullptr;
155
13
  case X86::ADD64ri32:
156
4
  case X86::ADD64ri8:
157
4
  case X86::ADD64ri32_DB:
158
4
  case X86::ADD64ri8_DB:
159
4
  case X86::ADD32ri:
160
4
  case X86::ADD32ri8:
161
4
  case X86::ADD32ri_DB:
162
4
  case X86::ADD32ri8_DB:
163
4
    if (!MI.getOperand(2).isImm()) {
164
0
      // convertToThreeAddress will call getImm()
165
0
      // which requires isImm() to be true
166
0
      return nullptr;
167
0
    }
168
4
    break;
169
6
  case X86::SHL64ri:
170
6
  case X86::SHL32ri:
171
6
  case X86::INC64r:
172
6
  case X86::INC32r:
173
6
  case X86::DEC64r:
174
6
  case X86::DEC32r:
175
6
  case X86::ADD64rr:
176
6
  case X86::ADD64rr_DB:
177
6
  case X86::ADD32rr:
178
6
  case X86::ADD32rr_DB:
179
6
    // These instructions are all fine to convert.
180
6
    break;
181
10
  }
182
10
  MachineFunction::iterator MFI = MBB.getIterator();
183
10
  return TII->convertToThreeAddress(MFI, MI, nullptr);
184
10
}
185
186
11.4k
FunctionPass *llvm::createX86FixupLEAs() { return new FixupLEAPass(); }
187
188
2.55M
static bool isLEA(unsigned Opcode) {
189
2.55M
  return Opcode == X86::LEA32r || 
Opcode == X86::LEA64r2.54M
||
190
2.55M
         
Opcode == X86::LEA64_32r2.45M
;
191
2.55M
}
192
193
135k
bool FixupLEAPass::runOnMachineFunction(MachineFunction &MF) {
194
135k
  if (skipFunction(MF.getFunction()))
195
196
    return false;
196
135k
197
135k
  const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>();
198
135k
  bool IsSlowLEA = ST.slowLEA();
199
135k
  bool IsSlow3OpsLEA = ST.slow3OpsLEA();
200
135k
  bool LEAUsesAG = ST.LEAusesAG();
201
135k
202
135k
  bool OptIncDec = !ST.slowIncDec() || 
MF.getFunction().hasOptSize()3.59k
;
203
135k
  bool UseLEAForSP = ST.useLeaForSP();
204
135k
205
135k
  TSM.init(&ST);
206
135k
  TII = ST.getInstrInfo();
207
135k
  TRI = ST.getRegisterInfo();
208
135k
209
135k
  LLVM_DEBUG(dbgs() << "Start X86FixupLEAs\n";);
210
384k
  for (MachineBasicBlock &MBB : MF) {
211
384k
    // First pass. Try to remove or optimize existing LEAs.
212
2.94M
    for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); 
++I2.55M
) {
213
2.55M
      if (!isLEA(I->getOpcode()))
214
2.44M
        continue;
215
108k
216
108k
      if (optTwoAddrLEA(I, MBB, OptIncDec, UseLEAForSP))
217
1.47k
        continue;
218
106k
219
106k
      if (IsSlowLEA) {
220
89
        processInstructionForSlowLEA(I, MBB);
221
106k
      } else if (IsSlow3OpsLEA) {
222
29.6k
        if (auto *NewMI = processInstrForSlow3OpLEA(*I, MBB)) {
223
1.72k
          MBB.erase(I);
224
1.72k
          I = NewMI;
225
1.72k
        }
226
29.6k
      }
227
106k
    }
228
384k
229
384k
    // Second pass for creating LEAs. This may reverse some of the
230
384k
    // transformations above.
231
384k
    if (LEAUsesAG) {
232
1.17k
      for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); 
++I1.02k
)
233
1.02k
        processInstruction(I, MBB);
234
148
    }
235
384k
  }
236
135k
237
135k
  LLVM_DEBUG(dbgs() << "End X86FixupLEAs\n";);
238
135k
239
135k
  return true;
240
135k
}
241
242
FixupLEAPass::RegUsageState
243
1.48k
FixupLEAPass::usesRegister(MachineOperand &p, MachineBasicBlock::iterator I) {
244
1.48k
  RegUsageState RegUsage = RU_NotUsed;
245
1.48k
  MachineInstr &MI = *I;
246
1.48k
247
8.08k
  for (unsigned i = 0; i < MI.getNumOperands(); 
++i6.60k
) {
248
6.66k
    MachineOperand &opnd = MI.getOperand(i);
249
6.66k
    if (opnd.isReg() && 
opnd.getReg() == p.getReg()4.65k
) {
250
1.21k
      if (opnd.isDef())
251
64
        return RU_Write;
252
1.15k
      RegUsage = RU_Read;
253
1.15k
    }
254
6.66k
  }
255
1.48k
  
return RegUsage1.42k
;
256
1.48k
}
257
258
/// getPreviousInstr - Given a reference to an instruction in a basic
259
/// block, return a reference to the previous instruction in the block,
260
/// wrapping around to the last instruction of the block if the block
261
/// branches to itself.
262
static inline bool getPreviousInstr(MachineBasicBlock::iterator &I,
263
1.94k
                                    MachineBasicBlock &MBB) {
264
1.94k
  if (I == MBB.begin()) {
265
252
    if (MBB.isPredecessor(&MBB)) {
266
45
      I = --MBB.end();
267
45
      return true;
268
45
    } else
269
207
      return false;
270
1.68k
  }
271
1.68k
  --I;
272
1.68k
  return true;
273
1.68k
}
274
275
MachineBasicBlock::iterator
276
FixupLEAPass::searchBackwards(MachineOperand &p, MachineBasicBlock::iterator &I,
277
516
                              MachineBasicBlock &MBB) {
278
516
  int InstrDistance = 1;
279
516
  MachineBasicBlock::iterator CurInst;
280
516
  static const int INSTR_DISTANCE_THRESHOLD = 5;
281
516
282
516
  CurInst = I;
283
516
  bool Found;
284
516
  Found = getPreviousInstr(CurInst, MBB);
285
1.94k
  while (Found && 
I != CurInst1.73k
) {
286
1.71k
    if (CurInst->isCall() || 
CurInst->isInlineAsm()1.68k
)
287
41
      break;
288
1.67k
    if (InstrDistance > INSTR_DISTANCE_THRESHOLD)
289
184
      break; // too far back to make a difference
290
1.48k
    if (usesRegister(p, CurInst) == RU_Write) {
291
64
      return CurInst;
292
64
    }
293
1.42k
    InstrDistance += TSM.computeInstrLatency(&*CurInst);
294
1.42k
    Found = getPreviousInstr(CurInst, MBB);
295
1.42k
  }
296
516
  
return MachineBasicBlock::iterator()452
;
297
516
}
298
299
31.4k
static inline bool isInefficientLEAReg(unsigned Reg) {
300
31.4k
  return Reg == X86::EBP || 
Reg == X86::RBP31.4k
||
301
31.4k
         
Reg == X86::R13D24.1k
||
Reg == X86::R1324.1k
;
302
31.4k
}
303
304
7.59k
static inline bool isRegOperand(const MachineOperand &Op) {
305
7.59k
  return Op.isReg() && Op.getReg() != X86::NoRegister;
306
7.59k
}
307
308
/// Returns true if this LEA uses base an index registers, and the base register
309
/// is known to be inefficient for the subtarget.
310
// TODO: use a variant scheduling class to model the latency profile
311
// of LEA instructions, and implement this logic as a scheduling predicate.
312
static inline bool hasInefficientLEABaseReg(const MachineOperand &Base,
313
27.9k
                                            const MachineOperand &Index) {
314
27.9k
  return Base.isReg() && isInefficientLEAReg(Base.getReg()) &&
315
27.9k
         
isRegOperand(Index)7.59k
;
316
27.9k
}
317
318
1.69k
static inline bool hasLEAOffset(const MachineOperand &Offset) {
319
1.69k
  return (Offset.isImm() && Offset.getImm() != 0) || 
Offset.isGlobal()46
;
320
1.69k
}
321
322
2.13k
static inline unsigned getADDrrFromLEA(unsigned LEAOpcode) {
323
2.13k
  switch (LEAOpcode) {
324
2.13k
  default:
325
0
    llvm_unreachable("Unexpected LEA instruction");
326
2.13k
  case X86::LEA32r:
327
451
  case X86::LEA64_32r:
328
451
    return X86::ADD32rr;
329
1.68k
  case X86::LEA64r:
330
1.68k
    return X86::ADD64rr;
331
2.13k
  }
332
2.13k
}
333
334
static inline unsigned getADDriFromLEA(unsigned LEAOpcode,
335
2.40k
                                       const MachineOperand &Offset) {
336
2.40k
  bool IsInt8 = Offset.isImm() && isInt<8>(Offset.getImm());
337
2.40k
  switch (LEAOpcode) {
338
2.40k
  default:
339
0
    llvm_unreachable("Unexpected LEA instruction");
340
2.40k
  case X86::LEA32r:
341
423
  case X86::LEA64_32r:
342
423
    return IsInt8 ? 
X86::ADD32ri8247
:
X86::ADD32ri176
;
343
1.98k
  case X86::LEA64r:
344
1.98k
    return IsInt8 ? 
X86::ADD64ri81.68k
:
X86::ADD64ri32293
;
345
2.40k
  }
346
2.40k
}
347
348
406
static inline unsigned getINCDECFromLEA(unsigned LEAOpcode, bool IsINC) {
349
406
  switch (LEAOpcode) {
350
406
  default:
351
0
    llvm_unreachable("Unexpected LEA instruction");
352
406
  case X86::LEA32r:
353
237
  case X86::LEA64_32r:
354
237
    return IsINC ? 
X86::INC32r198
:
X86::DEC32r39
;
355
237
  case X86::LEA64r:
356
169
    return IsINC ? 
X86::INC64r78
:
X86::DEC64r91
;
357
406
  }
358
406
}
359
360
bool FixupLEAPass::optTwoAddrLEA(MachineBasicBlock::iterator &I,
361
                                 MachineBasicBlock &MBB, bool OptIncDec,
362
108k
                                 bool UseLEAForSP) const {
363
108k
  MachineInstr &MI = *I;
364
108k
365
108k
  const MachineOperand &Base =    MI.getOperand(1 + X86::AddrBaseReg);
366
108k
  const MachineOperand &Scale =   MI.getOperand(1 + X86::AddrScaleAmt);
367
108k
  const MachineOperand &Index =   MI.getOperand(1 + X86::AddrIndexReg);
368
108k
  const MachineOperand &Disp =    MI.getOperand(1 + X86::AddrDisp);
369
108k
  const MachineOperand &Segment = MI.getOperand(1 + X86::AddrSegmentReg);
370
108k
371
108k
  if (
Segment.getReg() != 0108k
|| !Disp.isImm() ||
Scale.getImm() > 163.4k
||
372
108k
      
!TII->isSafeToClobberEFLAGS(MBB, I)55.7k
)
373
55.8k
    return false;
374
52.4k
375
52.4k
  unsigned DestReg  = MI.getOperand(0).getReg();
376
52.4k
  unsigned BaseReg  = Base.getReg();
377
52.4k
  unsigned IndexReg = Index.getReg();
378
52.4k
379
52.4k
  // Don't change stack adjustment LEAs.
380
52.4k
  if (UseLEAForSP && 
(37
DestReg == X86::ESP37
||
DestReg == X86::RSP15
))
381
28
    return false;
382
52.4k
383
52.4k
  // LEA64_32 has 64-bit operands but 32-bit result.
384
52.4k
  if (MI.getOpcode() == X86::LEA64_32r) {
385
3.73k
    if (BaseReg != 0)
386
3.73k
      BaseReg = TRI->getSubReg(BaseReg, X86::sub_32bit);
387
3.73k
    if (IndexReg != 0)
388
1.40k
      IndexReg = TRI->getSubReg(IndexReg, X86::sub_32bit);
389
3.73k
  }
390
52.4k
391
52.4k
  MachineInstr *NewMI = nullptr;
392
52.4k
393
52.4k
  // Look for lea(%reg1, %reg2), %reg1 or lea(%reg2, %reg1), %reg1
394
52.4k
  // which can be turned into add %reg2, %reg1
395
52.4k
  if (
BaseReg != 052.4k
&& IndexReg != 0 &&
Disp.getImm() == 07.60k
&&
396
52.4k
      
(3.11k
DestReg == BaseReg3.11k
||
DestReg == IndexReg2.91k
)) {
397
402
    unsigned NewOpcode = getADDrrFromLEA(MI.getOpcode());
398
402
    if (DestReg != BaseReg)
399
203
      std::swap(BaseReg, IndexReg);
400
402
401
402
    if (MI.getOpcode() == X86::LEA64_32r) {
402
74
      // TODO: Do we need the super register implicit use?
403
74
      NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)
404
74
        .addReg(BaseReg).addReg(IndexReg)
405
74
        .addReg(Base.getReg(), RegState::Implicit)
406
74
        .addReg(Index.getReg(), RegState::Implicit);
407
328
    } else {
408
328
      NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)
409
328
        .addReg(BaseReg).addReg(IndexReg);
410
328
    }
411
52.0k
  } else if (DestReg == BaseReg && 
IndexReg == 01.85k
) {
412
1.07k
    // This is an LEA with only a base register and a displacement,
413
1.07k
    // We can use ADDri or INC/DEC.
414
1.07k
415
1.07k
    // Does this LEA have one these forms:
416
1.07k
    // lea  %reg, 1(%reg)
417
1.07k
    // lea  %reg, -1(%reg)
418
1.07k
    if (OptIncDec && 
(1.07k
Disp.getImm() == 11.07k
||
Disp.getImm() == -1797
)) {
419
406
      bool IsINC = Disp.getImm() == 1;
420
406
      unsigned NewOpcode = getINCDECFromLEA(MI.getOpcode(), IsINC);
421
406
422
406
      if (MI.getOpcode() == X86::LEA64_32r) {
423
132
        // TODO: Do we need the super register implicit use?
424
132
        NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)
425
132
          .addReg(BaseReg).addReg(Base.getReg(), RegState::Implicit);
426
274
      } else {
427
274
        NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)
428
274
          .addReg(BaseReg);
429
274
      }
430
669
    } else {
431
669
      unsigned NewOpcode = getADDriFromLEA(MI.getOpcode(), Disp);
432
669
      if (MI.getOpcode() == X86::LEA64_32r) {
433
85
        // TODO: Do we need the super register implicit use?
434
85
        NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)
435
85
          .addReg(BaseReg).addImm(Disp.getImm())
436
85
          .addReg(Base.getReg(), RegState::Implicit);
437
584
      } else {
438
584
        NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)
439
584
          .addReg(BaseReg).addImm(Disp.getImm());
440
584
      }
441
669
    }
442
1.07k
  } else
443
50.9k
    return false;
444
1.47k
445
1.47k
  MBB.erase(I);
446
1.47k
  I = NewMI;
447
1.47k
  return true;
448
1.47k
}
449
450
void FixupLEAPass::processInstruction(MachineBasicBlock::iterator &I,
451
1.03k
                                      MachineBasicBlock &MBB) {
452
1.03k
  // Process a load, store, or LEA instruction.
453
1.03k
  MachineInstr &MI = *I;
454
1.03k
  const MCInstrDesc &Desc = MI.getDesc();
455
1.03k
  int AddrOffset = X86II::getMemoryOperandNo(Desc.TSFlags);
456
1.03k
  if (AddrOffset >= 0) {
457
297
    AddrOffset += X86II::getOperandBias(Desc);
458
297
    MachineOperand &p = MI.getOperand(AddrOffset + X86::AddrBaseReg);
459
297
    if (p.isReg() && p.getReg() != X86::ESP) {
460
219
      seekLEAFixup(p, I, MBB);
461
219
    }
462
297
    MachineOperand &q = MI.getOperand(AddrOffset + X86::AddrIndexReg);
463
297
    if (q.isReg() && q.getReg() != X86::ESP) {
464
297
      seekLEAFixup(q, I, MBB);
465
297
    }
466
297
  }
467
1.03k
}
468
469
void FixupLEAPass::seekLEAFixup(MachineOperand &p,
470
                                MachineBasicBlock::iterator &I,
471
516
                                MachineBasicBlock &MBB) {
472
516
  MachineBasicBlock::iterator MBI = searchBackwards(p, I, MBB);
473
516
  if (MBI != MachineBasicBlock::iterator()) {
474
64
    MachineInstr *NewMI = postRAConvertToLEA(MBB, MBI);
475
64
    if (NewMI) {
476
9
      ++NumLEAs;
477
9
      LLVM_DEBUG(dbgs() << "FixLEA: Candidate to replace:"; MBI->dump(););
478
9
      // now to replace with an equivalent LEA...
479
9
      LLVM_DEBUG(dbgs() << "FixLEA: Replaced by: "; NewMI->dump(););
480
9
      MBB.erase(MBI);
481
9
      MachineBasicBlock::iterator J =
482
9
          static_cast<MachineBasicBlock::iterator>(NewMI);
483
9
      processInstruction(J, MBB);
484
9
    }
485
64
  }
486
516
}
487
488
void FixupLEAPass::processInstructionForSlowLEA(MachineBasicBlock::iterator &I,
489
89
                                                MachineBasicBlock &MBB) {
490
89
  MachineInstr &MI = *I;
491
89
  const unsigned Opcode = MI.getOpcode();
492
89
493
89
  const MachineOperand &Dst =     MI.getOperand(0);
494
89
  const MachineOperand &Base =    MI.getOperand(1 + X86::AddrBaseReg);
495
89
  const MachineOperand &Scale =   MI.getOperand(1 + X86::AddrScaleAmt);
496
89
  const MachineOperand &Index =   MI.getOperand(1 + X86::AddrIndexReg);
497
89
  const MachineOperand &Offset =  MI.getOperand(1 + X86::AddrDisp);
498
89
  const MachineOperand &Segment = MI.getOperand(1 + X86::AddrSegmentReg);
499
89
500
89
  if (Segment.getReg() != 0 || !Offset.isImm() ||
501
89
      !TII->isSafeToClobberEFLAGS(MBB, I))
502
0
    return;
503
89
  const unsigned DstR = Dst.getReg();
504
89
  const unsigned SrcR1 = Base.getReg();
505
89
  const unsigned SrcR2 = Index.getReg();
506
89
  if ((SrcR1 == 0 || 
SrcR1 != DstR79
) &&
(86
SrcR2 == 086
||
SrcR2 != DstR80
))
507
79
    return;
508
10
  if (Scale.getImm() > 1)
509
3
    return;
510
7
  LLVM_DEBUG(dbgs() << "FixLEA: Candidate to replace:"; I->dump(););
511
7
  LLVM_DEBUG(dbgs() << "FixLEA: Replaced by: ";);
512
7
  MachineInstr *NewMI = nullptr;
513
7
  // Make ADD instruction for two registers writing to LEA's destination
514
7
  if (SrcR1 != 0 && SrcR2 != 0) {
515
7
    const MCInstrDesc &ADDrr = TII->get(getADDrrFromLEA(Opcode));
516
7
    const MachineOperand &Src = SrcR1 == DstR ? 
Index0
: Base;
517
7
    NewMI =
518
7
        BuildMI(MBB, I, MI.getDebugLoc(), ADDrr, DstR).addReg(DstR).add(Src);
519
7
    LLVM_DEBUG(NewMI->dump(););
520
7
  }
521
7
  // Make ADD instruction for immediate
522
7
  if (Offset.getImm() != 0) {
523
7
    const MCInstrDesc &ADDri =
524
7
        TII->get(getADDriFromLEA(Opcode, Offset));
525
7
    const MachineOperand &SrcR = SrcR1 == DstR ? 
Base0
: Index;
526
7
    NewMI = BuildMI(MBB, I, MI.getDebugLoc(), ADDri, DstR)
527
7
                .add(SrcR)
528
7
                .addImm(Offset.getImm());
529
7
    LLVM_DEBUG(NewMI->dump(););
530
7
  }
531
7
  if (NewMI) {
532
7
    MBB.erase(I);
533
7
    I = NewMI;
534
7
  }
535
7
}
536
537
MachineInstr *
538
FixupLEAPass::processInstrForSlow3OpLEA(MachineInstr &MI,
539
29.6k
                                        MachineBasicBlock &MBB) {
540
29.6k
  const unsigned LEAOpcode = MI.getOpcode();
541
29.6k
542
29.6k
  const MachineOperand &Dst =     MI.getOperand(0);
543
29.6k
  const MachineOperand &Base =    MI.getOperand(1 + X86::AddrBaseReg);
544
29.6k
  const MachineOperand &Scale =   MI.getOperand(1 + X86::AddrScaleAmt);
545
29.6k
  const MachineOperand &Index =   MI.getOperand(1 + X86::AddrIndexReg);
546
29.6k
  const MachineOperand &Offset =  MI.getOperand(1 + X86::AddrDisp);
547
29.6k
  const MachineOperand &Segment = MI.getOperand(1 + X86::AddrSegmentReg);
548
29.6k
549
29.6k
  if (!(TII->isThreeOperandsLEA(MI) ||
550
29.6k
        
hasInefficientLEABaseReg(Base, Index)27.9k
) ||
551
29.6k
      
!TII->isSafeToClobberEFLAGS(MBB, MI)1.85k
||
552
29.6k
      
Segment.getReg() != X86::NoRegister1.75k
)
553
27.9k
    return nullptr;
554
1.75k
555
1.75k
  unsigned DstR = Dst.getReg();
556
1.75k
  unsigned BaseR = Base.getReg();
557
1.75k
  unsigned IndexR = Index.getReg();
558
1.75k
  unsigned SSDstR =
559
1.75k
      (LEAOpcode == X86::LEA64_32r) ? 
getX86SubSuperRegister(DstR, 64)253
:
DstR1.50k
;
560
1.75k
  bool IsScale1 = Scale.getImm() == 1;
561
1.75k
  bool IsInefficientBase = isInefficientLEAReg(BaseR);
562
1.75k
  bool IsInefficientIndex = isInefficientLEAReg(IndexR);
563
1.75k
564
1.75k
  // Skip these cases since it takes more than 2 instructions
565
1.75k
  // to replace the LEA instruction.
566
1.75k
  if (IsInefficientBase && 
SSDstR == BaseR224
&&
!IsScale17
)
567
3
    return nullptr;
568
1.75k
  if (LEAOpcode == X86::LEA64_32r && 
IsInefficientBase252
&&
569
1.75k
      
(24
IsInefficientIndex24
||
!IsScale13
))
570
21
    return nullptr;
571
1.72k
572
1.72k
  const DebugLoc DL = MI.getDebugLoc();
573
1.72k
  const MCInstrDesc &ADDrr = TII->get(getADDrrFromLEA(LEAOpcode));
574
1.72k
  const MCInstrDesc &ADDri = TII->get(getADDriFromLEA(LEAOpcode, Offset));
575
1.72k
576
1.72k
  LLVM_DEBUG(dbgs() << "FixLEA: Candidate to replace:"; MI.dump(););
577
1.72k
  LLVM_DEBUG(dbgs() << "FixLEA: Replaced by: ";);
578
1.72k
579
1.72k
  // First try to replace LEA with one or two (for the 3-op LEA case)
580
1.72k
  // add instructions:
581
1.72k
  // 1.lea (%base,%index,1), %base => add %index,%base
582
1.72k
  // 2.lea (%base,%index,1), %index => add %base,%index
583
1.72k
  if (IsScale1 && 
(1.39k
DstR == BaseR1.39k
||
DstR == IndexR1.27k
)) {
584
299
    const MachineOperand &Src = DstR == BaseR ? 
Index116
:
Base183
;
585
299
    MachineInstr *NewMI =
586
299
        BuildMI(MBB, MI, DL, ADDrr, DstR).addReg(DstR).add(Src);
587
299
    LLVM_DEBUG(NewMI->dump(););
588
299
    // Create ADD instruction for the Offset in case of 3-Ops LEA.
589
299
    if (hasLEAOffset(Offset)) {
590
299
      NewMI = BuildMI(MBB, MI, DL, ADDri, DstR).addReg(DstR).add(Offset);
591
299
      LLVM_DEBUG(NewMI->dump(););
592
299
    }
593
299
    return NewMI;
594
299
  }
595
1.43k
  // If the base is inefficient try switching the index and base operands,
596
1.43k
  // otherwise just break the 3-Ops LEA inst into 2-Ops LEA + ADD instruction:
597
1.43k
  // lea offset(%base,%index,scale),%dst =>
598
1.43k
  // lea (%base,%index,scale); add offset,%dst
599
1.43k
  if (!IsInefficientBase || 
(186
!IsInefficientIndex186
&&
IsScale1162
)) {
600
1.39k
    MachineInstr *NewMI = BuildMI(MBB, MI, DL, TII->get(LEAOpcode))
601
1.39k
                              .add(Dst)
602
1.39k
                              .add(IsInefficientBase ? 
Index150
:
Base1.24k
)
603
1.39k
                              .add(Scale)
604
1.39k
                              .add(IsInefficientBase ? 
Base150
:
Index1.24k
)
605
1.39k
                              .addImm(0)
606
1.39k
                              .add(Segment);
607
1.39k
    LLVM_DEBUG(NewMI->dump(););
608
1.39k
    // Create ADD instruction for the Offset in case of 3-Ops LEA.
609
1.39k
    if (hasLEAOffset(Offset)) {
610
1.35k
      NewMI = BuildMI(MBB, MI, DL, ADDri, DstR).addReg(DstR).add(Offset);
611
1.35k
      LLVM_DEBUG(NewMI->dump(););
612
1.35k
    }
613
1.39k
    return NewMI;
614
1.39k
  }
615
36
  // Handle the rest of the cases with inefficient base register:
616
36
  assert(SSDstR != BaseR && "SSDstR == BaseR should be handled already!");
617
36
  assert(IsInefficientBase && "efficient base should be handled already!");
618
36
619
36
  // lea (%base,%index,1), %dst => mov %base,%dst; add %index,%dst
620
36
  if (IsScale1 && 
!hasLEAOffset(Offset)6
) {
621
4
    bool BIK = Base.isKill() && 
BaseR != IndexR2
;
622
4
    TII->copyPhysReg(MBB, MI, DL, DstR, BaseR, BIK);
623
4
    LLVM_DEBUG(MI.getPrevNode()->dump(););
624
4
625
4
    MachineInstr *NewMI =
626
4
        BuildMI(MBB, MI, DL, ADDrr, DstR).addReg(DstR).add(Index);
627
4
    LLVM_DEBUG(NewMI->dump(););
628
4
    return NewMI;
629
4
  }
630
32
  // lea offset(%base,%index,scale), %dst =>
631
32
  // lea offset( ,%index,scale), %dst; add %base,%dst
632
32
  MachineInstr *NewMI = BuildMI(MBB, MI, DL, TII->get(LEAOpcode))
633
32
                            .add(Dst)
634
32
                            .addReg(0)
635
32
                            .add(Scale)
636
32
                            .add(Index)
637
32
                            .add(Offset)
638
32
                            .add(Segment);
639
32
  LLVM_DEBUG(NewMI->dump(););
640
32
641
32
  NewMI = BuildMI(MBB, MI, DL, ADDrr, DstR).addReg(DstR).add(Base);
642
32
  LLVM_DEBUG(NewMI->dump(););
643
32
  return NewMI;
644
32
}