Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/X86/X86FixupSetCC.cpp
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//===---- X86FixupSetCC.cpp - optimize usage of LEA instructions ----------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines a pass that fixes zero-extension of setcc patterns.
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// X86 setcc instructions are modeled to have no input arguments, and a single
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// GR8 output argument. This is consistent with other similar instructions
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// (e.g. movb), but means it is impossible to directly generate a setcc into
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// the lower GR8 of a specified GR32.
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// This means that ISel must select (zext (setcc)) into something like
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// seta %al; movzbl %al, %eax.
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// Unfortunately, this can cause a stall due to the partial register write
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// performed by the setcc. Instead, we can use:
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// xor %eax, %eax; seta %al
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// This both avoids the stall, and encodes shorter.
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//===----------------------------------------------------------------------===//
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#include "X86.h"
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#include "X86InstrInfo.h"
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#include "X86Subtarget.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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using namespace llvm;
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#define DEBUG_TYPE "x86-fixup-setcc"
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STATISTIC(NumSubstZexts, "Number of setcc + zext pairs substituted");
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namespace {
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class X86FixupSetCCPass : public MachineFunctionPass {
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public:
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11.3k
  X86FixupSetCCPass() : MachineFunctionPass(ID) {}
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  StringRef getPassName() const override { return "X86 Fixup SetCC"; }
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  bool runOnMachineFunction(MachineFunction &MF) override;
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private:
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  // Find the preceding instruction that imp-defs eflags.
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  MachineInstr *findFlagsImpDef(MachineBasicBlock *MBB,
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                                MachineBasicBlock::reverse_iterator MI);
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  // Return true if MI imp-uses eflags.
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  bool impUsesFlags(MachineInstr *MI);
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  // Return true if this is the opcode of a SetCC instruction with a register
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  // output.
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  bool isSetCCr(unsigned Opode);
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  MachineRegisterInfo *MRI;
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  const X86InstrInfo *TII;
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  enum { SearchBound = 16 };
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  static char ID;
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};
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char X86FixupSetCCPass::ID = 0;
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}
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FunctionPass *llvm::createX86FixupSetCC() { return new X86FixupSetCCPass(); }
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// We expect the instruction *immediately* before the setcc to imp-def
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// EFLAGS (because of scheduling glue). To make this less brittle w.r.t
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// scheduling, look backwards until we hit the beginning of the
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// basic-block, or a small bound (to avoid quadratic behavior).
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MachineInstr *
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X86FixupSetCCPass::findFlagsImpDef(MachineBasicBlock *MBB,
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3.25k
                                   MachineBasicBlock::reverse_iterator MI) {
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  // FIXME: Should this be instr_rend(), and MI be reverse_instr_iterator?
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  auto MBBStart = MBB->rend();
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6.72k
  for (int i = 0; (i < SearchBound) && (MI != MBBStart); 
++i, ++MI3.47k
)
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    for (auto &Op : MI->implicit_operands())
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      if (Op.isReg() && 
(Op.getReg() == X86::EFLAGS)6.71k
&&
Op.isDef()6.37k
)
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        return &*MI;
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return nullptr190
;
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3.25k
}
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bool X86FixupSetCCPass::impUsesFlags(MachineInstr *MI) {
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  for (auto &Op : MI->implicit_operands())
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    if (Op.isReg() && 
(Op.getReg() == X86::EFLAGS)3.91k
&&
Op.isUse()3.41k
)
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      return true;
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return false2.70k
;
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}
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bool X86FixupSetCCPass::runOnMachineFunction(MachineFunction &MF) {
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  bool Changed = false;
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  MRI = &MF.getRegInfo();
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  TII = MF.getSubtarget<X86Subtarget>().getInstrInfo();
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  SmallVector<MachineInstr*, 4> ToErase;
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  for (auto &MBB : MF) {
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3.17M
    for (auto &MI : MBB) {
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3.17M
      // Find a setcc that is used by a zext.
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3.17M
      // This doesn't have to be the only use, the transformation is safe
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      // regardless.
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      if (MI.getOpcode() != X86::SETCCr)
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        continue;
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      MachineInstr *ZExt = nullptr;
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      for (auto &Use : MRI->use_instructions(MI.getOperand(0).getReg()))
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        if (Use.getOpcode() == X86::MOVZX32rr8)
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          ZExt = &Use;
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      if (!ZExt)
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        continue;
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      // Find the preceding instruction that imp-defs eflags.
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      MachineInstr *FlagsDefMI = findFlagsImpDef(
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          MI.getParent(), MachineBasicBlock::reverse_iterator(&MI));
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      if (!FlagsDefMI)
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        continue;
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      // We'd like to put something that clobbers eflags directly before
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      // FlagsDefMI. This can't hurt anything after FlagsDefMI, because
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      // it, itself, by definition, clobbers eflags. But it may happen that
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      // FlagsDefMI also *uses* eflags, in which case the transformation is
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      // invalid.
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      if (impUsesFlags(FlagsDefMI))
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        continue;
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      ++NumSubstZexts;
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      Changed = true;
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      // On 32-bit, we need to be careful to force an ABCD register.
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      const TargetRegisterClass *RC = MF.getSubtarget<X86Subtarget>().is64Bit()
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                                          ? 
&X86::GR32RegClass1.71k
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                                          : 
&X86::GR32_ABCDRegClass996
;
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      unsigned ZeroReg = MRI->createVirtualRegister(RC);
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      unsigned InsertReg = MRI->createVirtualRegister(RC);
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      // Initialize a register with 0. This must go before the eflags def
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      BuildMI(MBB, FlagsDefMI, MI.getDebugLoc(), TII->get(X86::MOV32r0),
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              ZeroReg);
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      // X86 setcc only takes an output GR8, so fake a GR32 input by inserting
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      // the setcc result into the low byte of the zeroed register.
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      BuildMI(*ZExt->getParent(), ZExt, ZExt->getDebugLoc(),
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              TII->get(X86::INSERT_SUBREG), InsertReg)
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          .addReg(ZeroReg)
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          .addReg(MI.getOperand(0).getReg())
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          .addImm(X86::sub_8bit);
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      MRI->replaceRegWith(ZExt->getOperand(0).getReg(), InsertReg);
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      ToErase.push_back(ZExt);
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    }
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  }
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  for (auto &I : ToErase)
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    I->eraseFromParent();
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  return Changed;
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}