Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/X86/X86InstrBuilder.h
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//===-- X86InstrBuilder.h - Functions to aid building x86 insts -*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file exposes functions that may be used with BuildMI from the
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// MachineInstrBuilder.h file to handle X86'isms in a clean way.
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//
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// The BuildMem function may be used with the BuildMI function to add entire
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// memory references in a single, typed, function call.  X86 memory references
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// can be very complex expressions (described in the README), so wrapping them
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// up behind an easier to use interface makes sense.  Descriptions of the
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// functions are included below.
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//
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// For reference, the order of operands for memory references is:
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// (Operand), Base, Scale, Index, Displacement.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_X86_X86INSTRBUILDER_H
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#define LLVM_LIB_TARGET_X86_X86INSTRBUILDER_H
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include <cassert>
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namespace llvm {
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/// X86AddressMode - This struct holds a generalized full x86 address mode.
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/// The base register can be a frame index, which will eventually be replaced
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/// with BP or SP and Disp being offsetted accordingly.  The displacement may
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/// also include the offset of a global value.
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struct X86AddressMode {
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  enum {
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    RegBase,
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    FrameIndexBase
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  } BaseType;
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  union {
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    unsigned Reg;
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    int FrameIndex;
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  } Base;
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  unsigned Scale;
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  unsigned IndexReg;
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  int Disp;
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  const GlobalValue *GV;
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  unsigned GVOpFlags;
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  X86AddressMode()
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    : BaseType(RegBase), Scale(1), IndexReg(0), Disp(0), GV(nullptr),
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      GVOpFlags(0) {
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7.61k
    Base.Reg = 0;
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  }
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  void getFullAddress(SmallVectorImpl<MachineOperand> &MO) {
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    assert(Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8);
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1.17k
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1.17k
    if (BaseType == X86AddressMode::RegBase)
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      MO.push_back(MachineOperand::CreateReg(Base.Reg, false, false, false,
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                                             false, false, false, 0, false));
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    else {
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      assert(BaseType == X86AddressMode::FrameIndexBase);
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      MO.push_back(MachineOperand::CreateFI(Base.FrameIndex));
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    }
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1.17k
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1.17k
    MO.push_back(MachineOperand::CreateImm(Scale));
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1.17k
    MO.push_back(MachineOperand::CreateReg(IndexReg, false, false, false, false,
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1.17k
                                           false, false, 0, false));
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1.17k
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1.17k
    if (GV)
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      MO.push_back(MachineOperand::CreateGA(GV, Disp, GVOpFlags));
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    else
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      MO.push_back(MachineOperand::CreateImm(Disp));
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1.17k
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    MO.push_back(MachineOperand::CreateReg(0, false, false, false, false, false,
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1.17k
                                           false, 0, false));
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1.17k
  }
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};
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/// Compute the addressing mode from an machine instruction starting with the
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/// given operand.
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static inline X86AddressMode getAddressFromInstr(const MachineInstr *MI,
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                                                 unsigned Operand) {
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  X86AddressMode AM;
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  const MachineOperand &Op0 = MI->getOperand(Operand);
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  if (Op0.isReg()) {
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    AM.BaseType = X86AddressMode::RegBase;
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    AM.Base.Reg = Op0.getReg();
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  } else {
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    AM.BaseType = X86AddressMode::FrameIndexBase;
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    AM.Base.FrameIndex = Op0.getIndex();
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  }
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  const MachineOperand &Op1 = MI->getOperand(Operand + 1);
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  AM.Scale = Op1.getImm();
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  const MachineOperand &Op2 = MI->getOperand(Operand + 2);
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  AM.IndexReg = Op2.getReg();
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  const MachineOperand &Op3 = MI->getOperand(Operand + 3);
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  if (Op3.isGlobal())
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    AM.GV = Op3.getGlobal();
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  else
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    AM.Disp = Op3.getImm();
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  return AM;
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}
Unexecuted instantiation: X86DiscriminateMemOps.cpp:llvm::getAddressFromInstr(llvm::MachineInstr const*, unsigned int)
Unexecuted instantiation: X86ExpandPseudo.cpp:llvm::getAddressFromInstr(llvm::MachineInstr const*, unsigned int)
Unexecuted instantiation: X86FastISel.cpp:llvm::getAddressFromInstr(llvm::MachineInstr const*, unsigned int)
Unexecuted instantiation: X86FlagsCopyLowering.cpp:llvm::getAddressFromInstr(llvm::MachineInstr const*, unsigned int)
Unexecuted instantiation: X86FrameLowering.cpp:llvm::getAddressFromInstr(llvm::MachineInstr const*, unsigned int)
Unexecuted instantiation: X86InstructionSelector.cpp:llvm::getAddressFromInstr(llvm::MachineInstr const*, unsigned int)
X86ISelLowering.cpp:llvm::getAddressFromInstr(llvm::MachineInstr const*, unsigned int)
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                                                 unsigned Operand) {
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  X86AddressMode AM;
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  const MachineOperand &Op0 = MI->getOperand(Operand);
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  if (Op0.isReg()) {
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    AM.BaseType = X86AddressMode::RegBase;
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    AM.Base.Reg = Op0.getReg();
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  } else {
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    AM.BaseType = X86AddressMode::FrameIndexBase;
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    AM.Base.FrameIndex = Op0.getIndex();
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  }
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  const MachineOperand &Op1 = MI->getOperand(Operand + 1);
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  AM.Scale = Op1.getImm();
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  const MachineOperand &Op2 = MI->getOperand(Operand + 2);
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  AM.IndexReg = Op2.getReg();
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  const MachineOperand &Op3 = MI->getOperand(Operand + 3);
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  if (Op3.isGlobal())
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    AM.GV = Op3.getGlobal();
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  else
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    AM.Disp = Op3.getImm();
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  return AM;
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}
Unexecuted instantiation: X86InsertPrefetch.cpp:llvm::getAddressFromInstr(llvm::MachineInstr const*, unsigned int)
Unexecuted instantiation: X86InstrInfo.cpp:llvm::getAddressFromInstr(llvm::MachineInstr const*, unsigned int)
Unexecuted instantiation: X86RetpolineThunks.cpp:llvm::getAddressFromInstr(llvm::MachineInstr const*, unsigned int)
Unexecuted instantiation: X86SpeculativeLoadHardening.cpp:llvm::getAddressFromInstr(llvm::MachineInstr const*, unsigned int)
Unexecuted instantiation: X86WinAllocaExpander.cpp:llvm::getAddressFromInstr(llvm::MachineInstr const*, unsigned int)
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/// addDirectMem - This function is used to add a direct memory reference to the
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/// current instruction -- that is, a dereference of an address in a register,
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/// with no scale, index or displacement. An example is: DWORD PTR [EAX].
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///
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static inline const MachineInstrBuilder &
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addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg) {
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  // Because memory references are always represented with five
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  // values, this adds: Reg, 1, NoReg, 0, NoReg to the instruction.
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  return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0);
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}
Unexecuted instantiation: X86DiscriminateMemOps.cpp:llvm::addDirectMem(llvm::MachineInstrBuilder const&, unsigned int)
Unexecuted instantiation: X86ExpandPseudo.cpp:llvm::addDirectMem(llvm::MachineInstrBuilder const&, unsigned int)
X86FastISel.cpp:llvm::addDirectMem(llvm::MachineInstrBuilder const&, unsigned int)
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124
20
addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg) {
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  // Because memory references are always represented with five
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  // values, this adds: Reg, 1, NoReg, 0, NoReg to the instruction.
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  return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0);
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20
}
Unexecuted instantiation: X86FlagsCopyLowering.cpp:llvm::addDirectMem(llvm::MachineInstrBuilder const&, unsigned int)
Unexecuted instantiation: X86FrameLowering.cpp:llvm::addDirectMem(llvm::MachineInstrBuilder const&, unsigned int)
X86InstructionSelector.cpp:llvm::addDirectMem(llvm::MachineInstrBuilder const&, unsigned int)
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124
3
addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg) {
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  // Because memory references are always represented with five
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3
  // values, this adds: Reg, 1, NoReg, 0, NoReg to the instruction.
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3
  return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0);
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3
}
X86ISelLowering.cpp:llvm::addDirectMem(llvm::MachineInstrBuilder const&, unsigned int)
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addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg) {
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  // Because memory references are always represented with five
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  // values, this adds: Reg, 1, NoReg, 0, NoReg to the instruction.
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  return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0);
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}
Unexecuted instantiation: X86InsertPrefetch.cpp:llvm::addDirectMem(llvm::MachineInstrBuilder const&, unsigned int)
Unexecuted instantiation: X86InstrInfo.cpp:llvm::addDirectMem(llvm::MachineInstrBuilder const&, unsigned int)
Unexecuted instantiation: X86RetpolineThunks.cpp:llvm::addDirectMem(llvm::MachineInstrBuilder const&, unsigned int)
Unexecuted instantiation: X86SpeculativeLoadHardening.cpp:llvm::addDirectMem(llvm::MachineInstrBuilder const&, unsigned int)
Unexecuted instantiation: X86WinAllocaExpander.cpp:llvm::addDirectMem(llvm::MachineInstrBuilder const&, unsigned int)
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/// Replace the address used in the instruction with the direct memory
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/// reference.
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static inline void setDirectAddressInInstr(MachineInstr *MI, unsigned Operand,
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1
                                           unsigned Reg) {
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  // Direct memory address is in a form of: Reg, 1 (Scale), NoReg, 0, NoReg.
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  MI->getOperand(Operand).setReg(Reg);
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  MI->getOperand(Operand + 1).setImm(1);
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  MI->getOperand(Operand + 2).setReg(0);
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1
  MI->getOperand(Operand + 3).setImm(0);
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1
  MI->getOperand(Operand + 4).setReg(0);
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1
}
Unexecuted instantiation: X86DiscriminateMemOps.cpp:llvm::setDirectAddressInInstr(llvm::MachineInstr*, unsigned int, unsigned int)
Unexecuted instantiation: X86ExpandPseudo.cpp:llvm::setDirectAddressInInstr(llvm::MachineInstr*, unsigned int, unsigned int)
Unexecuted instantiation: X86FastISel.cpp:llvm::setDirectAddressInInstr(llvm::MachineInstr*, unsigned int, unsigned int)
Unexecuted instantiation: X86FlagsCopyLowering.cpp:llvm::setDirectAddressInInstr(llvm::MachineInstr*, unsigned int, unsigned int)
Unexecuted instantiation: X86FrameLowering.cpp:llvm::setDirectAddressInInstr(llvm::MachineInstr*, unsigned int, unsigned int)
Unexecuted instantiation: X86InstructionSelector.cpp:llvm::setDirectAddressInInstr(llvm::MachineInstr*, unsigned int, unsigned int)
X86ISelLowering.cpp:llvm::setDirectAddressInInstr(llvm::MachineInstr*, unsigned int, unsigned int)
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1
                                           unsigned Reg) {
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1
  // Direct memory address is in a form of: Reg, 1 (Scale), NoReg, 0, NoReg.
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  MI->getOperand(Operand).setReg(Reg);
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  MI->getOperand(Operand + 1).setImm(1);
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  MI->getOperand(Operand + 2).setReg(0);
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  MI->getOperand(Operand + 3).setImm(0);
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  MI->getOperand(Operand + 4).setReg(0);
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1
}
Unexecuted instantiation: X86InsertPrefetch.cpp:llvm::setDirectAddressInInstr(llvm::MachineInstr*, unsigned int, unsigned int)
Unexecuted instantiation: X86InstrInfo.cpp:llvm::setDirectAddressInInstr(llvm::MachineInstr*, unsigned int, unsigned int)
Unexecuted instantiation: X86RetpolineThunks.cpp:llvm::setDirectAddressInInstr(llvm::MachineInstr*, unsigned int, unsigned int)
Unexecuted instantiation: X86SpeculativeLoadHardening.cpp:llvm::setDirectAddressInInstr(llvm::MachineInstr*, unsigned int, unsigned int)
Unexecuted instantiation: X86WinAllocaExpander.cpp:llvm::setDirectAddressInInstr(llvm::MachineInstr*, unsigned int, unsigned int)
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static inline const MachineInstrBuilder &
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82.7k
addOffset(const MachineInstrBuilder &MIB, int Offset) {
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82.7k
  return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0);
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}
Unexecuted instantiation: X86DiscriminateMemOps.cpp:llvm::addOffset(llvm::MachineInstrBuilder const&, int)
Unexecuted instantiation: X86ExpandPseudo.cpp:llvm::addOffset(llvm::MachineInstrBuilder const&, int)
Unexecuted instantiation: X86FastISel.cpp:llvm::addOffset(llvm::MachineInstrBuilder const&, int)
Unexecuted instantiation: X86FlagsCopyLowering.cpp:llvm::addOffset(llvm::MachineInstrBuilder const&, int)
X86FrameLowering.cpp:llvm::addOffset(llvm::MachineInstrBuilder const&, int)
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890
addOffset(const MachineInstrBuilder &MIB, int Offset) {
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  return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0);
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}
X86InstructionSelector.cpp:llvm::addOffset(llvm::MachineInstrBuilder const&, int)
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143
6
addOffset(const MachineInstrBuilder &MIB, int Offset) {
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  return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0);
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}
X86ISelLowering.cpp:llvm::addOffset(llvm::MachineInstrBuilder const&, int)
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143
3.47k
addOffset(const MachineInstrBuilder &MIB, int Offset) {
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3.47k
  return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0);
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}
Unexecuted instantiation: X86InsertPrefetch.cpp:llvm::addOffset(llvm::MachineInstrBuilder const&, int)
X86InstrInfo.cpp:llvm::addOffset(llvm::MachineInstrBuilder const&, int)
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143
78.3k
addOffset(const MachineInstrBuilder &MIB, int Offset) {
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  return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0);
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}
X86RetpolineThunks.cpp:llvm::addOffset(llvm::MachineInstrBuilder const&, int)
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143
15
addOffset(const MachineInstrBuilder &MIB, int Offset) {
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  return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0);
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15
}
Unexecuted instantiation: X86SpeculativeLoadHardening.cpp:llvm::addOffset(llvm::MachineInstrBuilder const&, int)
Unexecuted instantiation: X86WinAllocaExpander.cpp:llvm::addOffset(llvm::MachineInstrBuilder const&, int)
146
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static inline const MachineInstrBuilder &
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13.1k
addOffset(const MachineInstrBuilder &MIB, const MachineOperand& Offset) {
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  return MIB.addImm(1).addReg(0).add(Offset).addReg(0);
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}
Unexecuted instantiation: X86DiscriminateMemOps.cpp:llvm::addOffset(llvm::MachineInstrBuilder const&, llvm::MachineOperand const&)
Unexecuted instantiation: X86ExpandPseudo.cpp:llvm::addOffset(llvm::MachineInstrBuilder const&, llvm::MachineOperand const&)
Unexecuted instantiation: X86FastISel.cpp:llvm::addOffset(llvm::MachineInstrBuilder const&, llvm::MachineOperand const&)
Unexecuted instantiation: X86FlagsCopyLowering.cpp:llvm::addOffset(llvm::MachineInstrBuilder const&, llvm::MachineOperand const&)
Unexecuted instantiation: X86FrameLowering.cpp:llvm::addOffset(llvm::MachineInstrBuilder const&, llvm::MachineOperand const&)
Unexecuted instantiation: X86InstructionSelector.cpp:llvm::addOffset(llvm::MachineInstrBuilder const&, llvm::MachineOperand const&)
Unexecuted instantiation: X86ISelLowering.cpp:llvm::addOffset(llvm::MachineInstrBuilder const&, llvm::MachineOperand const&)
Unexecuted instantiation: X86InsertPrefetch.cpp:llvm::addOffset(llvm::MachineInstrBuilder const&, llvm::MachineOperand const&)
X86InstrInfo.cpp:llvm::addOffset(llvm::MachineInstrBuilder const&, llvm::MachineOperand const&)
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148
13.1k
addOffset(const MachineInstrBuilder &MIB, const MachineOperand& Offset) {
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13.1k
  return MIB.addImm(1).addReg(0).add(Offset).addReg(0);
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13.1k
}
Unexecuted instantiation: X86RetpolineThunks.cpp:llvm::addOffset(llvm::MachineInstrBuilder const&, llvm::MachineOperand const&)
Unexecuted instantiation: X86SpeculativeLoadHardening.cpp:llvm::addOffset(llvm::MachineInstrBuilder const&, llvm::MachineOperand const&)
Unexecuted instantiation: X86WinAllocaExpander.cpp:llvm::addOffset(llvm::MachineInstrBuilder const&, llvm::MachineOperand const&)
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/// addRegOffset - This function is used to add a memory reference of the form
153
/// [Reg + Offset], i.e., one with no scale or index, but with a
154
/// displacement. An example is: DWORD PTR [EAX + 4].
155
///
156
static inline const MachineInstrBuilder &
157
addRegOffset(const MachineInstrBuilder &MIB,
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1.37k
             unsigned Reg, bool isKill, int Offset) {
159
1.37k
  return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset);
160
1.37k
}
Unexecuted instantiation: X86DiscriminateMemOps.cpp:llvm::addRegOffset(llvm::MachineInstrBuilder const&, unsigned int, bool, int)
Unexecuted instantiation: X86ExpandPseudo.cpp:llvm::addRegOffset(llvm::MachineInstrBuilder const&, unsigned int, bool, int)
Unexecuted instantiation: X86FastISel.cpp:llvm::addRegOffset(llvm::MachineInstrBuilder const&, unsigned int, bool, int)
Unexecuted instantiation: X86FlagsCopyLowering.cpp:llvm::addRegOffset(llvm::MachineInstrBuilder const&, unsigned int, bool, int)
X86FrameLowering.cpp:llvm::addRegOffset(llvm::MachineInstrBuilder const&, unsigned int, bool, int)
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158
855
             unsigned Reg, bool isKill, int Offset) {
159
855
  return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset);
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}
Unexecuted instantiation: X86InstructionSelector.cpp:llvm::addRegOffset(llvm::MachineInstrBuilder const&, unsigned int, bool, int)
X86ISelLowering.cpp:llvm::addRegOffset(llvm::MachineInstrBuilder const&, unsigned int, bool, int)
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158
2
             unsigned Reg, bool isKill, int Offset) {
159
2
  return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset);
160
2
}
Unexecuted instantiation: X86InsertPrefetch.cpp:llvm::addRegOffset(llvm::MachineInstrBuilder const&, unsigned int, bool, int)
X86InstrInfo.cpp:llvm::addRegOffset(llvm::MachineInstrBuilder const&, unsigned int, bool, int)
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158
506
             unsigned Reg, bool isKill, int Offset) {
159
506
  return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset);
160
506
}
X86RetpolineThunks.cpp:llvm::addRegOffset(llvm::MachineInstrBuilder const&, unsigned int, bool, int)
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158
15
             unsigned Reg, bool isKill, int Offset) {
159
15
  return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset);
160
15
}
Unexecuted instantiation: X86SpeculativeLoadHardening.cpp:llvm::addRegOffset(llvm::MachineInstrBuilder const&, unsigned int, bool, int)
Unexecuted instantiation: X86WinAllocaExpander.cpp:llvm::addRegOffset(llvm::MachineInstrBuilder const&, unsigned int, bool, int)
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162
/// addRegReg - This function is used to add a memory reference of the form:
163
/// [Reg + Reg].
164
static inline const MachineInstrBuilder &addRegReg(const MachineInstrBuilder &MIB,
165
                                            unsigned Reg1, bool isKill1,
166
3.20k
                                            unsigned Reg2, bool isKill2) {
167
3.20k
  return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1)
168
3.20k
    .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0);
169
3.20k
}
Unexecuted instantiation: X86DiscriminateMemOps.cpp:llvm::addRegReg(llvm::MachineInstrBuilder const&, unsigned int, bool, unsigned int, bool)
Unexecuted instantiation: X86ExpandPseudo.cpp:llvm::addRegReg(llvm::MachineInstrBuilder const&, unsigned int, bool, unsigned int, bool)
Unexecuted instantiation: X86FastISel.cpp:llvm::addRegReg(llvm::MachineInstrBuilder const&, unsigned int, bool, unsigned int, bool)
Unexecuted instantiation: X86FlagsCopyLowering.cpp:llvm::addRegReg(llvm::MachineInstrBuilder const&, unsigned int, bool, unsigned int, bool)
Unexecuted instantiation: X86FrameLowering.cpp:llvm::addRegReg(llvm::MachineInstrBuilder const&, unsigned int, bool, unsigned int, bool)
Unexecuted instantiation: X86InstructionSelector.cpp:llvm::addRegReg(llvm::MachineInstrBuilder const&, unsigned int, bool, unsigned int, bool)
Unexecuted instantiation: X86ISelLowering.cpp:llvm::addRegReg(llvm::MachineInstrBuilder const&, unsigned int, bool, unsigned int, bool)
Unexecuted instantiation: X86InsertPrefetch.cpp:llvm::addRegReg(llvm::MachineInstrBuilder const&, unsigned int, bool, unsigned int, bool)
X86InstrInfo.cpp:llvm::addRegReg(llvm::MachineInstrBuilder const&, unsigned int, bool, unsigned int, bool)
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166
3.20k
                                            unsigned Reg2, bool isKill2) {
167
3.20k
  return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1)
168
3.20k
    .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0);
169
3.20k
}
Unexecuted instantiation: X86RetpolineThunks.cpp:llvm::addRegReg(llvm::MachineInstrBuilder const&, unsigned int, bool, unsigned int, bool)
Unexecuted instantiation: X86SpeculativeLoadHardening.cpp:llvm::addRegReg(llvm::MachineInstrBuilder const&, unsigned int, bool, unsigned int, bool)
Unexecuted instantiation: X86WinAllocaExpander.cpp:llvm::addRegReg(llvm::MachineInstrBuilder const&, unsigned int, bool, unsigned int, bool)
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171
static inline const MachineInstrBuilder &
172
addFullAddress(const MachineInstrBuilder &MIB,
173
5.26k
               const X86AddressMode &AM) {
174
5.26k
  assert(AM.Scale == 1 || AM.Scale == 2 || AM.Scale == 4 || AM.Scale == 8);
175
5.26k
176
5.26k
  if (AM.BaseType == X86AddressMode::RegBase)
177
2.28k
    MIB.addReg(AM.Base.Reg);
178
2.98k
  else {
179
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    assert(AM.BaseType == X86AddressMode::FrameIndexBase);
180
2.98k
    MIB.addFrameIndex(AM.Base.FrameIndex);
181
2.98k
  }
182
5.26k
183
5.26k
  MIB.addImm(AM.Scale).addReg(AM.IndexReg);
184
5.26k
  if (AM.GV)
185
412
    MIB.addGlobalAddress(AM.GV, AM.Disp, AM.GVOpFlags);
186
4.85k
  else
187
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    MIB.addImm(AM.Disp);
188
5.26k
189
5.26k
  return MIB.addReg(0);
190
5.26k
}
Unexecuted instantiation: X86DiscriminateMemOps.cpp:llvm::addFullAddress(llvm::MachineInstrBuilder const&, llvm::X86AddressMode const&)
Unexecuted instantiation: X86ExpandPseudo.cpp:llvm::addFullAddress(llvm::MachineInstrBuilder const&, llvm::X86AddressMode const&)
X86FastISel.cpp:llvm::addFullAddress(llvm::MachineInstrBuilder const&, llvm::X86AddressMode const&)
Line
Count
Source
173
4.03k
               const X86AddressMode &AM) {
174
4.03k
  assert(AM.Scale == 1 || AM.Scale == 2 || AM.Scale == 4 || AM.Scale == 8);
175
4.03k
176
4.03k
  if (AM.BaseType == X86AddressMode::RegBase)
177
1.90k
    MIB.addReg(AM.Base.Reg);
178
2.13k
  else {
179
2.13k
    assert(AM.BaseType == X86AddressMode::FrameIndexBase);
180
2.13k
    MIB.addFrameIndex(AM.Base.FrameIndex);
181
2.13k
  }
182
4.03k
183
4.03k
  MIB.addImm(AM.Scale).addReg(AM.IndexReg);
184
4.03k
  if (AM.GV)
185
387
    MIB.addGlobalAddress(AM.GV, AM.Disp, AM.GVOpFlags);
186
3.65k
  else
187
3.65k
    MIB.addImm(AM.Disp);
188
4.03k
189
4.03k
  return MIB.addReg(0);
190
4.03k
}
Unexecuted instantiation: X86FlagsCopyLowering.cpp:llvm::addFullAddress(llvm::MachineInstrBuilder const&, llvm::X86AddressMode const&)
Unexecuted instantiation: X86FrameLowering.cpp:llvm::addFullAddress(llvm::MachineInstrBuilder const&, llvm::X86AddressMode const&)
X86InstructionSelector.cpp:llvm::addFullAddress(llvm::MachineInstrBuilder const&, llvm::X86AddressMode const&)
Line
Count
Source
173
533
               const X86AddressMode &AM) {
174
533
  assert(AM.Scale == 1 || AM.Scale == 2 || AM.Scale == 4 || AM.Scale == 8);
175
533
176
533
  if (AM.BaseType == X86AddressMode::RegBase)
177
378
    MIB.addReg(AM.Base.Reg);
178
155
  else {
179
155
    assert(AM.BaseType == X86AddressMode::FrameIndexBase);
180
155
    MIB.addFrameIndex(AM.Base.FrameIndex);
181
155
  }
182
533
183
533
  MIB.addImm(AM.Scale).addReg(AM.IndexReg);
184
533
  if (AM.GV)
185
25
    MIB.addGlobalAddress(AM.GV, AM.Disp, AM.GVOpFlags);
186
508
  else
187
508
    MIB.addImm(AM.Disp);
188
533
189
533
  return MIB.addReg(0);
190
533
}
X86ISelLowering.cpp:llvm::addFullAddress(llvm::MachineInstrBuilder const&, llvm::X86AddressMode const&)
Line
Count
Source
173
694
               const X86AddressMode &AM) {
174
694
  assert(AM.Scale == 1 || AM.Scale == 2 || AM.Scale == 4 || AM.Scale == 8);
175
694
176
694
  if (AM.BaseType == X86AddressMode::RegBase)
177
1
    MIB.addReg(AM.Base.Reg);
178
693
  else {
179
693
    assert(AM.BaseType == X86AddressMode::FrameIndexBase);
180
693
    MIB.addFrameIndex(AM.Base.FrameIndex);
181
693
  }
182
694
183
694
  MIB.addImm(AM.Scale).addReg(AM.IndexReg);
184
694
  if (AM.GV)
185
0
    MIB.addGlobalAddress(AM.GV, AM.Disp, AM.GVOpFlags);
186
694
  else
187
694
    MIB.addImm(AM.Disp);
188
694
189
694
  return MIB.addReg(0);
190
694
}
Unexecuted instantiation: X86InsertPrefetch.cpp:llvm::addFullAddress(llvm::MachineInstrBuilder const&, llvm::X86AddressMode const&)
Unexecuted instantiation: X86InstrInfo.cpp:llvm::addFullAddress(llvm::MachineInstrBuilder const&, llvm::X86AddressMode const&)
Unexecuted instantiation: X86RetpolineThunks.cpp:llvm::addFullAddress(llvm::MachineInstrBuilder const&, llvm::X86AddressMode const&)
Unexecuted instantiation: X86SpeculativeLoadHardening.cpp:llvm::addFullAddress(llvm::MachineInstrBuilder const&, llvm::X86AddressMode const&)
Unexecuted instantiation: X86WinAllocaExpander.cpp:llvm::addFullAddress(llvm::MachineInstrBuilder const&, llvm::X86AddressMode const&)
191
192
/// addFrameReference - This function is used to add a reference to the base of
193
/// an abstract object on the stack frame of the current function.  This
194
/// reference has base register as the FrameIndex offset until it is resolved.
195
/// This allows a constant offset to be specified as well...
196
///
197
static inline const MachineInstrBuilder &
198
63.5k
addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0) {
199
63.5k
  MachineInstr *MI = MIB;
200
63.5k
  MachineFunction &MF = *MI->getParent()->getParent();
201
63.5k
  MachineFrameInfo &MFI = MF.getFrameInfo();
202
63.5k
  const MCInstrDesc &MCID = MI->getDesc();
203
63.5k
  auto Flags = MachineMemOperand::MONone;
204
63.5k
  if (MCID.mayLoad())
205
33.9k
    Flags |= MachineMemOperand::MOLoad;
206
63.5k
  if (MCID.mayStore())
207
29.6k
    Flags |= MachineMemOperand::MOStore;
208
63.5k
  MachineMemOperand *MMO = MF.getMachineMemOperand(
209
63.5k
      MachinePointerInfo::getFixedStack(MF, FI, Offset), Flags,
210
63.5k
      MFI.getObjectSize(FI), MFI.getObjectAlignment(FI));
211
63.5k
  return addOffset(MIB.addFrameIndex(FI), Offset)
212
63.5k
            .addMemOperand(MMO);
213
63.5k
}
Unexecuted instantiation: X86DiscriminateMemOps.cpp:llvm::addFrameReference(llvm::MachineInstrBuilder const&, int, int)
Unexecuted instantiation: X86ExpandPseudo.cpp:llvm::addFrameReference(llvm::MachineInstrBuilder const&, int, int)
Unexecuted instantiation: X86FastISel.cpp:llvm::addFrameReference(llvm::MachineInstrBuilder const&, int, int)
Unexecuted instantiation: X86FlagsCopyLowering.cpp:llvm::addFrameReference(llvm::MachineInstrBuilder const&, int, int)
X86FrameLowering.cpp:llvm::addFrameReference(llvm::MachineInstrBuilder const&, int, int)
Line
Count
Source
198
35
addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0) {
199
35
  MachineInstr *MI = MIB;
200
35
  MachineFunction &MF = *MI->getParent()->getParent();
201
35
  MachineFrameInfo &MFI = MF.getFrameInfo();
202
35
  const MCInstrDesc &MCID = MI->getDesc();
203
35
  auto Flags = MachineMemOperand::MONone;
204
35
  if (MCID.mayLoad())
205
0
    Flags |= MachineMemOperand::MOLoad;
206
35
  if (MCID.mayStore())
207
35
    Flags |= MachineMemOperand::MOStore;
208
35
  MachineMemOperand *MMO = MF.getMachineMemOperand(
209
35
      MachinePointerInfo::getFixedStack(MF, FI, Offset), Flags,
210
35
      MFI.getObjectSize(FI), MFI.getObjectAlignment(FI));
211
35
  return addOffset(MIB.addFrameIndex(FI), Offset)
212
35
            .addMemOperand(MMO);
213
35
}
Unexecuted instantiation: X86InstructionSelector.cpp:llvm::addFrameReference(llvm::MachineInstrBuilder const&, int, int)
X86ISelLowering.cpp:llvm::addFrameReference(llvm::MachineInstrBuilder const&, int, int)
Line
Count
Source
198
3.47k
addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0) {
199
3.47k
  MachineInstr *MI = MIB;
200
3.47k
  MachineFunction &MF = *MI->getParent()->getParent();
201
3.47k
  MachineFrameInfo &MFI = MF.getFrameInfo();
202
3.47k
  const MCInstrDesc &MCID = MI->getDesc();
203
3.47k
  auto Flags = MachineMemOperand::MONone;
204
3.47k
  if (MCID.mayLoad())
205
2.08k
    Flags |= MachineMemOperand::MOLoad;
206
3.47k
  if (MCID.mayStore())
207
1.39k
    Flags |= MachineMemOperand::MOStore;
208
3.47k
  MachineMemOperand *MMO = MF.getMachineMemOperand(
209
3.47k
      MachinePointerInfo::getFixedStack(MF, FI, Offset), Flags,
210
3.47k
      MFI.getObjectSize(FI), MFI.getObjectAlignment(FI));
211
3.47k
  return addOffset(MIB.addFrameIndex(FI), Offset)
212
3.47k
            .addMemOperand(MMO);
213
3.47k
}
Unexecuted instantiation: X86InsertPrefetch.cpp:llvm::addFrameReference(llvm::MachineInstrBuilder const&, int, int)
X86InstrInfo.cpp:llvm::addFrameReference(llvm::MachineInstrBuilder const&, int, int)
Line
Count
Source
198
60.0k
addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0) {
199
60.0k
  MachineInstr *MI = MIB;
200
60.0k
  MachineFunction &MF = *MI->getParent()->getParent();
201
60.0k
  MachineFrameInfo &MFI = MF.getFrameInfo();
202
60.0k
  const MCInstrDesc &MCID = MI->getDesc();
203
60.0k
  auto Flags = MachineMemOperand::MONone;
204
60.0k
  if (MCID.mayLoad())
205
31.8k
    Flags |= MachineMemOperand::MOLoad;
206
60.0k
  if (MCID.mayStore())
207
28.2k
    Flags |= MachineMemOperand::MOStore;
208
60.0k
  MachineMemOperand *MMO = MF.getMachineMemOperand(
209
60.0k
      MachinePointerInfo::getFixedStack(MF, FI, Offset), Flags,
210
60.0k
      MFI.getObjectSize(FI), MFI.getObjectAlignment(FI));
211
60.0k
  return addOffset(MIB.addFrameIndex(FI), Offset)
212
60.0k
            .addMemOperand(MMO);
213
60.0k
}
Unexecuted instantiation: X86RetpolineThunks.cpp:llvm::addFrameReference(llvm::MachineInstrBuilder const&, int, int)
Unexecuted instantiation: X86SpeculativeLoadHardening.cpp:llvm::addFrameReference(llvm::MachineInstrBuilder const&, int, int)
Unexecuted instantiation: X86WinAllocaExpander.cpp:llvm::addFrameReference(llvm::MachineInstrBuilder const&, int, int)
214
215
/// addConstantPoolReference - This function is used to add a reference to the
216
/// base of a constant value spilled to the per-function constant pool.  The
217
/// reference uses the abstract ConstantPoolIndex which is retained until
218
/// either machine code emission or assembly output. In PIC mode on x86-32,
219
/// the GlobalBaseReg parameter can be used to make this a
220
/// GlobalBaseReg-relative reference.
221
///
222
static inline const MachineInstrBuilder &
223
addConstantPoolReference(const MachineInstrBuilder &MIB, unsigned CPI,
224
41
                         unsigned GlobalBaseReg, unsigned char OpFlags) {
225
41
  //FIXME: factor this
226
41
  return MIB.addReg(GlobalBaseReg).addImm(1).addReg(0)
227
41
    .addConstantPoolIndex(CPI, 0, OpFlags).addReg(0);
228
41
}
Unexecuted instantiation: X86DiscriminateMemOps.cpp:llvm::addConstantPoolReference(llvm::MachineInstrBuilder const&, unsigned int, unsigned int, unsigned char)
Unexecuted instantiation: X86ExpandPseudo.cpp:llvm::addConstantPoolReference(llvm::MachineInstrBuilder const&, unsigned int, unsigned int, unsigned char)
X86FastISel.cpp:llvm::addConstantPoolReference(llvm::MachineInstrBuilder const&, unsigned int, unsigned int, unsigned char)
Line
Count
Source
224
29
                         unsigned GlobalBaseReg, unsigned char OpFlags) {
225
29
  //FIXME: factor this
226
29
  return MIB.addReg(GlobalBaseReg).addImm(1).addReg(0)
227
29
    .addConstantPoolIndex(CPI, 0, OpFlags).addReg(0);
228
29
}
Unexecuted instantiation: X86FlagsCopyLowering.cpp:llvm::addConstantPoolReference(llvm::MachineInstrBuilder const&, unsigned int, unsigned int, unsigned char)
Unexecuted instantiation: X86FrameLowering.cpp:llvm::addConstantPoolReference(llvm::MachineInstrBuilder const&, unsigned int, unsigned int, unsigned char)
X86InstructionSelector.cpp:llvm::addConstantPoolReference(llvm::MachineInstrBuilder const&, unsigned int, unsigned int, unsigned char)
Line
Count
Source
224
12
                         unsigned GlobalBaseReg, unsigned char OpFlags) {
225
12
  //FIXME: factor this
226
12
  return MIB.addReg(GlobalBaseReg).addImm(1).addReg(0)
227
12
    .addConstantPoolIndex(CPI, 0, OpFlags).addReg(0);
228
12
}
Unexecuted instantiation: X86ISelLowering.cpp:llvm::addConstantPoolReference(llvm::MachineInstrBuilder const&, unsigned int, unsigned int, unsigned char)
Unexecuted instantiation: X86InsertPrefetch.cpp:llvm::addConstantPoolReference(llvm::MachineInstrBuilder const&, unsigned int, unsigned int, unsigned char)
Unexecuted instantiation: X86InstrInfo.cpp:llvm::addConstantPoolReference(llvm::MachineInstrBuilder const&, unsigned int, unsigned int, unsigned char)
Unexecuted instantiation: X86RetpolineThunks.cpp:llvm::addConstantPoolReference(llvm::MachineInstrBuilder const&, unsigned int, unsigned int, unsigned char)
Unexecuted instantiation: X86SpeculativeLoadHardening.cpp:llvm::addConstantPoolReference(llvm::MachineInstrBuilder const&, unsigned int, unsigned int, unsigned char)
Unexecuted instantiation: X86WinAllocaExpander.cpp:llvm::addConstantPoolReference(llvm::MachineInstrBuilder const&, unsigned int, unsigned int, unsigned char)
229
230
} // end namespace llvm
231
232
#endif // LLVM_LIB_TARGET_X86_X86INSTRBUILDER_H