Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/X86/X86LegalizerInfo.cpp
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//===- X86LegalizerInfo.cpp --------------------------------------*- C++ -*-==//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
/// \file
9
/// This file implements the targeting of the Machinelegalizer class for X86.
10
/// \todo This should be generated by TableGen.
11
//===----------------------------------------------------------------------===//
12
13
#include "X86LegalizerInfo.h"
14
#include "X86Subtarget.h"
15
#include "X86TargetMachine.h"
16
#include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
17
#include "llvm/CodeGen/TargetOpcodes.h"
18
#include "llvm/CodeGen/ValueTypes.h"
19
#include "llvm/IR/DerivedTypes.h"
20
#include "llvm/IR/Type.h"
21
22
using namespace llvm;
23
using namespace TargetOpcode;
24
using namespace LegalizeActions;
25
26
/// FIXME: The following static functions are SizeChangeStrategy functions
27
/// that are meant to temporarily mimic the behaviour of the old legalization
28
/// based on doubling/halving non-legal types as closely as possible. This is
29
/// not entirly possible as only legalizing the types that are exactly a power
30
/// of 2 times the size of the legal types would require specifying all those
31
/// sizes explicitly.
32
/// In practice, not specifying those isn't a problem, and the below functions
33
/// should disappear quickly as we add support for legalizing non-power-of-2
34
/// sized types further.
35
static void
36
addAndInterleaveWithUnsupported(LegalizerInfo::SizeAndActionsVec &result,
37
91.6k
                                const LegalizerInfo::SizeAndActionsVec &v) {
38
439k
  for (unsigned i = 0; i < v.size(); 
++i347k
) {
39
347k
    result.push_back(v[i]);
40
347k
    if (
i + 1 < v[i].first347k
&& i + 1 < v.size() &&
41
347k
        
v[i + 1].first != v[i].first + 1255k
)
42
255k
      result.push_back({v[i].first + 1, Unsupported});
43
347k
  }
44
91.6k
}
45
46
static LegalizerInfo::SizeAndActionsVec
47
91.6k
widen_1(const LegalizerInfo::SizeAndActionsVec &v) {
48
91.6k
  assert(v.size() >= 1);
49
91.6k
  assert(v[0].first > 1);
50
91.6k
  LegalizerInfo::SizeAndActionsVec result = {{1, WidenScalar},
51
91.6k
                                             {2, Unsupported}};
52
91.6k
  addAndInterleaveWithUnsupported(result, v);
53
91.6k
  auto Largest = result.back().first;
54
91.6k
  result.push_back({Largest + 1, Unsupported});
55
91.6k
  return result;
56
91.6k
}
57
58
X86LegalizerInfo::X86LegalizerInfo(const X86Subtarget &STI,
59
                                   const X86TargetMachine &TM)
60
15.2k
    : Subtarget(STI), TM(TM) {
61
15.2k
62
15.2k
  setLegalizerInfo32bit();
63
15.2k
  setLegalizerInfo64bit();
64
15.2k
  setLegalizerInfoSSE1();
65
15.2k
  setLegalizerInfoSSE2();
66
15.2k
  setLegalizerInfoSSE41();
67
15.2k
  setLegalizerInfoAVX();
68
15.2k
  setLegalizerInfoAVX2();
69
15.2k
  setLegalizerInfoAVX512();
70
15.2k
  setLegalizerInfoAVX512DQ();
71
15.2k
  setLegalizerInfoAVX512BW();
72
15.2k
73
15.2k
  setLegalizeScalarToDifferentSizeStrategy(G_PHI, 0, widen_1);
74
15.2k
  for (unsigned BinOp : {G_SUB, G_MUL, G_AND, G_OR, G_XOR})
75
76.3k
    setLegalizeScalarToDifferentSizeStrategy(BinOp, 0, widen_1);
76
15.2k
  for (unsigned MemOp : {G_LOAD, G_STORE})
77
30.5k
    setLegalizeScalarToDifferentSizeStrategy(MemOp, 0,
78
30.5k
       narrowToSmallerAndWidenToSmallest);
79
15.2k
  setLegalizeScalarToDifferentSizeStrategy(
80
15.2k
      G_GEP, 1, widenToLargerTypesUnsupportedOtherwise);
81
15.2k
  setLegalizeScalarToDifferentSizeStrategy(
82
15.2k
      G_CONSTANT, 0, widenToLargerTypesAndNarrowToLargest);
83
15.2k
84
15.2k
  computeTables();
85
15.2k
  verify(*STI.getInstrInfo());
86
15.2k
}
87
88
bool X86LegalizerInfo::legalizeIntrinsic(MachineInstr &MI,
89
                                         MachineRegisterInfo &MRI,
90
0
                                         MachineIRBuilder &MIRBuilder) const {
91
0
  switch (MI.getIntrinsicID()) {
92
0
  case Intrinsic::memcpy:
93
0
  case Intrinsic::memset:
94
0
  case Intrinsic::memmove:
95
0
    if (createMemLibcall(MIRBuilder, MRI, MI) ==
96
0
        LegalizerHelper::UnableToLegalize)
97
0
      return false;
98
0
    MI.eraseFromParent();
99
0
    return true;
100
0
  default:
101
0
    break;
102
0
  }
103
0
  return true;
104
0
}
105
106
15.2k
void X86LegalizerInfo::setLegalizerInfo32bit() {
107
15.2k
108
15.2k
  const LLT p0 = LLT::pointer(0, TM.getPointerSizeInBits(0));
109
15.2k
  const LLT s1 = LLT::scalar(1);
110
15.2k
  const LLT s8 = LLT::scalar(8);
111
15.2k
  const LLT s16 = LLT::scalar(16);
112
15.2k
  const LLT s32 = LLT::scalar(32);
113
15.2k
  const LLT s64 = LLT::scalar(64);
114
15.2k
  const LLT s128 = LLT::scalar(128);
115
15.2k
116
15.2k
  for (auto Ty : {p0, s1, s8, s16, s32})
117
76.3k
    setAction({G_IMPLICIT_DEF, Ty}, Legal);
118
15.2k
119
15.2k
  for (auto Ty : {s8, s16, s32, p0})
120
61.0k
    setAction({G_PHI, Ty}, Legal);
121
15.2k
122
15.2k
  for (unsigned BinOp : {G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR})
123
91.6k
    for (auto Ty : {s8, s16, s32})
124
274k
      setAction({BinOp, Ty}, Legal);
125
15.2k
126
15.2k
  for (unsigned Op : {G_UADDE}) {
127
15.2k
    setAction({Op, s32}, Legal);
128
15.2k
    setAction({Op, 1, s1}, Legal);
129
15.2k
  }
130
15.2k
131
30.5k
  for (unsigned MemOp : {G_LOAD, G_STORE}) {
132
30.5k
    for (auto Ty : {s8, s16, s32, p0})
133
122k
      setAction({MemOp, Ty}, Legal);
134
30.5k
135
30.5k
    // And everything's fine in addrspace 0.
136
30.5k
    setAction({MemOp, 1, p0}, Legal);
137
30.5k
  }
138
15.2k
139
15.2k
  // Pointer-handling
140
15.2k
  setAction({G_FRAME_INDEX, p0}, Legal);
141
15.2k
  setAction({G_GLOBAL_VALUE, p0}, Legal);
142
15.2k
143
15.2k
  setAction({G_GEP, p0}, Legal);
144
15.2k
  setAction({G_GEP, 1, s32}, Legal);
145
15.2k
146
15.2k
  if (!Subtarget.is64Bit()) {
147
3.16k
    getActionDefinitionsBuilder(G_PTRTOINT)
148
3.16k
        .legalForCartesianProduct({s1, s8, s16, s32}, {p0})
149
3.16k
        .maxScalar(0, s32)
150
3.16k
        .widenScalarToNextPow2(0, /*Min*/ 8);
151
3.16k
    getActionDefinitionsBuilder(G_INTTOPTR).legalFor({{p0, s32}});
152
3.16k
153
3.16k
    // Shifts and SDIV
154
3.16k
    getActionDefinitionsBuilder(
155
3.16k
        {G_SDIV, G_SREM, G_UDIV, G_UREM})
156
3.16k
      .legalFor({s8, s16, s32})
157
3.16k
      .clampScalar(0, s8, s32);
158
3.16k
159
3.16k
    getActionDefinitionsBuilder(
160
3.16k
        {G_SHL, G_LSHR, G_ASHR})
161
3.16k
      .legalFor({{s8, s8}, {s16, s8}, {s32, s8}})
162
3.16k
      .clampScalar(0, s8, s32)
163
3.16k
      .clampScalar(1, s8, s8);
164
3.16k
  }
165
15.2k
166
15.2k
  // Control-flow
167
15.2k
  setAction({G_BRCOND, s1}, Legal);
168
15.2k
169
15.2k
  // Constants
170
15.2k
  for (auto Ty : {s8, s16, s32, p0})
171
61.0k
    setAction({TargetOpcode::G_CONSTANT, Ty}, Legal);
172
15.2k
173
15.2k
  // Extensions
174
45.8k
  for (auto Ty : {s8, s16, s32}) {
175
45.8k
    setAction({G_ZEXT, Ty}, Legal);
176
45.8k
    setAction({G_SEXT, Ty}, Legal);
177
45.8k
    setAction({G_ANYEXT, Ty}, Legal);
178
45.8k
  }
179
15.2k
  setAction({G_ANYEXT, s128}, Legal);
180
15.2k
181
15.2k
  // Comparison
182
15.2k
  setAction({G_ICMP, s1}, Legal);
183
15.2k
184
15.2k
  for (auto Ty : {s8, s16, s32, p0})
185
61.0k
    setAction({G_ICMP, 1, Ty}, Legal);
186
15.2k
187
15.2k
  // Merge/Unmerge
188
45.8k
  for (const auto &Ty : {s16, s32, s64}) {
189
45.8k
    setAction({G_MERGE_VALUES, Ty}, Legal);
190
45.8k
    setAction({G_UNMERGE_VALUES, 1, Ty}, Legal);
191
45.8k
  }
192
45.8k
  for (const auto &Ty : {s8, s16, s32}) {
193
45.8k
    setAction({G_MERGE_VALUES, 1, Ty}, Legal);
194
45.8k
    setAction({G_UNMERGE_VALUES, Ty}, Legal);
195
45.8k
  }
196
15.2k
}
197
198
15.2k
void X86LegalizerInfo::setLegalizerInfo64bit() {
199
15.2k
200
15.2k
  if (!Subtarget.is64Bit())
201
3.16k
    return;
202
12.1k
203
12.1k
  const LLT p0 = LLT::pointer(0, TM.getPointerSizeInBits(0));
204
12.1k
  const LLT s1 = LLT::scalar(1);
205
12.1k
  const LLT s8 = LLT::scalar(8);
206
12.1k
  const LLT s16 = LLT::scalar(16);
207
12.1k
  const LLT s32 = LLT::scalar(32);
208
12.1k
  const LLT s64 = LLT::scalar(64);
209
12.1k
  const LLT s128 = LLT::scalar(128);
210
12.1k
211
12.1k
  setAction({G_IMPLICIT_DEF, s64}, Legal);
212
12.1k
  // Need to have that, as tryFoldImplicitDef will create this pattern:
213
12.1k
  // s128 = EXTEND (G_IMPLICIT_DEF s32/s64) -> s128 = G_IMPLICIT_DEF
214
12.1k
  setAction({G_IMPLICIT_DEF, s128}, Legal);
215
12.1k
216
12.1k
  setAction({G_PHI, s64}, Legal);
217
12.1k
218
12.1k
  for (unsigned BinOp : {G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR})
219
72.6k
    setAction({BinOp, s64}, Legal);
220
12.1k
221
12.1k
  for (unsigned MemOp : {G_LOAD, G_STORE})
222
24.2k
    setAction({MemOp, s64}, Legal);
223
12.1k
224
12.1k
  // Pointer-handling
225
12.1k
  setAction({G_GEP, 1, s64}, Legal);
226
12.1k
  getActionDefinitionsBuilder(G_PTRTOINT)
227
12.1k
      .legalForCartesianProduct({s1, s8, s16, s32, s64}, {p0})
228
12.1k
      .maxScalar(0, s64)
229
12.1k
      .widenScalarToNextPow2(0, /*Min*/ 8);
230
12.1k
  getActionDefinitionsBuilder(G_INTTOPTR).legalFor({{p0, s64}});
231
12.1k
232
12.1k
  // Constants
233
12.1k
  setAction({TargetOpcode::G_CONSTANT, s64}, Legal);
234
12.1k
235
12.1k
  // Extensions
236
36.3k
  for (unsigned extOp : {G_ZEXT, G_SEXT, G_ANYEXT}) {
237
36.3k
    setAction({extOp, s64}, Legal);
238
36.3k
  }
239
12.1k
240
12.1k
  getActionDefinitionsBuilder(G_SITOFP)
241
12.1k
    .legalForCartesianProduct({s32, s64})
242
12.1k
      .clampScalar(1, s32, s64)
243
12.1k
      .widenScalarToNextPow2(1)
244
12.1k
      .clampScalar(0, s32, s64)
245
12.1k
      .widenScalarToNextPow2(0);
246
12.1k
247
12.1k
  getActionDefinitionsBuilder(G_FPTOSI)
248
12.1k
      .legalForCartesianProduct({s32, s64})
249
12.1k
      .clampScalar(1, s32, s64)
250
12.1k
      .widenScalarToNextPow2(0)
251
12.1k
      .clampScalar(0, s32, s64)
252
12.1k
      .widenScalarToNextPow2(1);
253
12.1k
254
12.1k
  // Comparison
255
12.1k
  setAction({G_ICMP, 1, s64}, Legal);
256
12.1k
257
12.1k
  getActionDefinitionsBuilder(G_FCMP)
258
12.1k
      .legalForCartesianProduct({s8}, {s32, s64})
259
12.1k
      .clampScalar(0, s8, s8)
260
12.1k
      .clampScalar(1, s32, s64)
261
12.1k
      .widenScalarToNextPow2(1);
262
12.1k
263
12.1k
  // Divisions
264
12.1k
  getActionDefinitionsBuilder(
265
12.1k
      {G_SDIV, G_SREM, G_UDIV, G_UREM})
266
12.1k
      .legalFor({s8, s16, s32, s64})
267
12.1k
      .clampScalar(0, s8, s64);
268
12.1k
269
12.1k
  // Shifts
270
12.1k
  getActionDefinitionsBuilder(
271
12.1k
    {G_SHL, G_LSHR, G_ASHR})
272
12.1k
    .legalFor({{s8, s8}, {s16, s8}, {s32, s8}, {s64, s8}})
273
12.1k
    .clampScalar(0, s8, s64)
274
12.1k
    .clampScalar(1, s8, s8);
275
12.1k
276
12.1k
  // Merge/Unmerge
277
12.1k
  setAction({G_MERGE_VALUES, s128}, Legal);
278
12.1k
  setAction({G_UNMERGE_VALUES, 1, s128}, Legal);
279
12.1k
  setAction({G_MERGE_VALUES, 1, s128}, Legal);
280
12.1k
  setAction({G_UNMERGE_VALUES, s128}, Legal);
281
12.1k
}
282
283
15.2k
void X86LegalizerInfo::setLegalizerInfoSSE1() {
284
15.2k
  if (!Subtarget.hasSSE1())
285
1.64k
    return;
286
13.6k
287
13.6k
  const LLT s32 = LLT::scalar(32);
288
13.6k
  const LLT s64 = LLT::scalar(64);
289
13.6k
  const LLT v4s32 = LLT::vector(4, 32);
290
13.6k
  const LLT v2s64 = LLT::vector(2, 64);
291
13.6k
292
13.6k
  for (unsigned BinOp : {G_FADD, G_FSUB, G_FMUL, G_FDIV})
293
54.4k
    for (auto Ty : {s32, v4s32})
294
108k
      setAction({BinOp, Ty}, Legal);
295
13.6k
296
13.6k
  for (unsigned MemOp : {G_LOAD, G_STORE})
297
27.2k
    for (auto Ty : {v4s32, v2s64})
298
54.5k
      setAction({MemOp, Ty}, Legal);
299
13.6k
300
13.6k
  // Constants
301
13.6k
  setAction({TargetOpcode::G_FCONSTANT, s32}, Legal);
302
13.6k
303
13.6k
  // Merge/Unmerge
304
27.2k
  for (const auto &Ty : {v4s32, v2s64}) {
305
27.2k
    setAction({G_CONCAT_VECTORS, Ty}, Legal);
306
27.2k
    setAction({G_UNMERGE_VALUES, 1, Ty}, Legal);
307
27.2k
  }
308
13.6k
  setAction({G_MERGE_VALUES, 1, s64}, Legal);
309
13.6k
  setAction({G_UNMERGE_VALUES, s64}, Legal);
310
13.6k
}
311
312
15.2k
void X86LegalizerInfo::setLegalizerInfoSSE2() {
313
15.2k
  if (!Subtarget.hasSSE2())
314
1.71k
    return;
315
13.5k
316
13.5k
  const LLT s32 = LLT::scalar(32);
317
13.5k
  const LLT s64 = LLT::scalar(64);
318
13.5k
  const LLT v16s8 = LLT::vector(16, 8);
319
13.5k
  const LLT v8s16 = LLT::vector(8, 16);
320
13.5k
  const LLT v4s32 = LLT::vector(4, 32);
321
13.5k
  const LLT v2s64 = LLT::vector(2, 64);
322
13.5k
323
13.5k
  const LLT v32s8 = LLT::vector(32, 8);
324
13.5k
  const LLT v16s16 = LLT::vector(16, 16);
325
13.5k
  const LLT v8s32 = LLT::vector(8, 32);
326
13.5k
  const LLT v4s64 = LLT::vector(4, 64);
327
13.5k
328
13.5k
  for (unsigned BinOp : {G_FADD, G_FSUB, G_FMUL, G_FDIV})
329
54.2k
    for (auto Ty : {s64, v2s64})
330
108k
      setAction({BinOp, Ty}, Legal);
331
13.5k
332
13.5k
  for (unsigned BinOp : {G_ADD, G_SUB})
333
27.1k
    for (auto Ty : {v16s8, v8s16, v4s32, v2s64})
334
108k
      setAction({BinOp, Ty}, Legal);
335
13.5k
336
13.5k
  setAction({G_MUL, v8s16}, Legal);
337
13.5k
338
13.5k
  setAction({G_FPEXT, s64}, Legal);
339
13.5k
  setAction({G_FPEXT, 1, s32}, Legal);
340
13.5k
341
13.5k
  setAction({G_FPTRUNC, s32}, Legal);
342
13.5k
  setAction({G_FPTRUNC, 1, s64}, Legal);
343
13.5k
344
13.5k
  // Constants
345
13.5k
  setAction({TargetOpcode::G_FCONSTANT, s64}, Legal);
346
13.5k
347
13.5k
  // Merge/Unmerge
348
13.5k
  for (const auto &Ty :
349
108k
       {v16s8, v32s8, v8s16, v16s16, v4s32, v8s32, v2s64, v4s64}) {
350
108k
    setAction({G_CONCAT_VECTORS, Ty}, Legal);
351
108k
    setAction({G_UNMERGE_VALUES, 1, Ty}, Legal);
352
108k
  }
353
54.2k
  for (const auto &Ty : {v16s8, v8s16, v4s32, v2s64}) {
354
54.2k
    setAction({G_CONCAT_VECTORS, 1, Ty}, Legal);
355
54.2k
    setAction({G_UNMERGE_VALUES, Ty}, Legal);
356
54.2k
  }
357
13.5k
}
358
359
15.2k
void X86LegalizerInfo::setLegalizerInfoSSE41() {
360
15.2k
  if (!Subtarget.hasSSE41())
361
9.64k
    return;
362
5.63k
363
5.63k
  const LLT v4s32 = LLT::vector(4, 32);
364
5.63k
365
5.63k
  setAction({G_MUL, v4s32}, Legal);
366
5.63k
}
367
368
15.2k
void X86LegalizerInfo::setLegalizerInfoAVX() {
369
15.2k
  if (!Subtarget.hasAVX())
370
10.7k
    return;
371
4.53k
372
4.53k
  const LLT v16s8 = LLT::vector(16, 8);
373
4.53k
  const LLT v8s16 = LLT::vector(8, 16);
374
4.53k
  const LLT v4s32 = LLT::vector(4, 32);
375
4.53k
  const LLT v2s64 = LLT::vector(2, 64);
376
4.53k
377
4.53k
  const LLT v32s8 = LLT::vector(32, 8);
378
4.53k
  const LLT v64s8 = LLT::vector(64, 8);
379
4.53k
  const LLT v16s16 = LLT::vector(16, 16);
380
4.53k
  const LLT v32s16 = LLT::vector(32, 16);
381
4.53k
  const LLT v8s32 = LLT::vector(8, 32);
382
4.53k
  const LLT v16s32 = LLT::vector(16, 32);
383
4.53k
  const LLT v4s64 = LLT::vector(4, 64);
384
4.53k
  const LLT v8s64 = LLT::vector(8, 64);
385
4.53k
386
4.53k
  for (unsigned MemOp : {G_LOAD, G_STORE})
387
9.06k
    for (auto Ty : {v8s32, v4s64})
388
18.1k
      setAction({MemOp, Ty}, Legal);
389
4.53k
390
18.1k
  for (auto Ty : {v32s8, v16s16, v8s32, v4s64}) {
391
18.1k
    setAction({G_INSERT, Ty}, Legal);
392
18.1k
    setAction({G_EXTRACT, 1, Ty}, Legal);
393
18.1k
  }
394
18.1k
  for (auto Ty : {v16s8, v8s16, v4s32, v2s64}) {
395
18.1k
    setAction({G_INSERT, 1, Ty}, Legal);
396
18.1k
    setAction({G_EXTRACT, Ty}, Legal);
397
18.1k
  }
398
4.53k
  // Merge/Unmerge
399
4.53k
  for (const auto &Ty :
400
36.2k
       {v32s8, v64s8, v16s16, v32s16, v8s32, v16s32, v4s64, v8s64}) {
401
36.2k
    setAction({G_CONCAT_VECTORS, Ty}, Legal);
402
36.2k
    setAction({G_UNMERGE_VALUES, 1, Ty}, Legal);
403
36.2k
  }
404
4.53k
  for (const auto &Ty :
405
36.2k
       {v16s8, v32s8, v8s16, v16s16, v4s32, v8s32, v2s64, v4s64}) {
406
36.2k
    setAction({G_CONCAT_VECTORS, 1, Ty}, Legal);
407
36.2k
    setAction({G_UNMERGE_VALUES, Ty}, Legal);
408
36.2k
  }
409
4.53k
}
410
411
15.2k
void X86LegalizerInfo::setLegalizerInfoAVX2() {
412
15.2k
  if (!Subtarget.hasAVX2())
413
11.8k
    return;
414
3.40k
415
3.40k
  const LLT v32s8 = LLT::vector(32, 8);
416
3.40k
  const LLT v16s16 = LLT::vector(16, 16);
417
3.40k
  const LLT v8s32 = LLT::vector(8, 32);
418
3.40k
  const LLT v4s64 = LLT::vector(4, 64);
419
3.40k
420
3.40k
  const LLT v64s8 = LLT::vector(64, 8);
421
3.40k
  const LLT v32s16 = LLT::vector(32, 16);
422
3.40k
  const LLT v16s32 = LLT::vector(16, 32);
423
3.40k
  const LLT v8s64 = LLT::vector(8, 64);
424
3.40k
425
3.40k
  for (unsigned BinOp : {G_ADD, G_SUB})
426
6.80k
    for (auto Ty : {v32s8, v16s16, v8s32, v4s64})
427
27.2k
      setAction({BinOp, Ty}, Legal);
428
3.40k
429
3.40k
  for (auto Ty : {v16s16, v8s32})
430
6.80k
    setAction({G_MUL, Ty}, Legal);
431
3.40k
432
3.40k
  // Merge/Unmerge
433
13.6k
  for (const auto &Ty : {v64s8, v32s16, v16s32, v8s64}) {
434
13.6k
    setAction({G_CONCAT_VECTORS, Ty}, Legal);
435
13.6k
    setAction({G_UNMERGE_VALUES, 1, Ty}, Legal);
436
13.6k
  }
437
13.6k
  for (const auto &Ty : {v32s8, v16s16, v8s32, v4s64}) {
438
13.6k
    setAction({G_CONCAT_VECTORS, 1, Ty}, Legal);
439
13.6k
    setAction({G_UNMERGE_VALUES, Ty}, Legal);
440
13.6k
  }
441
3.40k
}
442
443
15.2k
void X86LegalizerInfo::setLegalizerInfoAVX512() {
444
15.2k
  if (!Subtarget.hasAVX512())
445
13.5k
    return;
446
1.67k
447
1.67k
  const LLT v16s8 = LLT::vector(16, 8);
448
1.67k
  const LLT v8s16 = LLT::vector(8, 16);
449
1.67k
  const LLT v4s32 = LLT::vector(4, 32);
450
1.67k
  const LLT v2s64 = LLT::vector(2, 64);
451
1.67k
452
1.67k
  const LLT v32s8 = LLT::vector(32, 8);
453
1.67k
  const LLT v16s16 = LLT::vector(16, 16);
454
1.67k
  const LLT v8s32 = LLT::vector(8, 32);
455
1.67k
  const LLT v4s64 = LLT::vector(4, 64);
456
1.67k
457
1.67k
  const LLT v64s8 = LLT::vector(64, 8);
458
1.67k
  const LLT v32s16 = LLT::vector(32, 16);
459
1.67k
  const LLT v16s32 = LLT::vector(16, 32);
460
1.67k
  const LLT v8s64 = LLT::vector(8, 64);
461
1.67k
462
1.67k
  for (unsigned BinOp : {G_ADD, G_SUB})
463
3.33k
    for (auto Ty : {v16s32, v8s64})
464
6.67k
      setAction({BinOp, Ty}, Legal);
465
1.67k
466
1.67k
  setAction({G_MUL, v16s32}, Legal);
467
1.67k
468
1.67k
  for (unsigned MemOp : {G_LOAD, G_STORE})
469
3.33k
    for (auto Ty : {v16s32, v8s64})
470
6.67k
      setAction({MemOp, Ty}, Legal);
471
1.67k
472
6.67k
  for (auto Ty : {v64s8, v32s16, v16s32, v8s64}) {
473
6.67k
    setAction({G_INSERT, Ty}, Legal);
474
6.67k
    setAction({G_EXTRACT, 1, Ty}, Legal);
475
6.67k
  }
476
13.3k
  for (auto Ty : {v32s8, v16s16, v8s32, v4s64, v16s8, v8s16, v4s32, v2s64}) {
477
13.3k
    setAction({G_INSERT, 1, Ty}, Legal);
478
13.3k
    setAction({G_EXTRACT, Ty}, Legal);
479
13.3k
  }
480
1.67k
481
1.67k
  /************ VLX *******************/
482
1.67k
  if (!Subtarget.hasVLX())
483
883
    return;
484
792
485
792
  for (auto Ty : {v4s32, v8s32})
486
1.57k
    setAction({G_MUL, Ty}, Legal);
487
792
}
488
489
15.2k
void X86LegalizerInfo::setLegalizerInfoAVX512DQ() {
490
15.2k
  if (!(Subtarget.hasAVX512() && 
Subtarget.hasDQI()1.66k
))
491
14.8k
    return;
492
452
493
452
  const LLT v8s64 = LLT::vector(8, 64);
494
452
495
452
  setAction({G_MUL, v8s64}, Legal);
496
452
497
452
  /************ VLX *******************/
498
452
  if (!Subtarget.hasVLX())
499
104
    return;
500
348
501
348
  const LLT v2s64 = LLT::vector(2, 64);
502
348
  const LLT v4s64 = LLT::vector(4, 64);
503
348
504
348
  for (auto Ty : {v2s64, v4s64})
505
700
    setAction({G_MUL, Ty}, Legal);
506
348
}
507
508
15.2k
void X86LegalizerInfo::setLegalizerInfoAVX512BW() {
509
15.2k
  if (!(Subtarget.hasAVX512() && 
Subtarget.hasBWI()1.66k
))
510
14.4k
    return;
511
793
512
793
  const LLT v64s8 = LLT::vector(64, 8);
513
793
  const LLT v32s16 = LLT::vector(32, 16);
514
793
515
793
  for (unsigned BinOp : {G_ADD, G_SUB})
516
1.57k
    for (auto Ty : {v64s8, v32s16})
517
3.14k
      setAction({BinOp, Ty}, Legal);
518
793
519
793
  setAction({G_MUL, v32s16}, Legal);
520
793
521
793
  /************ VLX *******************/
522
793
  if (!Subtarget.hasVLX())
523
294
    return;
524
499
525
499
  const LLT v8s16 = LLT::vector(8, 16);
526
499
  const LLT v16s16 = LLT::vector(16, 16);
527
499
528
499
  for (auto Ty : {v8s16, v16s16})
529
986
    setAction({G_MUL, Ty}, Legal);
530
499
}