Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/X86/X86RegisterInfo.cpp
Line
Count
Source (jump to first uncovered line)
1
//===-- X86RegisterInfo.cpp - X86 Register Information --------------------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file contains the X86 implementation of the TargetRegisterInfo class.
10
// This file is responsible for the frame pointer elimination optimization
11
// on X86.
12
//
13
//===----------------------------------------------------------------------===//
14
15
#include "X86RegisterInfo.h"
16
#include "X86FrameLowering.h"
17
#include "X86MachineFunctionInfo.h"
18
#include "X86Subtarget.h"
19
#include "llvm/ADT/BitVector.h"
20
#include "llvm/ADT/STLExtras.h"
21
#include "llvm/CodeGen/MachineFrameInfo.h"
22
#include "llvm/CodeGen/MachineFunction.h"
23
#include "llvm/CodeGen/MachineFunctionPass.h"
24
#include "llvm/CodeGen/MachineRegisterInfo.h"
25
#include "llvm/CodeGen/TargetFrameLowering.h"
26
#include "llvm/CodeGen/TargetInstrInfo.h"
27
#include "llvm/IR/Constants.h"
28
#include "llvm/IR/Function.h"
29
#include "llvm/IR/Type.h"
30
#include "llvm/Support/CommandLine.h"
31
#include "llvm/Support/ErrorHandling.h"
32
#include "llvm/Target/TargetMachine.h"
33
#include "llvm/Target/TargetOptions.h"
34
35
using namespace llvm;
36
37
#define GET_REGINFO_TARGET_DESC
38
#include "X86GenRegisterInfo.inc"
39
40
static cl::opt<bool>
41
EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true),
42
          cl::desc("Enable use of a base pointer for complex stack frames"));
43
44
X86RegisterInfo::X86RegisterInfo(const Triple &TT)
45
    : X86GenRegisterInfo((TT.isArch64Bit() ? X86::RIP : X86::EIP),
46
                         X86_MC::getDwarfRegFlavour(TT, false),
47
                         X86_MC::getDwarfRegFlavour(TT, true),
48
15.2k
                         (TT.isArch64Bit() ? X86::RIP : X86::EIP)) {
49
15.2k
  X86_MC::initLLVMToSEHAndCVRegMapping(this);
50
15.2k
51
15.2k
  // Cache some information.
52
15.2k
  Is64Bit = TT.isArch64Bit();
53
15.2k
  IsWin64 = Is64Bit && 
TT.isOSWindows()12.1k
;
54
15.2k
55
15.2k
  // Use a callee-saved register as the base pointer.  These registers must
56
15.2k
  // not conflict with any ABI requirements.  For example, in 32-bit mode PIC
57
15.2k
  // requires GOT in the EBX register before function calls via PLT GOT pointer.
58
15.2k
  if (Is64Bit) {
59
12.1k
    SlotSize = 8;
60
12.1k
    // This matches the simplified 32-bit pointer code in the data layout
61
12.1k
    // computation.
62
12.1k
    // FIXME: Should use the data layout?
63
12.1k
    bool Use64BitReg = TT.getEnvironment() != Triple::GNUX32;
64
12.1k
    StackPtr = Use64BitReg ? 
X86::RSP12.0k
:
X86::ESP61
;
65
12.1k
    FramePtr = Use64BitReg ? 
X86::RBP12.0k
:
X86::EBP61
;
66
12.1k
    BasePtr = Use64BitReg ? 
X86::RBX12.0k
:
X86::EBX61
;
67
12.1k
  } else {
68
3.15k
    SlotSize = 4;
69
3.15k
    StackPtr = X86::ESP;
70
3.15k
    FramePtr = X86::EBP;
71
3.15k
    BasePtr = X86::ESI;
72
3.15k
  }
73
15.2k
}
74
75
bool
76
150k
X86RegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
77
150k
  // ExecutionDomainFix, BreakFalseDeps and PostRAScheduler require liveness.
78
150k
  return true;
79
150k
}
80
81
int
82
748
X86RegisterInfo::getSEHRegNum(unsigned i) const {
83
748
  return getEncodingValue(i);
84
748
}
85
86
const TargetRegisterClass *
87
X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC,
88
178k
                                       unsigned Idx) const {
89
178k
  // The sub_8bit sub-register index is more constrained in 32-bit mode.
90
178k
  // It behaves just like the sub_8bit_hi index.
91
178k
  if (!Is64Bit && 
Idx == X86::sub_8bit9.83k
)
92
5.74k
    Idx = X86::sub_8bit_hi;
93
178k
94
178k
  // Forward to TableGen's default version.
95
178k
  return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
96
178k
}
97
98
const TargetRegisterClass *
99
X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
100
                                          const TargetRegisterClass *B,
101
262k
                                          unsigned SubIdx) const {
102
262k
  // The sub_8bit sub-register index is more constrained in 32-bit mode.
103
262k
  if (!Is64Bit && 
SubIdx == X86::sub_8bit21.5k
) {
104
14.1k
    A = X86GenRegisterInfo::getSubClassWithSubReg(A, X86::sub_8bit_hi);
105
14.1k
    if (!A)
106
0
      return nullptr;
107
262k
  }
108
262k
  return X86GenRegisterInfo::getMatchingSuperRegClass(A, B, SubIdx);
109
262k
}
110
111
const TargetRegisterClass *
112
X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
113
451k
                                           const MachineFunction &MF) const {
114
451k
  // Don't allow super-classes of GR8_NOREX.  This class is only used after
115
451k
  // extracting sub_8bit_hi sub-registers.  The H sub-registers cannot be copied
116
451k
  // to the full GR8 register class in 64-bit mode, so we cannot allow the
117
451k
  // reigster class inflation.
118
451k
  //
119
451k
  // The GR8_NOREX class is always used in a way that won't be constrained to a
120
451k
  // sub-class, so sub-classes like GR8_ABCD_L are allowed to expand to the
121
451k
  // full GR8 class.
122
451k
  if (RC == &X86::GR8_NOREXRegClass)
123
5.91k
    return RC;
124
445k
125
445k
  const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
126
445k
127
445k
  const TargetRegisterClass *Super = RC;
128
445k
  TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
129
750k
  do {
130
750k
    switch (Super->getID()) {
131
750k
    case X86::FR32RegClassID:
132
9.66k
    case X86::FR64RegClassID:
133
9.66k
      // If AVX-512 isn't supported we should only inflate to these classes.
134
9.66k
      if (!Subtarget.hasAVX512() &&
135
9.66k
          
getRegSizeInBits(*Super) == getRegSizeInBits(*RC)7.51k
)
136
7.51k
        return Super;
137
2.14k
      break;
138
17.0k
    case X86::VR128RegClassID:
139
17.0k
    case X86::VR256RegClassID:
140
17.0k
      // If VLX isn't supported we should only inflate to these classes.
141
17.0k
      if (!Subtarget.hasVLX() &&
142
17.0k
          
getRegSizeInBits(*Super) == getRegSizeInBits(*RC)15.9k
)
143
15.9k
        return Super;
144
1.02k
      break;
145
2.99k
    case X86::VR128XRegClassID:
146
2.99k
    case X86::VR256XRegClassID:
147
2.99k
      // If VLX isn't support we shouldn't inflate to these classes.
148
2.99k
      if (Subtarget.hasVLX() &&
149
2.99k
          
getRegSizeInBits(*Super) == getRegSizeInBits(*RC)2.95k
)
150
2.95k
        return Super;
151
39
      break;
152
9.61k
    case X86::FR32XRegClassID:
153
9.61k
    case X86::FR64XRegClassID:
154
9.61k
      // If AVX-512 isn't support we shouldn't inflate to these classes.
155
9.61k
      if (Subtarget.hasAVX512() &&
156
9.61k
          
getRegSizeInBits(*Super) == getRegSizeInBits(*RC)4.71k
)
157
3.54k
        return Super;
158
6.07k
      break;
159
316k
    case X86::GR8RegClassID:
160
316k
    case X86::GR16RegClassID:
161
316k
    case X86::GR32RegClassID:
162
316k
    case X86::GR64RegClassID:
163
316k
    case X86::RFP32RegClassID:
164
316k
    case X86::RFP64RegClassID:
165
316k
    case X86::RFP80RegClassID:
166
316k
    case X86::VR512_0_15RegClassID:
167
316k
    case X86::VR512RegClassID:
168
316k
      // Don't return a super-class that would shrink the spill size.
169
316k
      // That can happen with the vector and float classes.
170
316k
      if (getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
171
316k
        return Super;
172
403k
    }
173
403k
    Super = *I++;
174
403k
  } while (Super);
175
445k
  
return RC99.4k
;
176
445k
}
177
178
const TargetRegisterClass *
179
X86RegisterInfo::getPointerRegClass(const MachineFunction &MF,
180
1.28M
                                    unsigned Kind) const {
181
1.28M
  const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
182
1.28M
  switch (Kind) {
183
1.28M
  
default: 0
llvm_unreachable0
("Unexpected Kind in getPointerRegClass!");
184
1.28M
  case 0: // Normal GPRs.
185
756k
    if (Subtarget.isTarget64BitLP64())
186
513k
      return &X86::GR64RegClass;
187
243k
    // If the target is 64bit but we have been told to use 32bit addresses,
188
243k
    // we can still use 64-bit register as long as we know the high bits
189
243k
    // are zeros.
190
243k
    // Reflect that in the returned register class.
191
243k
    if (Is64Bit) {
192
1.44k
      // When the target also allows 64-bit frame pointer and we do have a
193
1.44k
      // frame, this is fine to use it for the address accesses as well.
194
1.44k
      const X86FrameLowering *TFI = getFrameLowering(MF);
195
1.44k
      return TFI->hasFP(MF) && 
TFI->Uses64BitFramePtr77
196
1.44k
                 ? 
&X86::LOW32_ADDR_ACCESS_RBPRegClass24
197
1.44k
                 : 
&X86::LOW32_ADDR_ACCESSRegClass1.41k
;
198
1.44k
    }
199
241k
    return &X86::GR32RegClass;
200
520k
  case 1: // Normal GPRs except the stack pointer (for encoding reasons).
201
520k
    if (Subtarget.isTarget64BitLP64())
202
359k
      return &X86::GR64_NOSPRegClass;
203
161k
    // NOSP does not contain RIP, so no special case here.
204
161k
    return &X86::GR32_NOSPRegClass;
205
161k
  case 2: // NOREX GPRs.
206
176
    if (Subtarget.isTarget64BitLP64())
207
173
      return &X86::GR64_NOREXRegClass;
208
3
    return &X86::GR32_NOREXRegClass;
209
128
  case 3: // NOREX GPRs except the stack pointer (for encoding reasons).
210
128
    if (Subtarget.isTarget64BitLP64())
211
125
      return &X86::GR64_NOREX_NOSPRegClass;
212
3
    // NOSP does not contain RIP, so no special case here.
213
3
    return &X86::GR32_NOREX_NOSPRegClass;
214
3.04k
  case 4: // Available for tailcall (not callee-saved GPRs).
215
3.04k
    return getGPRsForTailCall(MF);
216
1.28M
  }
217
1.28M
}
218
219
bool X86RegisterInfo::shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
220
                                           unsigned DefSubReg,
221
                                           const TargetRegisterClass *SrcRC,
222
145k
                                           unsigned SrcSubReg) const {
223
145k
  // Prevent rewriting a copy where the destination size is larger than the
224
145k
  // input size. See PR41619.
225
145k
  // FIXME: Should this be factored into the base implementation somehow.
226
145k
  if (DefRC->hasSuperClassEq(&X86::GR64RegClass) && 
DefSubReg == 029.2k
&&
227
145k
      
SrcRC->hasSuperClassEq(&X86::GR64RegClass)23.2k
&&
SrcSubReg == X86::sub_32bit22.8k
)
228
3
    return false;
229
145k
230
145k
  return TargetRegisterInfo::shouldRewriteCopySrc(DefRC, DefSubReg,
231
145k
                                                  SrcRC, SrcSubReg);
232
145k
}
233
234
const TargetRegisterClass *
235
10.5k
X86RegisterInfo::getGPRsForTailCall(const MachineFunction &MF) const {
236
10.5k
  const Function &F = MF.getFunction();
237
10.5k
  if (IsWin64 || 
(F.getCallingConv() == CallingConv::Win64)10.1k
)
238
327
    return &X86::GR64_TCW64RegClass;
239
10.1k
  else if (Is64Bit)
240
8.29k
    return &X86::GR64_TCRegClass;
241
1.89k
242
1.89k
  bool hasHipeCC = (F.getCallingConv() == CallingConv::HiPE);
243
1.89k
  if (hasHipeCC)
244
3
    return &X86::GR32RegClass;
245
1.88k
  return &X86::GR32_TCRegClass;
246
1.88k
}
247
248
const TargetRegisterClass *
249
1.24k
X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
250
1.24k
  if (RC == &X86::CCRRegClass) {
251
1.24k
    if (Is64Bit)
252
799
      return &X86::GR64RegClass;
253
442
    else
254
442
      return &X86::GR32RegClass;
255
0
  }
256
0
  return RC;
257
0
}
258
259
unsigned
260
X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
261
176k
                                     MachineFunction &MF) const {
262
176k
  const X86FrameLowering *TFI = getFrameLowering(MF);
263
176k
264
176k
  unsigned FPDiff = TFI->hasFP(MF) ? 
10
: 0;
265
176k
  switch (RC->getID()) {
266
176k
  default:
267
170k
    return 0;
268
176k
  case X86::GR32RegClassID:
269
1.49k
    return 4 - FPDiff;
270
176k
  case X86::GR64RegClassID:
271
1.49k
    return 12 - FPDiff;
272
176k
  case X86::VR128RegClassID:
273
1.49k
    return Is64Bit ? 
10754
:
4740
;
274
176k
  case X86::VR64RegClassID:
275
1.49k
    return 4;
276
176k
  }
277
176k
}
278
279
const MCPhysReg *
280
1.70M
X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
281
1.70M
  assert(MF && "MachineFunction required");
282
1.70M
283
1.70M
  const X86Subtarget &Subtarget = MF->getSubtarget<X86Subtarget>();
284
1.70M
  const Function &F = MF->getFunction();
285
1.70M
  bool HasSSE = Subtarget.hasSSE1();
286
1.70M
  bool HasAVX = Subtarget.hasAVX();
287
1.70M
  bool HasAVX512 = Subtarget.hasAVX512();
288
1.70M
  bool CallsEHReturn = MF->callsEHReturn();
289
1.70M
290
1.70M
  CallingConv::ID CC = F.getCallingConv();
291
1.70M
292
1.70M
  // If attribute NoCallerSavedRegisters exists then we set X86_INTR calling
293
1.70M
  // convention because it has the CSR list.
294
1.70M
  if (MF->getFunction().hasFnAttribute("no_caller_saved_registers"))
295
7
    CC = CallingConv::X86_INTR;
296
1.70M
297
1.70M
  switch (CC) {
298
1.70M
  case CallingConv::GHC:
299
350
  case CallingConv::HiPE:
300
350
    return CSR_NoRegs_SaveList;
301
350
  case CallingConv::AnyReg:
302
30
    if (HasAVX)
303
10
      return CSR_64_AllRegs_AVX_SaveList;
304
20
    return CSR_64_AllRegs_SaveList;
305
20
  case CallingConv::PreserveMost:
306
20
    return CSR_64_RT_MostRegs_SaveList;
307
52
  case CallingConv::PreserveAll:
308
52
    if (HasAVX)
309
10
      return CSR_64_RT_AllRegs_AVX_SaveList;
310
42
    return CSR_64_RT_AllRegs_SaveList;
311
435
  case CallingConv::CXX_FAST_TLS:
312
435
    if (Is64Bit)
313
435
      return MF->getInfo<X86MachineFunctionInfo>()->isSplitCSR() ?
314
379
             CSR_64_CXX_TLS_Darwin_PE_SaveList : 
CSR_64_TLS_Darwin_SaveList56
;
315
0
    break;
316
224
  case CallingConv::Intel_OCL_BI: {
317
224
    if (HasAVX512 && 
IsWin64156
)
318
36
      return CSR_Win64_Intel_OCL_BI_AVX512_SaveList;
319
188
    if (HasAVX512 && 
Is64Bit120
)
320
40
      return CSR_64_Intel_OCL_BI_AVX512_SaveList;
321
148
    if (HasAVX && 
IsWin64119
)
322
9
      return CSR_Win64_Intel_OCL_BI_AVX_SaveList;
323
139
    if (HasAVX && 
Is64Bit110
)
324
10
      return CSR_64_Intel_OCL_BI_AVX_SaveList;
325
129
    if (!HasAVX && 
!IsWin6429
&&
Is64Bit20
)
326
10
      return CSR_64_Intel_OCL_BI_SaveList;
327
119
    break;
328
119
  }
329
119
  case CallingConv::HHVM:
330
115
    return CSR_64_HHVM_SaveList;
331
129
  case CallingConv::X86_RegCall:
332
129
    if (Is64Bit) {
333
86
      if (IsWin64) {
334
44
        return (HasSSE ? CSR_Win64_RegCall_SaveList :
335
44
                         
CSR_Win64_RegCall_NoSSE_SaveList0
);
336
44
      } else {
337
42
        return (HasSSE ? CSR_SysV64_RegCall_SaveList :
338
42
                         
CSR_SysV64_RegCall_NoSSE_SaveList0
);
339
42
      }
340
43
    } else {
341
43
      return (HasSSE ? 
CSR_32_RegCall_SaveList42
:
342
43
                       
CSR_32_RegCall_NoSSE_SaveList1
);
343
43
    }
344
9
  case CallingConv::Cold:
345
9
    if (Is64Bit)
346
9
      return CSR_64_MostRegs_SaveList;
347
0
    break;
348
283
  case CallingConv::Win64:
349
283
    if (!HasSSE)
350
40
      return CSR_Win64_NoSSE_SaveList;
351
243
    return CSR_Win64_SaveList;
352
243
  case CallingConv::X86_64_SysV:
353
28
    if (CallsEHReturn)
354
0
      return CSR_64EHRet_SaveList;
355
28
    return CSR_64_SaveList;
356
364
  case CallingConv::X86_INTR:
357
364
    if (Is64Bit) {
358
205
      if (HasAVX512)
359
56
        return CSR_64_AllRegs_AVX512_SaveList;
360
149
      if (HasAVX)
361
29
        return CSR_64_AllRegs_AVX_SaveList;
362
120
      if (HasSSE)
363
111
        return CSR_64_AllRegs_SaveList;
364
9
      return CSR_64_AllRegs_NoSSE_SaveList;
365
159
    } else {
366
159
      if (HasAVX512)
367
56
        return CSR_32_AllRegs_AVX512_SaveList;
368
103
      if (HasAVX)
369
0
        return CSR_32_AllRegs_AVX_SaveList;
370
103
      if (HasSSE)
371
16
        return CSR_32_AllRegs_SSE_SaveList;
372
87
      return CSR_32_AllRegs_SaveList;
373
87
    }
374
1.70M
  default:
375
1.70M
    break;
376
1.70M
  }
377
1.70M
378
1.70M
  if (Is64Bit) {
379
1.38M
    bool IsSwiftCC = Subtarget.getTargetLowering()->supportSwiftError() &&
380
1.38M
                     F.getAttributes().hasAttrSomewhere(Attribute::SwiftError);
381
1.38M
    if (IsSwiftCC)
382
991
      return IsWin64 ? 
CSR_Win64_SwiftError_SaveList9
383
991
                     : 
CSR_64_SwiftError_SaveList982
;
384
1.38M
385
1.38M
    if (IsWin64)
386
18.0k
      return HasSSE ? CSR_Win64_SaveList : 
CSR_Win64_NoSSE_SaveList0
;
387
1.37M
    if (CallsEHReturn)
388
823
      return CSR_64EHRet_SaveList;
389
1.36M
    return CSR_64_SaveList;
390
1.36M
  }
391
316k
392
316k
  return CallsEHReturn ? 
CSR_32EHRet_SaveList60
:
CSR_32_SaveList316k
;
393
316k
}
394
395
const MCPhysReg *X86RegisterInfo::getCalleeSavedRegsViaCopy(
396
125k
    const MachineFunction *MF) const {
397
125k
  assert(MF && "Invalid MachineFunction pointer.");
398
125k
  if (MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS &&
399
125k
      
MF->getInfo<X86MachineFunctionInfo>()->isSplitCSR()48
)
400
40
    return CSR_64_CXX_TLS_Darwin_ViaCopy_SaveList;
401
125k
  return nullptr;
402
125k
}
403
404
const uint32_t *
405
X86RegisterInfo::getCallPreservedMask(const MachineFunction &MF,
406
152k
                                      CallingConv::ID CC) const {
407
152k
  const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
408
152k
  bool HasSSE = Subtarget.hasSSE1();
409
152k
  bool HasAVX = Subtarget.hasAVX();
410
152k
  bool HasAVX512 = Subtarget.hasAVX512();
411
152k
412
152k
  switch (CC) {
413
152k
  case CallingConv::GHC:
414
20
  case CallingConv::HiPE:
415
20
    return CSR_NoRegs_RegMask;
416
38
  case CallingConv::AnyReg:
417
38
    if (HasAVX)
418
17
      return CSR_64_AllRegs_AVX_RegMask;
419
21
    return CSR_64_AllRegs_RegMask;
420
21
  case CallingConv::PreserveMost:
421
2
    return CSR_64_RT_MostRegs_RegMask;
422
21
  case CallingConv::PreserveAll:
423
2
    if (HasAVX)
424
1
      return CSR_64_RT_AllRegs_AVX_RegMask;
425
1
    return CSR_64_RT_AllRegs_RegMask;
426
6
  case CallingConv::CXX_FAST_TLS:
427
6
    if (Is64Bit)
428
6
      return CSR_64_TLS_Darwin_RegMask;
429
0
    break;
430
58
  case CallingConv::Intel_OCL_BI: {
431
58
    if (HasAVX512 && 
IsWin6432
)
432
8
      return CSR_Win64_Intel_OCL_BI_AVX512_RegMask;
433
50
    if (HasAVX512 && 
Is64Bit24
)
434
8
      return CSR_64_Intel_OCL_BI_AVX512_RegMask;
435
42
    if (HasAVX && 
IsWin6436
)
436
5
      return CSR_Win64_Intel_OCL_BI_AVX_RegMask;
437
37
    if (HasAVX && 
Is64Bit31
)
438
5
      return CSR_64_Intel_OCL_BI_AVX_RegMask;
439
32
    if (!HasAVX && 
!IsWin646
&&
Is64Bit4
)
440
2
      return CSR_64_Intel_OCL_BI_RegMask;
441
30
    break;
442
30
  }
443
30
  case CallingConv::HHVM:
444
8
    return CSR_64_HHVM_RegMask;
445
65
  case CallingConv::X86_RegCall:
446
65
    if (Is64Bit) {
447
43
      if (IsWin64) {
448
22
        return (HasSSE ? CSR_Win64_RegCall_RegMask :
449
22
                         
CSR_Win64_RegCall_NoSSE_RegMask0
);
450
22
      } else {
451
21
        return (HasSSE ? CSR_SysV64_RegCall_RegMask :
452
21
                         
CSR_SysV64_RegCall_NoSSE_RegMask0
);
453
21
      }
454
22
    } else {
455
22
      return (HasSSE ? 
CSR_32_RegCall_RegMask21
:
456
22
                       
CSR_32_RegCall_NoSSE_RegMask1
);
457
22
    }
458
0
  case CallingConv::Cold:
459
0
    if (Is64Bit)
460
0
      return CSR_64_MostRegs_RegMask;
461
0
    break;
462
7
  case CallingConv::Win64:
463
7
    return CSR_Win64_RegMask;
464
2
  case CallingConv::X86_64_SysV:
465
2
    return CSR_64_RegMask;
466
9
  case CallingConv::X86_INTR:
467
9
    if (Is64Bit) {
468
5
      if (HasAVX512)
469
0
        return CSR_64_AllRegs_AVX512_RegMask;
470
5
      if (HasAVX)
471
0
        return CSR_64_AllRegs_AVX_RegMask;
472
5
      if (HasSSE)
473
5
        return CSR_64_AllRegs_RegMask;
474
0
      return CSR_64_AllRegs_NoSSE_RegMask;
475
4
    } else {
476
4
      if (HasAVX512)
477
0
        return CSR_32_AllRegs_AVX512_RegMask;
478
4
      if (HasAVX)
479
0
        return CSR_32_AllRegs_AVX_RegMask;
480
4
      if (HasSSE)
481
4
        return CSR_32_AllRegs_SSE_RegMask;
482
0
      return CSR_32_AllRegs_RegMask;
483
0
    }
484
151k
  default:
485
151k
    break;
486
152k
  }
487
152k
488
152k
  // Unlike getCalleeSavedRegs(), we don't have MMI so we can't check
489
152k
  // callsEHReturn().
490
152k
  if (Is64Bit) {
491
130k
    const Function &F = MF.getFunction();
492
130k
    bool IsSwiftCC = Subtarget.getTargetLowering()->supportSwiftError() &&
493
130k
                     F.getAttributes().hasAttrSomewhere(Attribute::SwiftError);
494
130k
    if (IsSwiftCC)
495
37
      return IsWin64 ? 
CSR_Win64_SwiftError_RegMask1
:
CSR_64_SwiftError_RegMask36
;
496
130k
    return IsWin64 ? 
CSR_Win64_RegMask995
:
CSR_64_RegMask129k
;
497
130k
  }
498
21.6k
499
21.6k
  return CSR_32_RegMask;
500
21.6k
}
501
502
const uint32_t*
503
262
X86RegisterInfo::getNoPreservedMask() const {
504
262
  return CSR_NoRegs_RegMask;
505
262
}
506
507
354
const uint32_t *X86RegisterInfo::getDarwinTLSCallPreservedMask() const {
508
354
  return CSR_64_TLS_Darwin_RegMask;
509
354
}
510
511
416k
BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
512
416k
  BitVector Reserved(getNumRegs());
513
416k
  const X86FrameLowering *TFI = getFrameLowering(MF);
514
416k
515
416k
  // Set the floating point control register as reserved.
516
416k
  Reserved.set(X86::FPCW);
517
416k
518
416k
  // Set the stack-pointer register and its aliases as reserved.
519
2.91M
  for (MCSubRegIterator I(X86::RSP, this, /*IncludeSelf=*/true); I.isValid();
520
2.50M
       ++I)
521
2.50M
    Reserved.set(*I);
522
416k
523
416k
  // Set the Shadow Stack Pointer as reserved.
524
416k
  Reserved.set(X86::SSP);
525
416k
526
416k
  // Set the instruction pointer register and its aliases as reserved.
527
2.08M
  for (MCSubRegIterator I(X86::RIP, this, /*IncludeSelf=*/true); I.isValid();
528
1.66M
       ++I)
529
1.66M
    Reserved.set(*I);
530
416k
531
416k
  // Set the frame-pointer register and its aliases as reserved if needed.
532
416k
  if (TFI->hasFP(MF)) {
533
496k
    for (MCSubRegIterator I(X86::RBP, this, /*IncludeSelf=*/true); I.isValid();
534
425k
         ++I)
535
425k
      Reserved.set(*I);
536
70.9k
  }
537
416k
538
416k
  // Set the base-pointer register and its aliases as reserved if needed.
539
416k
  if (hasBasePointer(MF)) {
540
222
    CallingConv::ID CC = MF.getFunction().getCallingConv();
541
222
    const uint32_t *RegMask = getCallPreservedMask(MF, CC);
542
222
    if (MachineOperand::clobbersPhysReg(RegMask, getBaseRegister()))
543
0
      report_fatal_error(
544
0
        "Stack realignment in presence of dynamic allocas is not supported with"
545
0
        "this calling convention.");
546
222
547
222
    unsigned BasePtr = getX86SubSuperRegister(getBaseRegister(), 64);
548
222
    for (MCSubRegIterator I(BasePtr, this, /*IncludeSelf=*/true);
549
1.55k
         I.isValid(); 
++I1.33k
)
550
1.33k
      Reserved.set(*I);
551
222
  }
552
416k
553
416k
  // Mark the segment registers as reserved.
554
416k
  Reserved.set(X86::CS);
555
416k
  Reserved.set(X86::SS);
556
416k
  Reserved.set(X86::DS);
557
416k
  Reserved.set(X86::ES);
558
416k
  Reserved.set(X86::FS);
559
416k
  Reserved.set(X86::GS);
560
416k
561
416k
  // Mark the floating point stack registers as reserved.
562
3.75M
  for (unsigned n = 0; n != 8; 
++n3.33M
)
563
3.33M
    Reserved.set(X86::ST0 + n);
564
416k
565
416k
  // Reserve the registers that only exist in 64-bit mode.
566
416k
  if (!Is64Bit) {
567
81.3k
    // These 8-bit registers are part of the x86-64 extension even though their
568
81.3k
    // super-registers are old 32-bits.
569
81.3k
    Reserved.set(X86::SIL);
570
81.3k
    Reserved.set(X86::DIL);
571
81.3k
    Reserved.set(X86::BPL);
572
81.3k
    Reserved.set(X86::SPL);
573
81.3k
    Reserved.set(X86::SIH);
574
81.3k
    Reserved.set(X86::DIH);
575
81.3k
    Reserved.set(X86::BPH);
576
81.3k
    Reserved.set(X86::SPH);
577
81.3k
578
732k
    for (unsigned n = 0; n != 8; 
++n650k
) {
579
650k
      // R8, R9, ...
580
7.80M
      for (MCRegAliasIterator AI(X86::R8 + n, this, true); AI.isValid(); 
++AI7.15M
)
581
7.15M
        Reserved.set(*AI);
582
650k
583
650k
      // XMM8, XMM9, ...
584
2.60M
      for (MCRegAliasIterator AI(X86::XMM8 + n, this, true); AI.isValid(); 
++AI1.95M
)
585
1.95M
        Reserved.set(*AI);
586
650k
    }
587
81.3k
  }
588
416k
  if (!Is64Bit || 
!MF.getSubtarget<X86Subtarget>().hasAVX512()335k
) {
589
5.32M
    for (unsigned n = 16; n != 32; 
++n5.00M
) {
590
20.0M
      for (MCRegAliasIterator AI(X86::XMM0 + n, this, true); AI.isValid(); 
++AI15.0M
)
591
15.0M
        Reserved.set(*AI);
592
5.00M
    }
593
313k
  }
594
416k
595
416k
  assert(checkAllSuperRegsMarked(Reserved,
596
416k
                                 {X86::SIL, X86::DIL, X86::BPL, X86::SPL,
597
416k
                                  X86::SIH, X86::DIH, X86::BPH, X86::SPH}));
598
416k
  return Reserved;
599
416k
}
600
601
66
void X86RegisterInfo::adjustStackMapLiveOutMask(uint32_t *Mask) const {
602
66
  // Check if the EFLAGS register is marked as live-out. This shouldn't happen,
603
66
  // because the calling convention defines the EFLAGS register as NOT
604
66
  // preserved.
605
66
  //
606
66
  // Unfortunatelly the EFLAGS show up as live-out after branch folding. Adding
607
66
  // an assert to track this and clear the register afterwards to avoid
608
66
  // unnecessary crashes during release builds.
609
66
  assert(!(Mask[X86::EFLAGS / 32] & (1U << (X86::EFLAGS % 32))) &&
610
66
         "EFLAGS are not live-out from a patchpoint.");
611
66
612
66
  // Also clean other registers that don't need preserving (IP).
613
66
  for (auto Reg : {X86::EFLAGS, X86::RIP, X86::EIP, X86::IP})
614
264
    Mask[Reg / 32] &= ~(1U << (Reg % 32));
615
66
}
616
617
//===----------------------------------------------------------------------===//
618
// Stack Frame Processing methods
619
//===----------------------------------------------------------------------===//
620
621
176k
static bool CantUseSP(const MachineFrameInfo &MFI) {
622
176k
  return MFI.hasVarSizedObjects() || 
MFI.hasOpaqueSPAdjustment()171k
;
623
176k
}
624
625
1.31M
bool X86RegisterInfo::hasBasePointer(const MachineFunction &MF) const {
626
1.31M
   const MachineFrameInfo &MFI = MF.getFrameInfo();
627
1.31M
628
1.31M
   if (!EnableBasePointer)
629
70
     return false;
630
1.31M
631
1.31M
   // When we need stack realignment, we can't address the stack from the frame
632
1.31M
   // pointer.  When we have dynamic allocas or stack-adjusting inline asm, we
633
1.31M
   // can't address variables from the stack pointer.  MS inline asm can
634
1.31M
   // reference locals while also adjusting the stack pointer.  When we can't
635
1.31M
   // use both the SP and the FP, we need a separate base pointer register.
636
1.31M
   bool CantUseFP = needsStackRealignment(MF);
637
1.31M
   return CantUseFP && 
CantUseSP(MFI)44.9k
;
638
1.31M
}
639
640
176k
bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
641
176k
  if (!TargetRegisterInfo::canRealignStack(MF))
642
0
    return false;
643
176k
644
176k
  const MachineFrameInfo &MFI = MF.getFrameInfo();
645
176k
  const MachineRegisterInfo *MRI = &MF.getRegInfo();
646
176k
647
176k
  // Stack realignment requires a frame pointer.  If we already started
648
176k
  // register allocation with frame pointer elimination, it is too late now.
649
176k
  if (!MRI->canReserveReg(FramePtr))
650
44.6k
    return false;
651
131k
652
131k
  // If a base pointer is necessary.  Check that it isn't too late to reserve
653
131k
  // it.
654
131k
  if (CantUseSP(MFI))
655
4.57k
    return MRI->canReserveReg(BasePtr);
656
127k
  return true;
657
127k
}
658
659
bool X86RegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
660
0
                                           unsigned Reg, int &FrameIdx) const {
661
0
  // Since X86 defines assignCalleeSavedSpillSlots which always return true
662
0
  // this function neither used nor tested.
663
0
  llvm_unreachable("Unused function on X86. Otherwise need a test case.");
664
0
}
665
666
// tryOptimizeLEAtoMOV - helper function that tries to replace a LEA instruction
667
// of the form 'lea (%esp), %ebx' --> 'mov %esp, %ebx'.
668
// TODO: In this case we should be really trying first to entirely eliminate
669
// this instruction which is a plain copy.
670
7.07k
static bool tryOptimizeLEAtoMOV(MachineBasicBlock::iterator II) {
671
7.07k
  MachineInstr &MI = *II;
672
7.07k
  unsigned Opc = II->getOpcode();
673
7.07k
  // Check if this is a LEA of the form 'lea (%esp), %ebx'
674
7.07k
  if ((Opc != X86::LEA32r && 
Opc != X86::LEA64r6.92k
&&
Opc != X86::LEA64_32r6.62k
) ||
675
7.07k
      
MI.getOperand(2).getImm() != 1468
||
676
7.07k
      
MI.getOperand(3).getReg() != X86::NoRegister462
||
677
7.07k
      
MI.getOperand(4).getImm() != 0462
||
678
7.07k
      
MI.getOperand(5).getReg() != X86::NoRegister462
)
679
6.61k
    return false;
680
462
  unsigned BasePtr = MI.getOperand(1).getReg();
681
462
  // In X32 mode, ensure the base-pointer is a 32-bit operand, so the LEA will
682
462
  // be replaced with a 32-bit operand MOV which will zero extend the upper
683
462
  // 32-bits of the super register.
684
462
  if (Opc == X86::LEA64_32r)
685
12
    BasePtr = getX86SubSuperRegister(BasePtr, 32);
686
462
  unsigned NewDestReg = MI.getOperand(0).getReg();
687
462
  const X86InstrInfo *TII =
688
462
      MI.getParent()->getParent()->getSubtarget<X86Subtarget>().getInstrInfo();
689
462
  TII->copyPhysReg(*MI.getParent(), II, MI.getDebugLoc(), NewDestReg, BasePtr,
690
462
                   MI.getOperand(1).isKill());
691
462
  MI.eraseFromParent();
692
462
  return true;
693
462
}
694
695
void
696
X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
697
                                     int SPAdj, unsigned FIOperandNum,
698
225k
                                     RegScavenger *RS) const {
699
225k
  MachineInstr &MI = *II;
700
225k
  MachineFunction &MF = *MI.getParent()->getParent();
701
225k
  const X86FrameLowering *TFI = getFrameLowering(MF);
702
225k
  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
703
225k
704
225k
  // Determine base register and offset.
705
225k
  int FIOffset;
706
225k
  unsigned BasePtr;
707
225k
  if (MI.isReturn()) {
708
9
    assert((!needsStackRealignment(MF) ||
709
9
           MF.getFrameInfo().isFixedObjectIndex(FrameIndex)) &&
710
9
           "Return instruction can only reference SP relative frame objects");
711
9
    FIOffset = TFI->getFrameIndexReferenceSP(MF, FrameIndex, BasePtr, 0);
712
225k
  } else {
713
225k
    FIOffset = TFI->getFrameIndexReference(MF, FrameIndex, BasePtr);
714
225k
  }
715
225k
716
225k
  // LOCAL_ESCAPE uses a single offset, with no register. It only works in the
717
225k
  // simple FP case, and doesn't work with stack realignment. On 32-bit, the
718
225k
  // offset is from the traditional base pointer location.  On 64-bit, the
719
225k
  // offset is from the SP at the end of the prologue, not the FP location. This
720
225k
  // matches the behavior of llvm.frameaddress.
721
225k
  unsigned Opc = MI.getOpcode();
722
225k
  if (Opc == TargetOpcode::LOCAL_ESCAPE) {
723
19
    MachineOperand &FI = MI.getOperand(FIOperandNum);
724
19
    FI.ChangeToImmediate(FIOffset);
725
19
    return;
726
19
  }
727
225k
728
225k
  // For LEA64_32r when BasePtr is 32-bits (X32) we can use full-size 64-bit
729
225k
  // register as source operand, semantic is the same and destination is
730
225k
  // 32-bits. It saves one byte per lea in code since 0x67 prefix is avoided.
731
225k
  // Don't change BasePtr since it is used later for stack adjustment.
732
225k
  unsigned MachineBasePtr = BasePtr;
733
225k
  if (Opc == X86::LEA64_32r && 
X86::GR32RegClass.contains(BasePtr)49
)
734
46
    MachineBasePtr = getX86SubSuperRegister(BasePtr, 64);
735
225k
736
225k
  // This must be part of a four operand memory reference.  Replace the
737
225k
  // FrameIndex with base register.  Add an offset to the offset.
738
225k
  MI.getOperand(FIOperandNum).ChangeToRegister(MachineBasePtr, false);
739
225k
740
225k
  if (BasePtr == StackPtr)
741
78.8k
    FIOffset += SPAdj;
742
225k
743
225k
  // The frame index format for stackmaps and patchpoints is different from the
744
225k
  // X86 format. It only has a FI and an offset.
745
225k
  if (Opc == TargetOpcode::STACKMAP || 
Opc == TargetOpcode::PATCHPOINT225k
) {
746
65
    assert(BasePtr == FramePtr && "Expected the FP as base register");
747
65
    int64_t Offset = MI.getOperand(FIOperandNum + 1).getImm() + FIOffset;
748
65
    MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
749
65
    return;
750
65
  }
751
225k
752
225k
  if (MI.getOperand(FIOperandNum+3).isImm()) {
753
225k
    // Offset is a 32-bit integer.
754
225k
    int Imm = (int)(MI.getOperand(FIOperandNum + 3).getImm());
755
225k
    int Offset = FIOffset + Imm;
756
225k
    assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
757
225k
           "Requesting 64-bit offset in 32-bit immediate!");
758
225k
    if (Offset != 0 || 
!tryOptimizeLEAtoMOV(II)7.07k
)
759
224k
      MI.getOperand(FIOperandNum + 3).ChangeToImmediate(Offset);
760
225k
  } else {
761
2
    // Offset is symbolic. This is extremely rare.
762
2
    uint64_t Offset = FIOffset +
763
2
      (uint64_t)MI.getOperand(FIOperandNum+3).getOffset();
764
2
    MI.getOperand(FIOperandNum + 3).setOffset(Offset);
765
2
  }
766
225k
}
767
768
563k
Register X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
769
563k
  const X86FrameLowering *TFI = getFrameLowering(MF);
770
563k
  return TFI->hasFP(MF) ? 
FramePtr264k
:
StackPtr298k
;
771
563k
}
772
773
unsigned
774
5.35k
X86RegisterInfo::getPtrSizedFrameRegister(const MachineFunction &MF) const {
775
5.35k
  const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
776
5.35k
  unsigned FrameReg = getFrameRegister(MF);
777
5.35k
  if (Subtarget.isTarget64BitILP32())
778
8
    FrameReg = getX86SubSuperRegister(FrameReg, 32);
779
5.35k
  return FrameReg;
780
5.35k
}
781
782
unsigned
783
1
X86RegisterInfo::getPtrSizedStackRegister(const MachineFunction &MF) const {
784
1
  const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
785
1
  unsigned StackReg = getStackRegister();
786
1
  if (Subtarget.isTarget64BitILP32())
787
0
    StackReg = getX86SubSuperRegister(StackReg, 32);
788
1
  return StackReg;
789
1
}