Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/X86/X86Subtarget.h
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//===-- X86Subtarget.h - Define Subtarget for the X86 ----------*- C++ -*--===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
8
//
9
// This file declares the X86 specific subclass of TargetSubtargetInfo.
10
//
11
//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_X86_X86SUBTARGET_H
14
#define LLVM_LIB_TARGET_X86_X86SUBTARGET_H
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16
#include "X86FrameLowering.h"
17
#include "X86ISelLowering.h"
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#include "X86InstrInfo.h"
19
#include "X86SelectionDAGInfo.h"
20
#include "llvm/ADT/StringRef.h"
21
#include "llvm/ADT/Triple.h"
22
#include "llvm/CodeGen/GlobalISel/CallLowering.h"
23
#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
24
#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
25
#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
26
#include "llvm/CodeGen/TargetSubtargetInfo.h"
27
#include "llvm/IR/CallingConv.h"
28
#include "llvm/Target/TargetMachine.h"
29
#include <climits>
30
#include <memory>
31
32
#define GET_SUBTARGETINFO_HEADER
33
#include "X86GenSubtargetInfo.inc"
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namespace llvm {
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37
class GlobalValue;
38
39
/// The X86 backend supports a number of different styles of PIC.
40
///
41
namespace PICStyles {
42
43
enum Style {
44
  StubPIC,          // Used on i386-darwin in pic mode.
45
  GOT,              // Used on 32 bit elf on when in pic mode.
46
  RIPRel,           // Used on X86-64 when in pic mode.
47
  None              // Set when not in pic mode.
48
};
49
50
} // end namespace PICStyles
51
52
class X86Subtarget final : public X86GenSubtargetInfo {
53
public:
54
  // NOTE: Do not add anything new to this list. Coarse, CPU name based flags
55
  // are not a good idea. We should be migrating away from these.
56
  enum X86ProcFamilyEnum {
57
    Others,
58
    IntelAtom,
59
    IntelSLM,
60
    IntelGLM,
61
    IntelGLP,
62
    IntelTRM
63
  };
64
65
protected:
66
  enum X86SSEEnum {
67
    NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
68
  };
69
70
  enum X863DNowEnum {
71
    NoThreeDNow, MMX, ThreeDNow, ThreeDNowA
72
  };
73
74
  /// X86 processor family: Intel Atom, and others
75
  X86ProcFamilyEnum X86ProcFamily = Others;
76
77
  /// Which PIC style to use
78
  PICStyles::Style PICStyle;
79
80
  const TargetMachine &TM;
81
82
  /// SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported.
83
  X86SSEEnum X86SSELevel = NoSSE;
84
85
  /// MMX, 3DNow, 3DNow Athlon, or none supported.
86
  X863DNowEnum X863DNowLevel = NoThreeDNow;
87
88
  /// True if the processor supports X87 instructions.
89
  bool HasX87 = false;
90
91
  /// True if the processor supports CMPXCHG8B.
92
  bool HasCmpxchg8b = false;
93
94
  /// True if this processor has NOPL instruction
95
  /// (generally pentium pro+).
96
  bool HasNOPL = false;
97
98
  /// True if this processor has conditional move instructions
99
  /// (generally pentium pro+).
100
  bool HasCMov = false;
101
102
  /// True if the processor supports X86-64 instructions.
103
  bool HasX86_64 = false;
104
105
  /// True if the processor supports POPCNT.
106
  bool HasPOPCNT = false;
107
108
  /// True if the processor supports SSE4A instructions.
109
  bool HasSSE4A = false;
110
111
  /// Target has AES instructions
112
  bool HasAES = false;
113
  bool HasVAES = false;
114
115
  /// Target has FXSAVE/FXRESTOR instructions
116
  bool HasFXSR = false;
117
118
  /// Target has XSAVE instructions
119
  bool HasXSAVE = false;
120
121
  /// Target has XSAVEOPT instructions
122
  bool HasXSAVEOPT = false;
123
124
  /// Target has XSAVEC instructions
125
  bool HasXSAVEC = false;
126
127
  /// Target has XSAVES instructions
128
  bool HasXSAVES = false;
129
130
  /// Target has carry-less multiplication
131
  bool HasPCLMUL = false;
132
  bool HasVPCLMULQDQ = false;
133
134
  /// Target has Galois Field Arithmetic instructions
135
  bool HasGFNI = false;
136
137
  /// Target has 3-operand fused multiply-add
138
  bool HasFMA = false;
139
140
  /// Target has 4-operand fused multiply-add
141
  bool HasFMA4 = false;
142
143
  /// Target has XOP instructions
144
  bool HasXOP = false;
145
146
  /// Target has TBM instructions.
147
  bool HasTBM = false;
148
149
  /// Target has LWP instructions
150
  bool HasLWP = false;
151
152
  /// True if the processor has the MOVBE instruction.
153
  bool HasMOVBE = false;
154
155
  /// True if the processor has the RDRAND instruction.
156
  bool HasRDRAND = false;
157
158
  /// Processor has 16-bit floating point conversion instructions.
159
  bool HasF16C = false;
160
161
  /// Processor has FS/GS base insturctions.
162
  bool HasFSGSBase = false;
163
164
  /// Processor has LZCNT instruction.
165
  bool HasLZCNT = false;
166
167
  /// Processor has BMI1 instructions.
168
  bool HasBMI = false;
169
170
  /// Processor has BMI2 instructions.
171
  bool HasBMI2 = false;
172
173
  /// Processor has VBMI instructions.
174
  bool HasVBMI = false;
175
176
  /// Processor has VBMI2 instructions.
177
  bool HasVBMI2 = false;
178
179
  /// Processor has Integer Fused Multiply Add
180
  bool HasIFMA = false;
181
182
  /// Processor has RTM instructions.
183
  bool HasRTM = false;
184
185
  /// Processor has ADX instructions.
186
  bool HasADX = false;
187
188
  /// Processor has SHA instructions.
189
  bool HasSHA = false;
190
191
  /// Processor has PRFCHW instructions.
192
  bool HasPRFCHW = false;
193
194
  /// Processor has RDSEED instructions.
195
  bool HasRDSEED = false;
196
197
  /// Processor has LAHF/SAHF instructions.
198
  bool HasLAHFSAHF = false;
199
200
  /// Processor has MONITORX/MWAITX instructions.
201
  bool HasMWAITX = false;
202
203
  /// Processor has Cache Line Zero instruction
204
  bool HasCLZERO = false;
205
206
  /// Processor has Cache Line Demote instruction
207
  bool HasCLDEMOTE = false;
208
209
  /// Processor has MOVDIRI instruction (direct store integer).
210
  bool HasMOVDIRI = false;
211
212
  /// Processor has MOVDIR64B instruction (direct store 64 bytes).
213
  bool HasMOVDIR64B = false;
214
215
  /// Processor has ptwrite instruction.
216
  bool HasPTWRITE = false;
217
218
  /// Processor has Prefetch with intent to Write instruction
219
  bool HasPREFETCHWT1 = false;
220
221
  /// True if SHLD instructions are slow.
222
  bool IsSHLDSlow = false;
223
224
  /// True if the PMULLD instruction is slow compared to PMULLW/PMULHW and
225
  //  PMULUDQ.
226
  bool IsPMULLDSlow = false;
227
228
  /// True if the PMADDWD instruction is slow compared to PMULLD.
229
  bool IsPMADDWDSlow = false;
230
231
  /// True if unaligned memory accesses of 16-bytes are slow.
232
  bool IsUAMem16Slow = false;
233
234
  /// True if unaligned memory accesses of 32-bytes are slow.
235
  bool IsUAMem32Slow = false;
236
237
  /// True if SSE operations can have unaligned memory operands.
238
  /// This may require setting a configuration bit in the processor.
239
  bool HasSSEUnalignedMem = false;
240
241
  /// True if this processor has the CMPXCHG16B instruction;
242
  /// this is true for most x86-64 chips, but not the first AMD chips.
243
  bool HasCmpxchg16b = false;
244
245
  /// True if the LEA instruction should be used for adjusting
246
  /// the stack pointer. This is an optimization for Intel Atom processors.
247
  bool UseLeaForSP = false;
248
249
  /// True if POPCNT instruction has a false dependency on the destination register.
250
  bool HasPOPCNTFalseDeps = false;
251
252
  /// True if LZCNT/TZCNT instructions have a false dependency on the destination register.
253
  bool HasLZCNTFalseDeps = false;
254
255
  /// True if its preferable to combine to a single shuffle using a variable
256
  /// mask over multiple fixed shuffles.
257
  bool HasFastVariableShuffle = false;
258
259
  /// True if there is no performance penalty to writing only the lower parts
260
  /// of a YMM or ZMM register without clearing the upper part.
261
  bool HasFastPartialYMMorZMMWrite = false;
262
263
  /// True if there is no performance penalty for writing NOPs with up to
264
  /// 11 bytes.
265
  bool HasFast11ByteNOP = false;
266
267
  /// True if there is no performance penalty for writing NOPs with up to
268
  /// 15 bytes.
269
  bool HasFast15ByteNOP = false;
270
271
  /// True if gather is reasonably fast. This is true for Skylake client and
272
  /// all AVX-512 CPUs.
273
  bool HasFastGather = false;
274
275
  /// True if hardware SQRTSS instruction is at least as fast (latency) as
276
  /// RSQRTSS followed by a Newton-Raphson iteration.
277
  bool HasFastScalarFSQRT = false;
278
279
  /// True if hardware SQRTPS/VSQRTPS instructions are at least as fast
280
  /// (throughput) as RSQRTPS/VRSQRTPS followed by a Newton-Raphson iteration.
281
  bool HasFastVectorFSQRT = false;
282
283
  /// True if 8-bit divisions are significantly faster than
284
  /// 32-bit divisions and should be used when possible.
285
  bool HasSlowDivide32 = false;
286
287
  /// True if 32-bit divides are significantly faster than
288
  /// 64-bit divisions and should be used when possible.
289
  bool HasSlowDivide64 = false;
290
291
  /// True if LZCNT instruction is fast.
292
  bool HasFastLZCNT = false;
293
294
  /// True if SHLD based rotate is fast.
295
  bool HasFastSHLDRotate = false;
296
297
  /// True if the processor supports macrofusion.
298
  bool HasMacroFusion = false;
299
300
  /// True if the processor supports branch fusion.
301
  bool HasBranchFusion = false;
302
303
  /// True if the processor has enhanced REP MOVSB/STOSB.
304
  bool HasERMSB = false;
305
306
  /// True if the short functions should be padded to prevent
307
  /// a stall when returning too early.
308
  bool PadShortFunctions = false;
309
310
  /// True if two memory operand instructions should use a temporary register
311
  /// instead.
312
  bool SlowTwoMemOps = false;
313
314
  /// True if the LEA instruction inputs have to be ready at address generation
315
  /// (AG) time.
316
  bool LEAUsesAG = false;
317
318
  /// True if the LEA instruction with certain arguments is slow
319
  bool SlowLEA = false;
320
321
  /// True if the LEA instruction has all three source operands: base, index,
322
  /// and offset or if the LEA instruction uses base and index registers where
323
  /// the base is EBP, RBP,or R13
324
  bool Slow3OpsLEA = false;
325
326
  /// True if INC and DEC instructions are slow when writing to flags
327
  bool SlowIncDec = false;
328
329
  /// Processor has AVX-512 PreFetch Instructions
330
  bool HasPFI = false;
331
332
  /// Processor has AVX-512 Exponential and Reciprocal Instructions
333
  bool HasERI = false;
334
335
  /// Processor has AVX-512 Conflict Detection Instructions
336
  bool HasCDI = false;
337
338
  /// Processor has AVX-512 population count Instructions
339
  bool HasVPOPCNTDQ = false;
340
341
  /// Processor has AVX-512 Doubleword and Quadword instructions
342
  bool HasDQI = false;
343
344
  /// Processor has AVX-512 Byte and Word instructions
345
  bool HasBWI = false;
346
347
  /// Processor has AVX-512 Vector Length eXtenstions
348
  bool HasVLX = false;
349
350
  /// Processor has PKU extenstions
351
  bool HasPKU = false;
352
353
  /// Processor has AVX-512 Vector Neural Network Instructions
354
  bool HasVNNI = false;
355
356
  /// Processor has AVX-512 bfloat16 floating-point extensions
357
  bool HasBF16 = false;
358
359
  /// Processor supports ENQCMD instructions
360
  bool HasENQCMD = false;
361
362
  /// Processor has AVX-512 Bit Algorithms instructions
363
  bool HasBITALG = false;
364
365
  /// Processor has AVX-512 vp2intersect instructions
366
  bool HasVP2INTERSECT = false;
367
368
  /// Processor supports MPX - Memory Protection Extensions
369
  bool HasMPX = false;
370
371
  /// Processor supports CET SHSTK - Control-Flow Enforcement Technology
372
  /// using Shadow Stack
373
  bool HasSHSTK = false;
374
375
  /// Processor supports Invalidate Process-Context Identifier
376
  bool HasINVPCID = false;
377
378
  /// Processor has Software Guard Extensions
379
  bool HasSGX = false;
380
381
  /// Processor supports Flush Cache Line instruction
382
  bool HasCLFLUSHOPT = false;
383
384
  /// Processor supports Cache Line Write Back instruction
385
  bool HasCLWB = false;
386
387
  /// Processor supports Write Back No Invalidate instruction
388
  bool HasWBNOINVD = false;
389
390
  /// Processor support RDPID instruction
391
  bool HasRDPID = false;
392
393
  /// Processor supports WaitPKG instructions
394
  bool HasWAITPKG = false;
395
396
  /// Processor supports PCONFIG instruction
397
  bool HasPCONFIG = false;
398
399
  /// Processor has a single uop BEXTR implementation.
400
  bool HasFastBEXTR = false;
401
402
  /// Try harder to combine to horizontal vector ops if they are fast.
403
  bool HasFastHorizontalOps = false;
404
405
  /// Prefer a left/right scalar logical shifts pair over a shift+and pair.
406
  bool HasFastScalarShiftMasks = false;
407
408
  /// Prefer a left/right vector logical shifts pair over a shift+and pair.
409
  bool HasFastVectorShiftMasks = false;
410
411
  /// Use a retpoline thunk rather than indirect calls to block speculative
412
  /// execution.
413
  bool UseRetpolineIndirectCalls = false;
414
415
  /// Use a retpoline thunk or remove any indirect branch to block speculative
416
  /// execution.
417
  bool UseRetpolineIndirectBranches = false;
418
419
  /// Deprecated flag, query `UseRetpolineIndirectCalls` and
420
  /// `UseRetpolineIndirectBranches` instead.
421
  bool DeprecatedUseRetpoline = false;
422
423
  /// When using a retpoline thunk, call an externally provided thunk rather
424
  /// than emitting one inside the compiler.
425
  bool UseRetpolineExternalThunk = false;
426
427
  /// Use software floating point for code generation.
428
  bool UseSoftFloat = false;
429
430
  /// The minimum alignment known to hold of the stack frame on
431
  /// entry to the function and which must be maintained by every function.
432
  unsigned stackAlignment = 4;
433
434
  /// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops.
435
  ///
436
  // FIXME: this is a known good value for Yonah. How about others?
437
  unsigned MaxInlineSizeThreshold = 128;
438
439
  /// Indicates target prefers 256 bit instructions.
440
  bool Prefer256Bit = false;
441
442
  /// Threeway branch is profitable in this subtarget.
443
  bool ThreewayBranchProfitable = false;
444
445
  /// What processor and OS we're targeting.
446
  Triple TargetTriple;
447
448
  /// GlobalISel related APIs.
449
  std::unique_ptr<CallLowering> CallLoweringInfo;
450
  std::unique_ptr<LegalizerInfo> Legalizer;
451
  std::unique_ptr<RegisterBankInfo> RegBankInfo;
452
  std::unique_ptr<InstructionSelector> InstSelector;
453
454
private:
455
  /// Override the stack alignment.
456
  unsigned StackAlignOverride;
457
458
  /// Preferred vector width from function attribute.
459
  unsigned PreferVectorWidthOverride;
460
461
  /// Resolved preferred vector width from function attribute and subtarget
462
  /// features.
463
  unsigned PreferVectorWidth = UINT32_MAX;
464
465
  /// Required vector width from function attribute.
466
  unsigned RequiredVectorWidth;
467
468
  /// True if compiling for 64-bit, false for 16-bit or 32-bit.
469
  bool In64BitMode;
470
471
  /// True if compiling for 32-bit, false for 16-bit or 64-bit.
472
  bool In32BitMode;
473
474
  /// True if compiling for 16-bit, false for 32-bit or 64-bit.
475
  bool In16BitMode;
476
477
  /// Contains the Overhead of gather\scatter instructions
478
  int GatherOverhead = 1024;
479
  int ScatterOverhead = 1024;
480
481
  X86SelectionDAGInfo TSInfo;
482
  // Ordering here is important. X86InstrInfo initializes X86RegisterInfo which
483
  // X86TargetLowering needs.
484
  X86InstrInfo InstrInfo;
485
  X86TargetLowering TLInfo;
486
  X86FrameLowering FrameLowering;
487
488
public:
489
  /// This constructor initializes the data members to match that
490
  /// of the specified triple.
491
  ///
492
  X86Subtarget(const Triple &TT, StringRef CPU, StringRef FS,
493
               const X86TargetMachine &TM, unsigned StackAlignOverride,
494
               unsigned PreferVectorWidthOverride,
495
               unsigned RequiredVectorWidth);
496
497
11.7M
  const X86TargetLowering *getTargetLowering() const override {
498
11.7M
    return &TLInfo;
499
11.7M
  }
500
501
60.9M
  const X86InstrInfo *getInstrInfo() const override { return &InstrInfo; }
502
503
10.5M
  const X86FrameLowering *getFrameLowering() const override {
504
10.5M
    return &FrameLowering;
505
10.5M
  }
506
507
139k
  const X86SelectionDAGInfo *getSelectionDAGInfo() const override {
508
139k
    return &TSInfo;
509
139k
  }
510
511
45.0M
  const X86RegisterInfo *getRegisterInfo() const override {
512
45.0M
    return &getInstrInfo()->getRegisterInfo();
513
45.0M
  }
514
515
  /// Returns the minimum alignment known to hold of the
516
  /// stack frame on entry to the function and which must be maintained by every
517
  /// function for this subtarget.
518
15.2k
  unsigned getStackAlignment() const { return stackAlignment; }
519
520
  /// Returns the maximum memset / memcpy size
521
  /// that still makes it profitable to inline the call.
522
289
  unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; }
523
524
  /// ParseSubtargetFeatures - Parses features string setting specified
525
  /// subtarget options.  Definition of function is auto generated by tblgen.
526
  void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
527
528
  /// Methods used by Global ISel
529
  const CallLowering *getCallLowering() const override;
530
  const InstructionSelector *getInstructionSelector() const override;
531
  const LegalizerInfo *getLegalizerInfo() const override;
532
  const RegisterBankInfo *getRegBankInfo() const override;
533
534
private:
535
  /// Initialize the full set of dependencies so we can use an initializer
536
  /// list for X86Subtarget.
537
  X86Subtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
538
  void initSubtargetFeatures(StringRef CPU, StringRef FS);
539
540
public:
541
  /// Is this x86_64? (disregarding specific ABI / programming model)
542
9.37M
  bool is64Bit() const {
543
9.37M
    return In64BitMode;
544
9.37M
  }
545
546
16.4k
  bool is32Bit() const {
547
16.4k
    return In32BitMode;
548
16.4k
  }
549
550
0
  bool is16Bit() const {
551
0
    return In16BitMode;
552
0
  }
553
554
  /// Is this x86_64 with the ILP32 programming model (x32 ABI)?
555
288k
  bool isTarget64BitILP32() const {
556
288k
    return In64BitMode && 
(232k
TargetTriple.getEnvironment() == Triple::GNUX32232k
||
557
232k
                           
TargetTriple.isOSNaCl()231k
);
558
288k
  }
559
560
  /// Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
561
1.88M
  bool isTarget64BitLP64() const {
562
1.88M
    return In64BitMode && 
(1.42M
TargetTriple.getEnvironment() != Triple::GNUX321.42M
&&
563
1.42M
                           
!TargetTriple.isOSNaCl()1.41M
);
564
1.88M
  }
565
566
0
  PICStyles::Style getPICStyle() const { return PICStyle; }
567
15.2k
  void setPICStyle(PICStyles::Style Style)  { PICStyle = Style; }
568
569
28.8k
  bool hasX87() const { return HasX87; }
570
31.3k
  bool hasCmpxchg8b() const { return HasCmpxchg8b; }
571
0
  bool hasNOPL() const { return HasNOPL; }
572
  // SSE codegen depends on cmovs, and all SSE1+ processors support them.
573
  // All 64-bit processors support cmov.
574
510k
  bool hasCMov() const { return HasCMov || 
X86SSELevel >= SSE1170k
||
is64Bit()22.9k
; }
575
3.15M
  bool hasSSE1() const { return X86SSELevel >= SSE1; }
576
5.08M
  bool hasSSE2() const { return X86SSELevel >= SSE2; }
577
457k
  bool hasSSE3() const { return X86SSELevel >= SSE3; }
578
288k
  bool hasSSSE3() const { return X86SSELevel >= SSSE3; }
579
873k
  bool hasSSE41() const { return X86SSELevel >= SSE41; }
580
197k
  bool hasSSE42() const { return X86SSELevel >= SSE42; }
581
4.26M
  bool hasAVX() const { return X86SSELevel >= AVX; }
582
1.68M
  bool hasAVX2() const { return X86SSELevel >= AVX2; }
583
6.61M
  bool hasAVX512() const { return X86SSELevel >= AVX512F; }
584
107k
  bool hasInt256() const { return hasAVX2(); }
585
137k
  bool hasSSE4A() const { return HasSSE4A; }
586
45.9k
  bool hasMMX() const { return X863DNowLevel >= MMX; }
587
17.0k
  bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
588
0
  bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
589
44.6k
  bool hasPOPCNT() const { return HasPOPCNT; }
590
15.3k
  bool hasAES() const { return HasAES; }
591
16.0k
  bool hasVAES() const { return HasVAES; }
592
15.2k
  bool hasFXSR() const { return HasFXSR; }
593
15.2k
  bool hasXSAVE() const { return HasXSAVE; }
594
15.2k
  bool hasXSAVEOPT() const { return HasXSAVEOPT; }
595
15.2k
  bool hasXSAVEC() const { return HasXSAVEC; }
596
15.2k
  bool hasXSAVES() const { return HasXSAVES; }
597
15.3k
  bool hasPCLMUL() const { return HasPCLMUL; }
598
16.0k
  bool hasVPCLMULQDQ() const { return HasVPCLMULQDQ; }
599
15.3k
  bool hasGFNI() const { return HasGFNI; }
600
  // Prefer FMA4 to FMA - its better for commutation/memory folding and
601
  // has equal or better performance on all supported targets.
602
142k
  bool hasFMA() const { return HasFMA; }
603
114k
  bool hasFMA4() const { return HasFMA4; }
604
125k
  bool hasAnyFMA() const { return hasFMA() || 
hasFMA4()81.6k
; }
605
382k
  bool hasXOP() const { return HasXOP; }
606
101k
  bool hasTBM() const { return HasTBM; }
607
15.3k
  bool hasLWP() const { return HasLWP; }
608
30.8k
  bool hasMOVBE() const { return HasMOVBE; }
609
15.2k
  bool hasRDRAND() const { return HasRDRAND; }
610
31.6k
  bool hasF16C() const { return HasF16C; }
611
15.2k
  bool hasFSGSBase() const { return HasFSGSBase; }
612
35.6k
  bool hasLZCNT() const { return HasLZCNT; }
613
186k
  bool hasBMI() const { return HasBMI; }
614
211k
  bool hasBMI2() const { return HasBMI2; }
615
136k
  bool hasVBMI() const { return HasVBMI; }
616
19.7k
  bool hasVBMI2() const { return HasVBMI2; }
617
15.5k
  bool hasIFMA() const { return HasIFMA; }
618
15.2k
  bool hasRTM() const { return HasRTM; }
619
0
  bool hasADX() const { return HasADX; }
620
15.2k
  bool hasSHA() const { return HasSHA; }
621
20.2k
  bool hasPRFCHW() const { return HasPRFCHW || 
HasPREFETCHWT119.6k
; }
622
20.2k
  bool hasPREFETCHWT1() const { return HasPREFETCHWT1; }
623
45.8k
  bool hasSSEPrefetch() const {
624
45.8k
    // We implicitly enable these when we have a write prefix supporting cache
625
45.8k
    // level OR if we have prfchw, but don't already have a read prefetch from
626
45.8k
    // 3dnow.
627
45.8k
    return hasSSE1() || 
(4.97k
hasPRFCHW()4.97k
&&
!has3DNow()32
) ||
hasPREFETCHWT1()4.95k
;
628
45.8k
  }
629
15.2k
  bool hasRDSEED() const { return HasRDSEED; }
630
15.6k
  bool hasLAHFSAHF() const { return HasLAHFSAHF; }
631
15.2k
  bool hasMWAITX() const { return HasMWAITX; }
632
2
  bool hasCLZERO() const { return HasCLZERO; }
633
15.2k
  bool hasCLDEMOTE() const { return HasCLDEMOTE; }
634
15.2k
  bool hasMOVDIRI() const { return HasMOVDIRI; }
635
15.2k
  bool hasMOVDIR64B() const { return HasMOVDIR64B; }
636
15.2k
  bool hasPTWRITE() const { return HasPTWRITE; }
637
23.0k
  bool isSHLDSlow() const { return IsSHLDSlow; }
638
4.13k
  bool isPMULLDSlow() const { return IsPMULLDSlow; }
639
38.2k
  bool isPMADDWDSlow() const { return IsPMADDWDSlow; }
640
52.4k
  bool isUnalignedMem16Slow() const { return IsUAMem16Slow; }
641
26.4k
  bool isUnalignedMem32Slow() const { return IsUAMem32Slow; }
642
130
  int getGatherOverhead() const { return GatherOverhead; }
643
70
  int getScatterOverhead() const { return ScatterOverhead; }
644
21.1k
  bool hasSSEUnalignedMem() const { return HasSSEUnalignedMem; }
645
30.8k
  bool hasCmpxchg16b() const { return HasCmpxchg16b && 
is64Bit()8.84k
; }
646
195k
  bool useLeaForSP() const { return UseLeaForSP; }
647
141
  bool hasPOPCNTFalseDeps() const { return HasPOPCNTFalseDeps; }
648
462
  bool hasLZCNTFalseDeps() const { return HasLZCNTFalseDeps; }
649
71.2k
  bool hasFastVariableShuffle() const {
650
71.2k
    return HasFastVariableShuffle;
651
71.2k
  }
652
77.2k
  bool hasFastPartialYMMorZMMWrite() const {
653
77.2k
    return HasFastPartialYMMorZMMWrite;
654
77.2k
  }
655
2.47k
  bool hasFastGather() const { return HasFastGather; }
656
61
  bool hasFastScalarFSQRT() const { return HasFastScalarFSQRT; }
657
72
  bool hasFastVectorFSQRT() const { return HasFastVectorFSQRT; }
658
32.8k
  bool hasFastLZCNT() const { return HasFastLZCNT; }
659
15.7k
  bool hasFastSHLDRotate() const { return HasFastSHLDRotate; }
660
13.1k
  bool hasFastBEXTR() const { return HasFastBEXTR; }
661
2.46k
  bool hasFastHorizontalOps() const { return HasFastHorizontalOps; }
662
3.04k
  bool hasFastScalarShiftMasks() const { return HasFastScalarShiftMasks; }
663
3.05k
  bool hasFastVectorShiftMasks() const { return HasFastVectorShiftMasks; }
664
628k
  bool hasMacroFusion() const { return HasMacroFusion; }
665
534k
  bool hasBranchFusion() const { return HasBranchFusion; }
666
268
  bool hasERMSB() const { return HasERMSB; }
667
12.5k
  bool hasSlowDivide32() const { return HasSlowDivide32; }
668
12.5k
  bool hasSlowDivide64() const { return HasSlowDivide64; }
669
133k
  bool padShortFunctions() const { return PadShortFunctions; }
670
306k
  bool slowTwoMemOps() const { return SlowTwoMemOps; }
671
135k
  bool LEAusesAG() const { return LEAUsesAG; }
672
142k
  bool slowLEA() const { return SlowLEA; }
673
135k
  bool slow3OpsLEA() const { return Slow3OpsLEA; }
674
159k
  bool slowIncDec() const { return SlowIncDec; }
675
52.3k
  bool hasCDI() const { return HasCDI; }
676
19.1k
  bool hasVPOPCNTDQ() const { return HasVPOPCNTDQ; }
677
0
  bool hasPFI() const { return HasPFI; }
678
15.2k
  bool hasERI() const { return HasERI; }
679
721k
  bool hasDQI() const { return HasDQI; }
680
821k
  bool hasBWI() const { return HasBWI; }
681
1.19M
  bool hasVLX() const { return HasVLX; }
682
0
  bool hasPKU() const { return HasPKU; }
683
15.3k
  bool hasVNNI() const { return HasVNNI; }
684
15.3k
  bool hasBF16() const { return HasBF16; }
685
15.2k
  bool hasVP2INTERSECT() const { return HasVP2INTERSECT; }
686
16.9k
  bool hasBITALG() const { return HasBITALG; }
687
0
  bool hasMPX() const { return HasMPX; }
688
0
  bool hasSHSTK() const { return HasSHSTK; }
689
15.2k
  bool hasCLFLUSHOPT() const { return HasCLFLUSHOPT; }
690
15.2k
  bool hasCLWB() const { return HasCLWB; }
691
15.2k
  bool hasWBNOINVD() const { return HasWBNOINVD; }
692
15.2k
  bool hasRDPID() const { return HasRDPID; }
693
15.2k
  bool hasWAITPKG() const { return HasWAITPKG; }
694
0
  bool hasPCONFIG() const { return HasPCONFIG; }
695
0
  bool hasSGX() const { return HasSGX; }
696
50
  bool threewayBranchProfitable() const { return ThreewayBranchProfitable; }
697
15.2k
  bool hasINVPCID() const { return HasINVPCID; }
698
15.2k
  bool hasENQCMD() const { return HasENQCMD; }
699
8.09M
  bool useRetpolineIndirectCalls() const { return UseRetpolineIndirectCalls; }
700
283k
  bool useRetpolineIndirectBranches() const {
701
283k
    return UseRetpolineIndirectBranches;
702
283k
  }
703
80
  bool useRetpolineExternalThunk() const { return UseRetpolineExternalThunk; }
704
705
311k
  unsigned getPreferVectorWidth() const { return PreferVectorWidth; }
706
0
  unsigned getRequiredVectorWidth() const { return RequiredVectorWidth; }
707
708
  // Helper functions to determine when we should allow widening to 512-bit
709
  // during codegen.
710
  // TODO: Currently we're always allowing widening on CPUs without VLX,
711
  // because for many cases we don't have a better option.
712
18.3k
  bool canExtendTo512DQ() const {
713
18.3k
    return hasAVX512() && 
(15.6k
!hasVLX()15.6k
||
getPreferVectorWidth() >= 5127.61k
);
714
18.3k
  }
715
2.03k
  bool canExtendTo512BW() const  {
716
2.03k
    return hasBWI() && 
canExtendTo512DQ()298
;
717
2.03k
  }
718
719
  // If there are no 512-bit vectors and we prefer not to use 512-bit registers,
720
  // disable them in the legalizer.
721
28.8k
  bool useAVX512Regs() const {
722
28.8k
    return hasAVX512() && 
(11.8k
canExtendTo512DQ()11.8k
||
RequiredVectorWidth > 256138
);
723
28.8k
  }
724
725
128k
  bool useBWIRegs() const {
726
128k
    return hasBWI() && 
useAVX512Regs()9.83k
;
727
128k
  }
728
729
28
  bool isXRaySupported() const override { return is64Bit(); }
730
731
0
  X86ProcFamilyEnum getProcFamily() const { return X86ProcFamily; }
732
733
  /// TODO: to be removed later and replaced with suitable properties
734
48.1k
  bool isAtom() const { return X86ProcFamily == IntelAtom; }
735
165k
  bool isSLM() const { return X86ProcFamily == IntelSLM; }
736
134k
  bool isGLM() const {
737
134k
    return X86ProcFamily == IntelGLM ||
738
134k
           
X86ProcFamily == IntelGLP132k
||
739
134k
           
X86ProcFamily == IntelTRM132k
;
740
134k
  }
741
916k
  bool useSoftFloat() const { return UseSoftFloat; }
742
743
  /// Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
744
  /// no-sse2). There isn't any reason to disable it if the target processor
745
  /// supports it.
746
15.6k
  bool hasMFence() const { return hasSSE2() || 
is64Bit()1.73k
; }
747
748
71.4k
  const Triple &getTargetTriple() const { return TargetTriple; }
749
750
230k
  bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
751
89
  bool isTargetFreeBSD() const { return TargetTriple.isOSFreeBSD(); }
752
102
  bool isTargetDragonFly() const { return TargetTriple.isOSDragonFly(); }
753
5.57k
  bool isTargetSolaris() const { return TargetTriple.isOSSolaris(); }
754
30.4k
  bool isTargetPS4() const { return TargetTriple.isPS4CPU(); }
755
756
221k
  bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
757
336k
  bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
758
4.64k
  bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
759
760
9.24k
  bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
761
5.56k
  bool isTargetKFreeBSD() const { return TargetTriple.isOSKFreeBSD(); }
762
106
  bool isTargetGlibc() const { return TargetTriple.isOSGlibc(); }
763
154
  bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
764
3.60k
  bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
765
0
  bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
766
3.24k
  bool isTargetNaCl64() const { return isTargetNaCl() && 
is64Bit()11
; }
767
277k
  bool isTargetMCU() const { return TargetTriple.isOSIAMCU(); }
768
670
  bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
769
770
18.4k
  bool isTargetWindowsMSVC() const {
771
18.4k
    return TargetTriple.isWindowsMSVCEnvironment();
772
18.4k
  }
773
774
124
  bool isTargetWindowsCoreCLR() const {
775
124
    return TargetTriple.isWindowsCoreCLREnvironment();
776
124
  }
777
778
0
  bool isTargetWindowsCygwin() const {
779
0
    return TargetTriple.isWindowsCygwinEnvironment();
780
0
  }
781
782
8.80k
  bool isTargetWindowsGNU() const {
783
8.80k
    return TargetTriple.isWindowsGNUEnvironment();
784
8.80k
  }
785
786
17.4k
  bool isTargetWindowsItanium() const {
787
17.4k
    return TargetTriple.isWindowsItaniumEnvironment();
788
17.4k
  }
789
790
134k
  bool isTargetCygMing() const { return TargetTriple.isOSCygMing(); }
791
792
1.49M
  bool isOSWindows() const { return TargetTriple.isOSWindows(); }
793
794
1.40M
  bool isTargetWin64() const { return In64BitMode && 
isOSWindows()1.29M
; }
795
796
278k
  bool isTargetWin32() const { return !In64BitMode && 
isOSWindows()57.2k
; }
797
798
291k
  bool isPICStyleGOT() const { return PICStyle == PICStyles::GOT; }
799
121k
  bool isPICStyleRIPRel() const { return PICStyle == PICStyles::RIPRel; }
800
801
53
  bool isPICStyleStubPIC() const {
802
53
    return PICStyle == PICStyles::StubPIC;
803
53
  }
804
805
180k
  bool isPositionIndependent() const { return TM.isPositionIndependent(); }
806
807
443k
  bool isCallingConvWin64(CallingConv::ID CC) const {
808
443k
    switch (CC) {
809
443k
    // On Win64, all these conventions just use the default convention.
810
443k
    case CallingConv::C:
811
442k
    case CallingConv::Fast:
812
442k
    case CallingConv::Swift:
813
442k
    case CallingConv::X86_FastCall:
814
442k
    case CallingConv::X86_StdCall:
815
442k
    case CallingConv::X86_ThisCall:
816
442k
    case CallingConv::X86_VectorCall:
817
442k
    case CallingConv::Intel_OCL_BI:
818
442k
      return isTargetWin64();
819
442k
    // This convention allows using the Win64 convention on other targets.
820
442k
    case CallingConv::Win64:
821
97
      return true;
822
442k
    // This convention allows using the SysV convention on Windows targets.
823
442k
    case CallingConv::X86_64_SysV:
824
10
      return false;
825
442k
    // Otherwise, who knows what this is.
826
442k
    default:
827
665
      return false;
828
443k
    }
829
443k
  }
830
831
  /// Classify a global variable reference for the current subtarget according
832
  /// to how we should reference it in a non-pcrel context.
833
  unsigned char classifyLocalReference(const GlobalValue *GV) const;
834
835
  unsigned char classifyGlobalReference(const GlobalValue *GV,
836
                                        const Module &M) const;
837
  unsigned char classifyGlobalReference(const GlobalValue *GV) const;
838
839
  /// Classify a global function reference for the current subtarget.
840
  unsigned char classifyGlobalFunctionReference(const GlobalValue *GV,
841
                                                const Module &M) const;
842
  unsigned char classifyGlobalFunctionReference(const GlobalValue *GV) const;
843
844
  /// Classify a blockaddress reference for the current subtarget according to
845
  /// how we should reference it in a non-pcrel context.
846
  unsigned char classifyBlockAddressReference() const;
847
848
  /// Return true if the subtarget allows calls to immediate address.
849
  bool isLegalToCallImmediateAddr() const;
850
851
  /// If we are using retpolines, we need to expand indirectbr to avoid it
852
  /// lowering to an actual indirect jump.
853
137k
  bool enableIndirectBrExpand() const override {
854
137k
    return useRetpolineIndirectBranches();
855
137k
  }
856
857
  /// Enable the MachineScheduler pass for all X86 subtargets.
858
650k
  bool enableMachineScheduler() const override { return true; }
859
860
  bool enableEarlyIfConversion() const override;
861
862
  void getPostRAMutations(std::vector<std::unique_ptr<ScheduleDAGMutation>>
863
                              &Mutations) const override;
864
865
135k
  AntiDepBreakMode getAntiDepBreakMode() const override {
866
135k
    return TargetSubtargetInfo::ANTIDEP_CRITICAL;
867
135k
  }
868
869
135k
  bool enableAdvancedRASplitCost() const override { return true; }
870
};
871
872
} // end namespace llvm
873
874
#endif // LLVM_LIB_TARGET_X86_X86SUBTARGET_H