Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/X86/X86TargetMachine.cpp
Line
Count
Source (jump to first uncovered line)
1
//===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file defines the X86 specific subclass of TargetMachine.
10
//
11
//===----------------------------------------------------------------------===//
12
13
#include "X86TargetMachine.h"
14
#include "MCTargetDesc/X86MCTargetDesc.h"
15
#include "TargetInfo/X86TargetInfo.h"
16
#include "X86.h"
17
#include "X86CallLowering.h"
18
#include "X86LegalizerInfo.h"
19
#include "X86MacroFusion.h"
20
#include "X86Subtarget.h"
21
#include "X86TargetObjectFile.h"
22
#include "X86TargetTransformInfo.h"
23
#include "llvm/ADT/Optional.h"
24
#include "llvm/ADT/STLExtras.h"
25
#include "llvm/ADT/SmallString.h"
26
#include "llvm/ADT/StringRef.h"
27
#include "llvm/ADT/Triple.h"
28
#include "llvm/Analysis/TargetTransformInfo.h"
29
#include "llvm/CodeGen/ExecutionDomainFix.h"
30
#include "llvm/CodeGen/GlobalISel/CallLowering.h"
31
#include "llvm/CodeGen/GlobalISel/IRTranslator.h"
32
#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
33
#include "llvm/CodeGen/GlobalISel/Legalizer.h"
34
#include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
35
#include "llvm/CodeGen/MachineScheduler.h"
36
#include "llvm/CodeGen/Passes.h"
37
#include "llvm/CodeGen/TargetPassConfig.h"
38
#include "llvm/IR/Attributes.h"
39
#include "llvm/IR/DataLayout.h"
40
#include "llvm/IR/Function.h"
41
#include "llvm/MC/MCAsmInfo.h"
42
#include "llvm/Pass.h"
43
#include "llvm/Support/CodeGen.h"
44
#include "llvm/Support/CommandLine.h"
45
#include "llvm/Support/ErrorHandling.h"
46
#include "llvm/Support/TargetRegistry.h"
47
#include "llvm/Target/TargetLoweringObjectFile.h"
48
#include "llvm/Target/TargetOptions.h"
49
#include <memory>
50
#include <string>
51
52
using namespace llvm;
53
54
static cl::opt<bool> EnableMachineCombinerPass("x86-machine-combiner",
55
                               cl::desc("Enable the machine combiner pass"),
56
                               cl::init(true), cl::Hidden);
57
58
static cl::opt<bool> EnableCondBrFoldingPass("x86-condbr-folding",
59
                               cl::desc("Enable the conditional branch "
60
                                        "folding pass"),
61
                               cl::init(false), cl::Hidden);
62
63
139k
extern "C" void LLVMInitializeX86Target() {
64
139k
  // Register the target.
65
139k
  RegisterTargetMachine<X86TargetMachine> X(getTheX86_32Target());
66
139k
  RegisterTargetMachine<X86TargetMachine> Y(getTheX86_64Target());
67
139k
68
139k
  PassRegistry &PR = *PassRegistry::getPassRegistry();
69
139k
  initializeGlobalISel(PR);
70
139k
  initializeWinEHStatePassPass(PR);
71
139k
  initializeFixupBWInstPassPass(PR);
72
139k
  initializeEvexToVexInstPassPass(PR);
73
139k
  initializeFixupLEAPassPass(PR);
74
139k
  initializeFPSPass(PR);
75
139k
  initializeX86CallFrameOptimizationPass(PR);
76
139k
  initializeX86CmovConverterPassPass(PR);
77
139k
  initializeX86ExpandPseudoPass(PR);
78
139k
  initializeX86ExecutionDomainFixPass(PR);
79
139k
  initializeX86DomainReassignmentPass(PR);
80
139k
  initializeX86AvoidSFBPassPass(PR);
81
139k
  initializeX86SpeculativeLoadHardeningPassPass(PR);
82
139k
  initializeX86FlagsCopyLoweringPassPass(PR);
83
139k
  initializeX86CondBrFoldingPassPass(PR);
84
139k
}
85
86
22.9k
static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
87
22.9k
  if (TT.isOSBinFormatMachO()) {
88
9.23k
    if (TT.getArch() == Triple::x86_64)
89
8.02k
      return llvm::make_unique<X86_64MachoTargetObjectFile>();
90
1.20k
    return llvm::make_unique<TargetLoweringObjectFileMachO>();
91
1.20k
  }
92
13.6k
93
13.6k
  if (TT.isOSFreeBSD())
94
62
    return llvm::make_unique<X86FreeBSDTargetObjectFile>();
95
13.6k
  if (TT.isOSLinux() || 
TT.isOSNaCl()8.23k
||
TT.isOSIAMCU()8.21k
)
96
5.39k
    return llvm::make_unique<X86LinuxNaClTargetObjectFile>();
97
8.22k
  if (TT.isOSSolaris())
98
12
    return llvm::make_unique<X86SolarisTargetObjectFile>();
99
8.21k
  if (TT.isOSFuchsia())
100
6
    return llvm::make_unique<X86FuchsiaTargetObjectFile>();
101
8.20k
  if (TT.isOSBinFormatELF())
102
6.57k
    return llvm::make_unique<X86ELFTargetObjectFile>();
103
1.62k
  if (TT.isOSBinFormatCOFF())
104
1.61k
    return llvm::make_unique<TargetLoweringObjectFileCOFF>();
105
9
  llvm_unreachable("unknown subtarget type");
106
9
}
107
108
22.9k
static std::string computeDataLayout(const Triple &TT) {
109
22.9k
  // X86 is little endian
110
22.9k
  std::string Ret = "e";
111
22.9k
112
22.9k
  Ret += DataLayout::getManglingComponent(TT);
113
22.9k
  // X86 and x32 have 32 bit pointers.
114
22.9k
  if ((TT.isArch64Bit() &&
115
22.9k
       
(17.4k
TT.getEnvironment() == Triple::GNUX3217.4k
||
TT.isOSNaCl()17.4k
)) ||
116
22.9k
      
!TT.isArch64Bit()22.8k
)
117
5.50k
    Ret += "-p:32:32";
118
22.9k
119
22.9k
  // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
120
22.9k
  if (TT.isArch64Bit() || 
TT.isOSWindows()5.41k
||
TT.isOSNaCl()4.66k
)
121
18.2k
    Ret += "-i64:64";
122
4.65k
  else if (TT.isOSIAMCU())
123
7
    Ret += "-i64:32-f64:32";
124
4.64k
  else
125
4.64k
    Ret += "-f64:32:64";
126
22.9k
127
22.9k
  // Some ABIs align long double to 128 bits, others to 32.
128
22.9k
  if (TT.isOSNaCl() || 
TT.isOSIAMCU()22.8k
)
129
26
    ; // No f80
130
22.8k
  else if (TT.isArch64Bit() || 
TT.isOSDarwin()5.41k
)
131
18.6k
    Ret += "-f80:128";
132
4.22k
  else
133
4.22k
    Ret += "-f80:32";
134
22.9k
135
22.9k
  if (TT.isOSIAMCU())
136
7
    Ret += "-f128:32";
137
22.9k
138
22.9k
  // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
139
22.9k
  if (TT.isArch64Bit())
140
17.4k
    Ret += "-n8:16:32:64";
141
5.43k
  else
142
5.43k
    Ret += "-n8:16:32";
143
22.9k
144
22.9k
  // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
145
22.9k
  if ((!TT.isArch64Bit() && 
TT.isOSWindows()5.41k
) ||
TT.isOSIAMCU()22.1k
)
146
764
    Ret += "-a:0:32-S32";
147
22.1k
  else
148
22.1k
    Ret += "-S128";
149
22.9k
150
22.9k
  return Ret;
151
22.9k
}
152
153
static Reloc::Model getEffectiveRelocModel(const Triple &TT,
154
                                           bool JIT,
155
22.9k
                                           Optional<Reloc::Model> RM) {
156
22.9k
  bool is64Bit = TT.getArch() == Triple::x86_64;
157
22.9k
  if (!RM.hasValue()) {
158
12.8k
    // JIT codegen should use static relocations by default, since it's
159
12.8k
    // typically executed in process and not relocatable.
160
12.8k
    if (JIT)
161
258
      return Reloc::Static;
162
12.5k
163
12.5k
    // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
164
12.5k
    // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
165
12.5k
    // use static relocation model by default.
166
12.5k
    if (TT.isOSDarwin()) {
167
3.28k
      if (is64Bit)
168
2.78k
        return Reloc::PIC_;
169
507
      return Reloc::DynamicNoPIC;
170
507
    }
171
9.26k
    if (TT.isOSWindows() && 
is64Bit841
)
172
485
      return Reloc::PIC_;
173
8.77k
    return Reloc::Static;
174
8.77k
  }
175
10.1k
176
10.1k
  // ELF and X86-64 don't have a distinct DynamicNoPIC model.  DynamicNoPIC
177
10.1k
  // is defined as a model for code which may be used in static or dynamic
178
10.1k
  // executables but not necessarily a shared library. On X86-32 we just
179
10.1k
  // compile in -static mode, in x86-64 we use PIC.
180
10.1k
  if (*RM == Reloc::DynamicNoPIC) {
181
14
    if (is64Bit)
182
6
      return Reloc::PIC_;
183
8
    if (!TT.isOSDarwin())
184
2
      return Reloc::Static;
185
10.1k
  }
186
10.1k
187
10.1k
  // If we are on Darwin, disallow static relocation model in X86-64 mode, since
188
10.1k
  // the Mach-O file format doesn't support it.
189
10.1k
  if (*RM == Reloc::Static && 
TT.isOSDarwin()793
&&
is64Bit489
)
190
405
    return Reloc::PIC_;
191
9.70k
192
9.70k
  return *RM;
193
9.70k
}
194
195
static CodeModel::Model getEffectiveX86CodeModel(Optional<CodeModel::Model> CM,
196
22.9k
                                                 bool JIT, bool Is64Bit) {
197
22.9k
  if (CM) {
198
79
    if (*CM == CodeModel::Tiny)
199
1
      report_fatal_error("Target does not support the tiny CodeModel", false);
200
78
    return *CM;
201
78
  }
202
22.8k
  if (JIT)
203
258
    return Is64Bit ? CodeModel::Large : 
CodeModel::Small0
;
204
22.5k
  return CodeModel::Small;
205
22.5k
}
206
207
/// Create an X86 target.
208
///
209
X86TargetMachine::X86TargetMachine(const Target &T, const Triple &TT,
210
                                   StringRef CPU, StringRef FS,
211
                                   const TargetOptions &Options,
212
                                   Optional<Reloc::Model> RM,
213
                                   Optional<CodeModel::Model> CM,
214
                                   CodeGenOpt::Level OL, bool JIT)
215
    : LLVMTargetMachine(
216
          T, computeDataLayout(TT), TT, CPU, FS, Options,
217
          getEffectiveRelocModel(TT, JIT, RM),
218
          getEffectiveX86CodeModel(CM, JIT, TT.getArch() == Triple::x86_64),
219
          OL),
220
22.9k
      TLOF(createTLOF(getTargetTriple())) {
221
22.9k
  // Windows stack unwinder gets confused when execution flow "falls through"
222
22.9k
  // after a call to 'noreturn' function.
223
22.9k
  // To prevent that, we emit a trap for 'unreachable' IR instructions.
224
22.9k
  // (which on X86, happens to be the 'ud2' instruction)
225
22.9k
  // On PS4, the "return address" of a 'noreturn' call must still be within
226
22.9k
  // the calling function, and TrapUnreachable is an easy way to get that.
227
22.9k
  // The check here for 64-bit windows is a bit icky, but as we're unlikely
228
22.9k
  // to ever want to mix 32 and 64-bit windows code in a single module
229
22.9k
  // this should be fine.
230
22.9k
  if ((TT.isOSWindows() && 
TT.getArch() == Triple::x86_641.62k
) ||
TT.isPS4()22.0k
||
231
22.9k
      
TT.isOSBinFormatMachO()21.9k
) {
232
10.1k
    this->Options.TrapUnreachable = true;
233
10.1k
    this->Options.NoTrapAfterNoreturn = TT.isOSBinFormatMachO();
234
10.1k
  }
235
22.9k
236
22.9k
  // Outlining is available for x86-64.
237
22.9k
  if (TT.getArch() == Triple::x86_64)
238
17.4k
    setMachineOutliner(true);
239
22.9k
240
22.9k
  initAsmInfo();
241
22.9k
}
242
243
19.8k
X86TargetMachine::~X86TargetMachine() = default;
244
245
const X86Subtarget *
246
4.12M
X86TargetMachine::getSubtargetImpl(const Function &F) const {
247
4.12M
  Attribute CPUAttr = F.getFnAttribute("target-cpu");
248
4.12M
  Attribute FSAttr = F.getFnAttribute("target-features");
249
4.12M
250
4.12M
  StringRef CPU = !CPUAttr.hasAttribute(Attribute::None)
251
4.12M
                      ? 
CPUAttr.getValueAsString()2.40M
252
4.12M
                      : 
(StringRef)TargetCPU1.72M
;
253
4.12M
  StringRef FS = !FSAttr.hasAttribute(Attribute::None)
254
4.12M
                     ? 
FSAttr.getValueAsString()3.72M
255
4.12M
                     : 
(StringRef)TargetFS394k
;
256
4.12M
257
4.12M
  SmallString<512> Key;
258
4.12M
  Key.reserve(CPU.size() + FS.size());
259
4.12M
  Key += CPU;
260
4.12M
  Key += FS;
261
4.12M
262
4.12M
  // FIXME: This is related to the code below to reset the target options,
263
4.12M
  // we need to know whether or not the soft float flag is set on the
264
4.12M
  // function before we can generate a subtarget. We also need to use
265
4.12M
  // it as a key for the subtarget since that can be the only difference
266
4.12M
  // between two functions.
267
4.12M
  bool SoftFloat =
268
4.12M
      F.getFnAttribute("use-soft-float").getValueAsString() == "true";
269
4.12M
  // If the soft float attribute is set on the function turn on the soft float
270
4.12M
  // subtarget feature.
271
4.12M
  if (SoftFloat)
272
1.05k
    Key += FS.empty() ? "+soft-float" : 
",+soft-float"0
;
273
4.12M
274
4.12M
  // Keep track of the key width after all features are added so we can extract
275
4.12M
  // the feature string out later.
276
4.12M
  unsigned CPUFSWidth = Key.size();
277
4.12M
278
4.12M
  // Extract prefer-vector-width attribute.
279
4.12M
  unsigned PreferVectorWidthOverride = 0;
280
4.12M
  if (F.hasFnAttribute("prefer-vector-width")) {
281
338
    StringRef Val = F.getFnAttribute("prefer-vector-width").getValueAsString();
282
338
    unsigned Width;
283
338
    if (!Val.getAsInteger(0, Width)) {
284
338
      Key += ",prefer-vector-width=";
285
338
      Key += Val;
286
338
      PreferVectorWidthOverride = Width;
287
338
    }
288
338
  }
289
4.12M
290
4.12M
  // Extract min-legal-vector-width attribute.
291
4.12M
  unsigned RequiredVectorWidth = UINT32_MAX;
292
4.12M
  if (F.hasFnAttribute("min-legal-vector-width")) {
293
2.23M
    StringRef Val =
294
2.23M
        F.getFnAttribute("min-legal-vector-width").getValueAsString();
295
2.23M
    unsigned Width;
296
2.23M
    if (!Val.getAsInteger(0, Width)) {
297
2.23M
      Key += ",min-legal-vector-width=";
298
2.23M
      Key += Val;
299
2.23M
      RequiredVectorWidth = Width;
300
2.23M
    }
301
2.23M
  }
302
4.12M
303
4.12M
  // Extracted here so that we make sure there is backing for the StringRef. If
304
4.12M
  // we assigned earlier, its possible the SmallString reallocated leaving a
305
4.12M
  // dangling StringRef.
306
4.12M
  FS = Key.slice(CPU.size(), CPUFSWidth);
307
4.12M
308
4.12M
  auto &I = SubtargetMap[Key];
309
4.12M
  if (!I) {
310
15.2k
    // This needs to be done before we create a new subtarget since any
311
15.2k
    // creation will depend on the TM and the code generation flags on the
312
15.2k
    // function that reside in TargetOptions.
313
15.2k
    resetTargetOptions(F);
314
15.2k
    I = llvm::make_unique<X86Subtarget>(TargetTriple, CPU, FS, *this,
315
15.2k
                                        Options.StackAlignmentOverride,
316
15.2k
                                        PreferVectorWidthOverride,
317
15.2k
                                        RequiredVectorWidth);
318
15.2k
  }
319
4.12M
  return I.get();
320
4.12M
}
321
322
//===----------------------------------------------------------------------===//
323
// Command line options for x86
324
//===----------------------------------------------------------------------===//
325
static cl::opt<bool>
326
UseVZeroUpper("x86-use-vzeroupper", cl::Hidden,
327
  cl::desc("Minimize AVX to SSE transition penalty"),
328
  cl::init(true));
329
330
//===----------------------------------------------------------------------===//
331
// X86 TTI query.
332
//===----------------------------------------------------------------------===//
333
334
TargetTransformInfo
335
2.43M
X86TargetMachine::getTargetTransformInfo(const Function &F) {
336
2.43M
  return TargetTransformInfo(X86TTIImpl(this, F));
337
2.43M
}
338
339
//===----------------------------------------------------------------------===//
340
// Pass Pipeline Configuration
341
//===----------------------------------------------------------------------===//
342
343
namespace {
344
345
/// X86 Code Generator Pass Configuration Options.
346
class X86PassConfig : public TargetPassConfig {
347
public:
348
  X86PassConfig(X86TargetMachine &TM, PassManagerBase &PM)
349
16.0k
    : TargetPassConfig(TM, PM) {}
350
351
12.1k
  X86TargetMachine &getX86TargetMachine() const {
352
12.1k
    return getTM<X86TargetMachine>();
353
12.1k
  }
354
355
  ScheduleDAGInstrs *
356
135k
  createMachineScheduler(MachineSchedContext *C) const override {
357
135k
    ScheduleDAGMILive *DAG = createGenericSchedLive(C);
358
135k
    DAG->addMutation(createX86MacroFusionDAGMutation());
359
135k
    return DAG;
360
135k
  }
361
362
  ScheduleDAGInstrs *
363
12
  createPostMachineScheduler(MachineSchedContext *C) const override {
364
12
    ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
365
12
    DAG->addMutation(createX86MacroFusionDAGMutation());
366
12
    return DAG;
367
12
  }
368
369
  void addIRPasses() override;
370
  bool addInstSelector() override;
371
  bool addIRTranslator() override;
372
  bool addLegalizeMachineIR() override;
373
  bool addRegBankSelect() override;
374
  bool addGlobalInstructionSelect() override;
375
  bool addILPOpts() override;
376
  bool addPreISel() override;
377
  void addMachineSSAOptimization() override;
378
  void addPreRegAlloc() override;
379
  void addPostRegAlloc() override;
380
  void addPreEmitPass() override;
381
  void addPreEmitPass2() override;
382
  void addPreSched2() override;
383
384
  std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
385
};
386
387
class X86ExecutionDomainFix : public ExecutionDomainFix {
388
public:
389
  static char ID;
390
11.3k
  X86ExecutionDomainFix() : ExecutionDomainFix(ID, X86::VR128XRegClass) {}
391
146k
  StringRef getPassName() const override {
392
146k
    return "X86 Execution Dependency Fix";
393
146k
  }
394
};
395
char X86ExecutionDomainFix::ID;
396
397
} // end anonymous namespace
398
399
102k
INITIALIZE_PASS_BEGIN(X86ExecutionDomainFix, "x86-execution-domain-fix",
400
102k
  "X86 Execution Domain Fix", false, false)
401
102k
INITIALIZE_PASS_DEPENDENCY(ReachingDefAnalysis)
402
102k
INITIALIZE_PASS_END(X86ExecutionDomainFix, "x86-execution-domain-fix",
403
  "X86 Execution Domain Fix", false, false)
404
405
16.0k
TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
406
16.0k
  return new X86PassConfig(*this, PM);
407
16.0k
}
408
409
12.2k
void X86PassConfig::addIRPasses() {
410
12.2k
  addPass(createAtomicExpandPass());
411
12.2k
412
12.2k
  TargetPassConfig::addIRPasses();
413
12.2k
414
12.2k
  if (TM->getOptLevel() != CodeGenOpt::None)
415
11.4k
    addPass(createInterleavedAccessPass());
416
12.2k
417
12.2k
  // Add passes that handle indirect branch removal and insertion of a retpoline
418
12.2k
  // thunk. These will be a no-op unless a function subtarget has the retpoline
419
12.2k
  // feature enabled.
420
12.2k
  addPass(createIndirectBrExpandPass());
421
12.2k
}
422
423
12.1k
bool X86PassConfig::addInstSelector() {
424
12.1k
  // Install an instruction selector.
425
12.1k
  addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
426
12.1k
427
12.1k
  // For ELF, cleanup any local-dynamic TLS accesses.
428
12.1k
  if (TM->getTargetTriple().isOSBinFormatELF() &&
429
12.1k
      
getOptLevel() != CodeGenOpt::None6.65k
)
430
6.40k
    addPass(createCleanupLocalDynamicTLSPass());
431
12.1k
432
12.1k
  addPass(createX86GlobalBaseRegPass());
433
12.1k
  return false;
434
12.1k
}
435
436
69
bool X86PassConfig::addIRTranslator() {
437
69
  addPass(new IRTranslator());
438
69
  return false;
439
69
}
440
441
69
bool X86PassConfig::addLegalizeMachineIR() {
442
69
  addPass(new Legalizer());
443
69
  return false;
444
69
}
445
446
69
bool X86PassConfig::addRegBankSelect() {
447
69
  addPass(new RegBankSelect());
448
69
  return false;
449
69
}
450
451
69
bool X86PassConfig::addGlobalInstructionSelect() {
452
69
  addPass(new InstructionSelect());
453
69
  return false;
454
69
}
455
456
11.3k
bool X86PassConfig::addILPOpts() {
457
11.3k
  if (EnableCondBrFoldingPass)
458
14
    addPass(createX86CondBrFolding());
459
11.3k
  addPass(&EarlyIfConverterID);
460
11.3k
  if (EnableMachineCombinerPass)
461
11.3k
    addPass(&MachineCombinerID);
462
11.3k
  addPass(createX86CmovConverterPass());
463
11.3k
  return true;
464
11.3k
}
465
466
12.2k
bool X86PassConfig::addPreISel() {
467
12.2k
  // Only add this pass for 32-bit x86 Windows.
468
12.2k
  const Triple &TT = TM->getTargetTriple();
469
12.2k
  if (TT.isOSWindows() && 
TT.getArch() == Triple::x86775
)
470
312
    addPass(createX86WinEHStatePass());
471
12.2k
  return true;
472
12.2k
}
473
474
12.2k
void X86PassConfig::addPreRegAlloc() {
475
12.2k
  if (getOptLevel() != CodeGenOpt::None) {
476
11.3k
    addPass(&LiveRangeShrinkID);
477
11.3k
    addPass(createX86FixupSetCC());
478
11.3k
    addPass(createX86OptimizeLEAs());
479
11.3k
    addPass(createX86CallFrameOptimization());
480
11.3k
    addPass(createX86AvoidStoreForwardingBlocks());
481
11.3k
  }
482
12.2k
483
12.2k
  addPass(createX86SpeculativeLoadHardeningPass());
484
12.2k
  addPass(createX86FlagsCopyLoweringPass());
485
12.2k
  addPass(createX86WinAllocaExpander());
486
12.2k
}
487
11.3k
void X86PassConfig::addMachineSSAOptimization() {
488
11.3k
  addPass(createX86DomainReassignmentPass());
489
11.3k
  TargetPassConfig::addMachineSSAOptimization();
490
11.3k
}
491
492
12.2k
void X86PassConfig::addPostRegAlloc() {
493
12.2k
  addPass(createX86FloatingPointStackifierPass());
494
12.2k
}
495
496
12.2k
void X86PassConfig::addPreSched2() { addPass(createX86ExpandPseudoPass()); }
497
498
12.2k
void X86PassConfig::addPreEmitPass() {
499
12.2k
  if (getOptLevel() != CodeGenOpt::None) {
500
11.3k
    addPass(new X86ExecutionDomainFix());
501
11.3k
    addPass(createBreakFalseDeps());
502
11.3k
  }
503
12.2k
504
12.2k
  addPass(createX86IndirectBranchTrackingPass());
505
12.2k
506
12.2k
  if (UseVZeroUpper)
507
12.2k
    addPass(createX86IssueVZeroUpperPass());
508
12.2k
509
12.2k
  if (getOptLevel() != CodeGenOpt::None) {
510
11.4k
    addPass(createX86FixupBWInsts());
511
11.4k
    addPass(createX86PadShortFunctions());
512
11.4k
    addPass(createX86FixupLEAs());
513
11.4k
    addPass(createX86EvexToVexInsts());
514
11.4k
  }
515
12.2k
  addPass(createX86DiscriminateMemOpsPass());
516
12.2k
  addPass(createX86InsertPrefetchPass());
517
12.2k
}
518
519
12.2k
void X86PassConfig::addPreEmitPass2() {
520
12.2k
  addPass(createX86RetpolineThunksPass());
521
12.2k
  // Verify basic block incoming and outgoing cfa offset and register values and
522
12.2k
  // correct CFA calculation rule where needed by inserting appropriate CFI
523
12.2k
  // instructions.
524
12.2k
  const Triple &TT = TM->getTargetTriple();
525
12.2k
  const MCAsmInfo *MAI = TM->getMCAsmInfo();
526
12.2k
  if (!TT.isOSDarwin() &&
527
12.2k
      
(7.49k
!TT.isOSWindows()7.49k
||
528
7.49k
       
MAI->getExceptionHandlingType() == ExceptionHandling::DwarfCFI775
))
529
6.78k
    addPass(createCFIInstrInserter());
530
12.2k
}
531
532
1.09k
std::unique_ptr<CSEConfigBase> X86PassConfig::getCSEConfig() const {
533
1.09k
  return getStandardCSEConfigForOpt(TM->getOptLevel());
534
1.09k
}