Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/XCore/XCoreInstrInfo.h
Line
Count
Source
1
//===-- XCoreInstrInfo.h - XCore Instruction Information --------*- C++ -*-===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file contains the XCore implementation of the TargetInstrInfo class.
10
//
11
//===----------------------------------------------------------------------===//
12
13
#ifndef LLVM_LIB_TARGET_XCORE_XCOREINSTRINFO_H
14
#define LLVM_LIB_TARGET_XCORE_XCOREINSTRINFO_H
15
16
#include "XCoreRegisterInfo.h"
17
#include "llvm/CodeGen/TargetInstrInfo.h"
18
19
#define GET_INSTRINFO_HEADER
20
#include "XCoreGenInstrInfo.inc"
21
22
namespace llvm {
23
24
class XCoreInstrInfo : public XCoreGenInstrInfo {
25
  const XCoreRegisterInfo RI;
26
  virtual void anchor();
27
public:
28
  XCoreInstrInfo();
29
30
  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
31
  /// such, whenever a client has an instance of instruction info, it should
32
  /// always be able to get register info as well (through this method).
33
  ///
34
25.5k
  const TargetRegisterInfo &getRegisterInfo() const { return RI; }
35
36
  /// isLoadFromStackSlot - If the specified machine instruction is a direct
37
  /// load from a stack slot, return the virtual or physical register number of
38
  /// the destination along with the FrameIndex of the loaded stack slot.  If
39
  /// not, return 0.  This predicate must return 0 if the instruction has
40
  /// any side effects other than loading from the stack slot.
41
  unsigned isLoadFromStackSlot(const MachineInstr &MI,
42
                               int &FrameIndex) const override;
43
44
  /// isStoreToStackSlot - If the specified machine instruction is a direct
45
  /// store to a stack slot, return the virtual or physical register number of
46
  /// the source reg along with the FrameIndex of the loaded stack slot.  If
47
  /// not, return 0.  This predicate must return 0 if the instruction has
48
  /// any side effects other than storing to the stack slot.
49
  unsigned isStoreToStackSlot(const MachineInstr &MI,
50
                              int &FrameIndex) const override;
51
52
  bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
53
                     MachineBasicBlock *&FBB,
54
                     SmallVectorImpl<MachineOperand> &Cond,
55
                     bool AllowModify) const override;
56
57
  unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
58
                        MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
59
                        const DebugLoc &DL,
60
                        int *BytesAdded = nullptr) const override;
61
62
  unsigned removeBranch(MachineBasicBlock &MBB,
63
                        int *BytesRemoved = nullptr) const override;
64
65
  void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
66
                   const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
67
                   bool KillSrc) const override;
68
69
  void storeRegToStackSlot(MachineBasicBlock &MBB,
70
                           MachineBasicBlock::iterator MI,
71
                           unsigned SrcReg, bool isKill, int FrameIndex,
72
                           const TargetRegisterClass *RC,
73
                           const TargetRegisterInfo *TRI) const override;
74
75
  void loadRegFromStackSlot(MachineBasicBlock &MBB,
76
                            MachineBasicBlock::iterator MI,
77
                            unsigned DestReg, int FrameIndex,
78
                            const TargetRegisterClass *RC,
79
                            const TargetRegisterInfo *TRI) const override;
80
81
  bool reverseBranchCondition(
82
                          SmallVectorImpl<MachineOperand> &Cond) const override;
83
84
  // Emit code before MBBI to load immediate value into physical register Reg.
85
  // Returns an iterator to the new instruction.
86
  MachineBasicBlock::iterator loadImmediate(MachineBasicBlock &MBB,
87
                                            MachineBasicBlock::iterator MI,
88
                                            unsigned Reg, uint64_t Value) const;
89
};
90
91
}
92
93
#endif