Coverage Report

Created: 2017-10-03 07:32

/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/llvm/include/llvm/CodeGen/LiveIntervalAnalysis.h
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//===- LiveIntervalAnalysis.h - Live Interval Analysis ----------*- C++ -*-===//
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//
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//                     The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file This file implements the LiveInterval analysis pass.  Given some
11
/// numbering of each the machine instructions (in this implemention depth-first
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/// order) an interval [i, j) is said to be a live interval for register v if
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/// there is no instruction with number j' > j such that v is live at j' and
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/// there is no instruction with number i' < i such that v is live at i'. In
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/// this implementation intervals can have holes, i.e. an interval might look
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/// like [1,20), [50,65), [1000,1001).
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_LIVEINTERVALANALYSIS_H
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#define LLVM_CODEGEN_LIVEINTERVALANALYSIS_H
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/IndexedMap.h"
25
#include "llvm/ADT/SmallVector.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/CodeGen/LiveInterval.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/SlotIndexes.h"
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#include "llvm/MC/LaneBitmask.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/ErrorHandling.h"
35
#include "llvm/Target/TargetRegisterInfo.h"
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#include <cassert>
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#include <cstdint>
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#include <utility>
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40
namespace llvm {
41
42
extern cl::opt<bool> UseSegmentSetForPhysRegs;
43
44
class BitVector;
45
class LiveRangeCalc;
46
class MachineBlockFrequencyInfo;
47
class MachineDominatorTree;
48
class MachineFunction;
49
class MachineInstr;
50
class MachineRegisterInfo;
51
class raw_ostream;
52
class TargetInstrInfo;
53
class VirtRegMap;
54
55
  class LiveIntervals : public MachineFunctionPass {
56
    MachineFunction* MF;
57
    MachineRegisterInfo* MRI;
58
    const TargetRegisterInfo* TRI;
59
    const TargetInstrInfo* TII;
60
    AliasAnalysis *AA;
61
    SlotIndexes* Indexes;
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    MachineDominatorTree *DomTree = nullptr;
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    LiveRangeCalc *LRCalc = nullptr;
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65
    /// Special pool allocator for VNInfo's (LiveInterval val#).
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    VNInfo::Allocator VNInfoAllocator;
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    /// Live interval pointers for all the virtual registers.
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    IndexedMap<LiveInterval*, VirtReg2IndexFunctor> VirtRegIntervals;
70
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    /// Sorted list of instructions with register mask operands. Always use the
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    /// 'r' slot, RegMasks are normal clobbers, not early clobbers.
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    SmallVector<SlotIndex, 8> RegMaskSlots;
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    /// This vector is parallel to RegMaskSlots, it holds a pointer to the
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    /// corresponding register mask.  This pointer can be recomputed as:
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    ///
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    ///   MI = Indexes->getInstructionFromIndex(RegMaskSlot[N]);
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    ///   unsigned OpNum = findRegMaskOperand(MI);
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    ///   RegMaskBits[N] = MI->getOperand(OpNum).getRegMask();
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    ///
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    /// This is kept in a separate vector partly because some standard
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    /// libraries don't support lower_bound() with mixed objects, partly to
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    /// improve locality when searching in RegMaskSlots.
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    /// Also see the comment in LiveInterval::find().
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    SmallVector<const uint32_t*, 8> RegMaskBits;
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    /// For each basic block number, keep (begin, size) pairs indexing into the
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    /// RegMaskSlots and RegMaskBits arrays.
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    /// Note that basic block numbers may not be layout contiguous, that's why
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    /// we can't just keep track of the first register mask in each basic
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    /// block.
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    SmallVector<std::pair<unsigned, unsigned>, 8> RegMaskBlocks;
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    /// Keeps a live range set for each register unit to track fixed physreg
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    /// interference.
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    SmallVector<LiveRange*, 0> RegUnitRanges;
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  public:
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    static char ID;
101
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    LiveIntervals();
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    ~LiveIntervals() override;
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    /// Calculate the spill weight to assign to a single instruction.
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    static float getSpillWeight(bool isDef, bool isUse,
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                                const MachineBlockFrequencyInfo *MBFI,
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                                const MachineInstr &Instr);
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110
177M
    LiveInterval &getInterval(unsigned Reg) {
111
177M
      if (hasInterval(Reg))
112
176M
        return *VirtRegIntervals[Reg];
113
177M
      else
114
306k
        return createAndComputeVirtRegInterval(Reg);
115
177M
    }
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117
56.1M
    const LiveInterval &getInterval(unsigned Reg) const {
118
56.1M
      return const_cast<LiveIntervals*>(this)->getInterval(Reg);
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56.1M
    }
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121
183M
    bool hasInterval(unsigned Reg) const {
122
183M
      return VirtRegIntervals.inBounds(Reg) && VirtRegIntervals[Reg];
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183M
    }
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    /// Interval creation.
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18.0M
    LiveInterval &createEmptyInterval(unsigned Reg) {
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18.0M
      assert(!hasInterval(Reg) && "Interval already exists!");
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18.0M
      VirtRegIntervals.grow(Reg);
129
18.0M
      VirtRegIntervals[Reg] = createInterval(Reg);
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18.0M
      return *VirtRegIntervals[Reg];
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18.0M
    }
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133
17.6M
    LiveInterval &createAndComputeVirtRegInterval(unsigned Reg) {
134
17.6M
      LiveInterval &LI = createEmptyInterval(Reg);
135
17.6M
      computeVirtRegInterval(LI);
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17.6M
      return LI;
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17.6M
    }
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    /// Interval removal.
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7.34M
    void removeInterval(unsigned Reg) {
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7.34M
      delete VirtRegIntervals[Reg];
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7.34M
      VirtRegIntervals[Reg] = nullptr;
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7.34M
    }
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    /// Given a register and an instruction, adds a live segment from that
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    /// instruction to the end of its MBB.
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    LiveInterval::Segment addSegmentToEndOfBlock(unsigned reg,
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                                                 MachineInstr &startInst);
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    /// After removing some uses of a register, shrink its live range to just
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    /// the remaining uses. This method does not compute reaching defs for new
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    /// uses, and it doesn't remove dead defs.
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    /// Dead PHIDef values are marked as unused. New dead machine instructions
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    /// are added to the dead vector. Returns true if the interval may have been
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    /// separated into multiple connected components.
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    bool shrinkToUses(LiveInterval *li,
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                      SmallVectorImpl<MachineInstr*> *dead = nullptr);
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    /// Specialized version of
160
    /// shrinkToUses(LiveInterval *li, SmallVectorImpl<MachineInstr*> *dead)
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    /// that works on a subregister live range and only looks at uses matching
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    /// the lane mask of the subregister range.
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    /// This may leave the subrange empty which needs to be cleaned up with
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    /// LiveInterval::removeEmptySubranges() afterwards.
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    void shrinkToUses(LiveInterval::SubRange &SR, unsigned Reg);
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    /// Extend the live range \p LR to reach all points in \p Indices. The
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    /// points in the \p Indices array must be jointly dominated by the union
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    /// of the existing defs in \p LR and points in \p Undefs.
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    ///
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    /// PHI-defs are added as needed to maintain SSA form.
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    ///
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    /// If a SlotIndex in \p Indices is the end index of a basic block, \p LR
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    /// will be extended to be live out of the basic block.
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    /// If a SlotIndex in \p Indices is jointy dominated only by points in
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    /// \p Undefs, the live range will not be extended to that point.
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    ///
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    /// See also LiveRangeCalc::extend().
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    void extendToIndices(LiveRange &LR, ArrayRef<SlotIndex> Indices,
180
                         ArrayRef<SlotIndex> Undefs);
181
182
56.5k
    void extendToIndices(LiveRange &LR, ArrayRef<SlotIndex> Indices) {
183
56.5k
      extendToIndices(LR, Indices, /*Undefs=*/{});
184
56.5k
    }
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    /// If \p LR has a live value at \p Kill, prune its live range by removing
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    /// any liveness reachable from Kill. Add live range end points to
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    /// EndPoints such that extendToIndices(LI, EndPoints) will reconstruct the
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    /// value's live range.
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    ///
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    /// Calling pruneValue() and extendToIndices() can be used to reconstruct
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    /// SSA form after adding defs to a virtual register.
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    void pruneValue(LiveRange &LR, SlotIndex Kill,
194
                    SmallVectorImpl<SlotIndex> *EndPoints);
195
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    /// This function should not be used. Its intend is to tell you that
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    /// you are doing something wrong if you call pruveValue directly on a
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    /// LiveInterval. Indeed, you are supposed to call pruneValue on the main
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    /// LiveRange and all the LiveRange of the subranges if any.
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    LLVM_ATTRIBUTE_UNUSED void pruneValue(LiveInterval &, SlotIndex,
201
0
                                          SmallVectorImpl<SlotIndex> *) {
202
0
      llvm_unreachable(
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0
          "Use pruneValue on the main LiveRange and on each subrange");
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0
    }
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139M
    SlotIndexes *getSlotIndexes() const {
207
139M
      return Indexes;
208
139M
    }
209
210
4.90M
    AliasAnalysis *getAliasAnalysis() const {
211
4.90M
      return AA;
212
4.90M
    }
213
214
    /// Returns true if the specified machine instr has been removed or was
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    /// never entered in the map.
216
7.36M
    bool isNotInMIMap(const MachineInstr &Instr) const {
217
7.36M
      return !Indexes->hasIndex(Instr);
218
7.36M
    }
219
220
    /// Returns the base index of the given instruction.
221
87.8M
    SlotIndex getInstructionIndex(const MachineInstr &Instr) const {
222
87.8M
      return Indexes->getInstructionIndex(Instr);
223
87.8M
    }
224
225
    /// Returns the instruction associated with the given index.
226
35.7M
    MachineInstr* getInstructionFromIndex(SlotIndex index) const {
227
35.7M
      return Indexes->getInstructionFromIndex(index);
228
35.7M
    }
229
230
    /// Return the first index in the given basic block.
231
4.32M
    SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const {
232
4.32M
      return Indexes->getMBBStartIdx(mbb);
233
4.32M
    }
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235
    /// Return the last index in the given basic block.
236
12.6M
    SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const {
237
12.6M
      return Indexes->getMBBEndIdx(mbb);
238
12.6M
    }
239
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    bool isLiveInToMBB(const LiveRange &LR,
241
931k
                       const MachineBasicBlock *mbb) const {
242
931k
      return LR.liveAt(getMBBStartIdx(mbb));
243
931k
    }
244
245
    bool isLiveOutOfMBB(const LiveRange &LR,
246
1.57M
                        const MachineBasicBlock *mbb) const {
247
1.57M
      return LR.liveAt(getMBBEndIdx(mbb).getPrevSlot());
248
1.57M
    }
249
250
10.3M
    MachineBasicBlock* getMBBFromIndex(SlotIndex index) const {
251
10.3M
      return Indexes->getMBBFromIndex(index);
252
10.3M
    }
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254
0
    void insertMBBInMaps(MachineBasicBlock *MBB) {
255
0
      Indexes->insertMBBInMaps(MBB);
256
0
      assert(unsigned(MBB->getNumber()) == RegMaskBlocks.size() &&
257
0
             "Blocks must be added in order.");
258
0
      RegMaskBlocks.push_back(std::make_pair(RegMaskSlots.size(), 0));
259
0
    }
260
261
16.1k
    SlotIndex InsertMachineInstrInMaps(MachineInstr &MI) {
262
16.1k
      return Indexes->insertMachineInstrInMaps(MI);
263
16.1k
    }
264
265
    void InsertMachineInstrRangeInMaps(MachineBasicBlock::iterator B,
266
145k
                                       MachineBasicBlock::iterator E) {
267
290k
      for (MachineBasicBlock::iterator I = B; 
I != E290k
;
++I145k
)
268
145k
        Indexes->insertMachineInstrInMaps(*I);
269
145k
    }
270
271
7.90M
    void RemoveMachineInstrFromMaps(MachineInstr &MI) {
272
7.90M
      Indexes->removeMachineInstrFromMaps(MI);
273
7.90M
    }
274
275
961k
    SlotIndex ReplaceMachineInstrInMaps(MachineInstr &MI, MachineInstr &NewMI) {
276
961k
      return Indexes->replaceMachineInstrInMaps(MI, NewMI);
277
961k
    }
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279
25.6M
    VNInfo::Allocator& getVNInfoAllocator() { return VNInfoAllocator; }
280
281
    void getAnalysisUsage(AnalysisUsage &AU) const override;
282
    void releaseMemory() override;
283
284
    /// Pass entry point; Calculates LiveIntervals.
285
    bool runOnMachineFunction(MachineFunction&) override;
286
287
    /// Implement the dump method.
288
    void print(raw_ostream &O, const Module* = nullptr) const override;
289
290
    /// If LI is confined to a single basic block, return a pointer to that
291
    /// block.  If LI is live in to or out of any block, return NULL.
292
    MachineBasicBlock *intervalIsInOneMBB(const LiveInterval &LI) const;
293
294
    /// Returns true if VNI is killed by any PHI-def values in LI.
295
    /// This may conservatively return true to avoid expensive computations.
296
    bool hasPHIKill(const LiveInterval &LI, const VNInfo *VNI) const;
297
298
    /// Add kill flags to any instruction that kills a virtual register.
299
    void addKillFlags(const VirtRegMap*);
300
301
    /// Call this method to notify LiveIntervals that instruction \p MI has been
302
    /// moved within a basic block. This will update the live intervals for all
303
    /// operands of \p MI. Moves between basic blocks are not supported.
304
    ///
305
    /// \param UpdateFlags Update live intervals for nonallocatable physregs.
306
    void handleMove(MachineInstr &MI, bool UpdateFlags = false);
307
308
    /// Update intervals for operands of \p MI so that they begin/end on the
309
    /// SlotIndex for \p BundleStart.
310
    ///
311
    /// \param UpdateFlags Update live intervals for nonallocatable physregs.
312
    ///
313
    /// Requires MI and BundleStart to have SlotIndexes, and assumes
314
    /// existing liveness is accurate. BundleStart should be the first
315
    /// instruction in the Bundle.
316
    void handleMoveIntoBundle(MachineInstr &MI, MachineInstr &BundleStart,
317
                              bool UpdateFlags = false);
318
319
    /// Update live intervals for instructions in a range of iterators. It is
320
    /// intended for use after target hooks that may insert or remove
321
    /// instructions, and is only efficient for a small number of instructions.
322
    ///
323
    /// OrigRegs is a vector of registers that were originally used by the
324
    /// instructions in the range between the two iterators.
325
    ///
326
    /// Currently, the only only changes that are supported are simple removal
327
    /// and addition of uses.
328
    void repairIntervalsInRange(MachineBasicBlock *MBB,
329
                                MachineBasicBlock::iterator Begin,
330
                                MachineBasicBlock::iterator End,
331
                                ArrayRef<unsigned> OrigRegs);
332
333
    // Register mask functions.
334
    //
335
    // Machine instructions may use a register mask operand to indicate that a
336
    // large number of registers are clobbered by the instruction.  This is
337
    // typically used for calls.
338
    //
339
    // For compile time performance reasons, these clobbers are not recorded in
340
    // the live intervals for individual physical registers.  Instead,
341
    // LiveIntervalAnalysis maintains a sorted list of instructions with
342
    // register mask operands.
343
344
    /// Returns a sorted array of slot indices of all instructions with
345
    /// register mask operands.
346
110M
    ArrayRef<SlotIndex> getRegMaskSlots() const { return RegMaskSlots; }
347
348
    /// Returns a sorted array of slot indices of all instructions with register
349
    /// mask operands in the basic block numbered \p MBBNum.
350
103M
    ArrayRef<SlotIndex> getRegMaskSlotsInBlock(unsigned MBBNum) const {
351
103M
      std::pair<unsigned, unsigned> P = RegMaskBlocks[MBBNum];
352
103M
      return getRegMaskSlots().slice(P.first, P.second);
353
103M
    }
354
355
    /// Returns an array of register mask pointers corresponding to
356
    /// getRegMaskSlots().
357
106M
    ArrayRef<const uint32_t*> getRegMaskBits() const { return RegMaskBits; }
358
359
    /// Returns an array of mask pointers corresponding to
360
    /// getRegMaskSlotsInBlock(MBBNum).
361
103M
    ArrayRef<const uint32_t*> getRegMaskBitsInBlock(unsigned MBBNum) const {
362
103M
      std::pair<unsigned, unsigned> P = RegMaskBlocks[MBBNum];
363
103M
      return getRegMaskBits().slice(P.first, P.second);
364
103M
    }
365
366
    /// Test if \p LI is live across any register mask instructions, and
367
    /// compute a bit mask of physical registers that are not clobbered by any
368
    /// of them.
369
    ///
370
    /// Returns false if \p LI doesn't cross any register mask instructions. In
371
    /// that case, the bit vector is not filled in.
372
    bool checkRegMaskInterference(LiveInterval &LI,
373
                                  BitVector &UsableRegs);
374
375
    // Register unit functions.
376
    //
377
    // Fixed interference occurs when MachineInstrs use physregs directly
378
    // instead of virtual registers. This typically happens when passing
379
    // arguments to a function call, or when instructions require operands in
380
    // fixed registers.
381
    //
382
    // Each physreg has one or more register units, see MCRegisterInfo. We
383
    // track liveness per register unit to handle aliasing registers more
384
    // efficiently.
385
386
    /// Return the live range for register unit \p Unit. It will be computed if
387
    /// it doesn't exist.
388
86.8M
    LiveRange &getRegUnit(unsigned Unit) {
389
86.8M
      LiveRange *LR = RegUnitRanges[Unit];
390
86.8M
      if (
!LR86.8M
) {
391
3.18M
        // Compute missing ranges on demand.
392
3.18M
        // Use segment set to speed-up initial computation of the live range.
393
3.18M
        RegUnitRanges[Unit] = LR = new LiveRange(UseSegmentSetForPhysRegs);
394
3.18M
        computeRegUnitRange(*LR, Unit);
395
3.18M
      }
396
86.8M
      return *LR;
397
86.8M
    }
398
399
    /// Return the live range for register unit \p Unit if it has already been
400
    /// computed, or nullptr if it hasn't been computed yet.
401
138M
    LiveRange *getCachedRegUnit(unsigned Unit) {
402
138M
      return RegUnitRanges[Unit];
403
138M
    }
404
405
1.06M
    const LiveRange *getCachedRegUnit(unsigned Unit) const {
406
1.06M
      return RegUnitRanges[Unit];
407
1.06M
    }
408
409
    /// Remove computed live range for register unit \p Unit. Subsequent uses
410
    /// should rely on on-demand recomputation.
411
538
    void removeRegUnit(unsigned Unit) {
412
538
      delete RegUnitRanges[Unit];
413
538
      RegUnitRanges[Unit] = nullptr;
414
538
    }
415
416
    /// Remove value numbers and related live segments starting at position
417
    /// \p Pos that are part of any liverange of physical register \p Reg or one
418
    /// of its subregisters.
419
    void removePhysRegDefAt(unsigned Reg, SlotIndex Pos);
420
421
    /// Remove value number and related live segments of \p LI and its subranges
422
    /// that start at position \p Pos.
423
    void removeVRegDefAt(LiveInterval &LI, SlotIndex Pos);
424
425
    /// Split separate components in LiveInterval \p LI into separate intervals.
426
    void splitSeparateComponents(LiveInterval &LI,
427
                                 SmallVectorImpl<LiveInterval*> &SplitLIs);
428
429
    /// For live interval \p LI with correct SubRanges construct matching
430
    /// information for the main live range. Expects the main live range to not
431
    /// have any segments or value numbers.
432
    void constructMainRangeFromSubranges(LiveInterval &LI);
433
434
  private:
435
    /// Compute live intervals for all virtual registers.
436
    void computeVirtRegs();
437
438
    /// Compute RegMaskSlots and RegMaskBits.
439
    void computeRegMasks();
440
441
    /// Walk the values in \p LI and check for dead values:
442
    /// - Dead PHIDef values are marked as unused.
443
    /// - Dead operands are marked as such.
444
    /// - Completely dead machine instructions are added to the \p dead vector
445
    ///   if it is not nullptr.
446
    /// Returns true if any PHI value numbers have been removed which may
447
    /// have separated the interval into multiple connected components.
448
    bool computeDeadValues(LiveInterval &LI,
449
                           SmallVectorImpl<MachineInstr*> *dead);
450
451
    static LiveInterval* createInterval(unsigned Reg);
452
453
    void printInstrs(raw_ostream &O) const;
454
    void dumpInstrs() const;
455
456
    void computeLiveInRegUnits();
457
    void computeRegUnitRange(LiveRange&, unsigned Unit);
458
    void computeVirtRegInterval(LiveInterval&);
459
460
461
    /// Helper function for repairIntervalsInRange(), walks backwards and
462
    /// creates/modifies live segments in \p LR to match the operands found.
463
    /// Only full operands or operands with subregisters matching \p LaneMask
464
    /// are considered.
465
    void repairOldRegInRange(MachineBasicBlock::iterator Begin,
466
                             MachineBasicBlock::iterator End,
467
                             const SlotIndex endIdx, LiveRange &LR,
468
                             unsigned Reg,
469
                             LaneBitmask LaneMask = LaneBitmask::getAll());
470
471
    class HMEditor;
472
  };
473
474
} // end namespace llvm
475
476
#endif // LLVM_CODEGEN_LIVEINTERVALANALYSIS_H