Coverage Report

Created: 2017-10-03 07:32

/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/llvm/lib/CodeGen/AggressiveAntiDepBreaker.h
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//=- llvm/CodeGen/AggressiveAntiDepBreaker.h - Anti-Dep Support -*- C++ -*-=//
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//
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//                     The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the AggressiveAntiDepBreaker class, which
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// implements register anti-dependence breaking during post-RA
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// scheduling. It attempts to break all anti-dependencies within a
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// block.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_CODEGEN_AGGRESSIVEANTIDEPBREAKER_H
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#define LLVM_LIB_CODEGEN_AGGRESSIVEANTIDEPBREAKER_H
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#include "AntiDepBreaker.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/ScheduleDAG.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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#include <map>
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namespace llvm {
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class RegisterClassInfo;
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  /// Contains all the state necessary for anti-dep breaking.
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class LLVM_LIBRARY_VISIBILITY AggressiveAntiDepState {
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  public:
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    /// Information about a register reference within a liverange
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    typedef struct {
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      /// The registers operand
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      MachineOperand *Operand;
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      /// The register class
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      const TargetRegisterClass *RC;
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    } RegisterReference;
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  private:
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    /// Number of non-virtual target registers (i.e. TRI->getNumRegs()).
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    const unsigned NumTargetRegs;
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    /// Implements a disjoint-union data structure to
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    /// form register groups. A node is represented by an index into
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    /// the vector. A node can "point to" itself to indicate that it
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    /// is the parent of a group, or point to another node to indicate
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    /// that it is a member of the same group as that node.
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    std::vector<unsigned> GroupNodes;
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    /// For each register, the index of the GroupNode
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    /// currently representing the group that the register belongs to.
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    /// Register 0 is always represented by the 0 group, a group
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    /// composed of registers that are not eligible for anti-aliasing.
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    std::vector<unsigned> GroupNodeIndices;
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    /// Map registers to all their references within a live range.
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    std::multimap<unsigned, RegisterReference> RegRefs;
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    /// The index of the most recent kill (proceeding bottom-up),
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    /// or ~0u if the register is not live.
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    std::vector<unsigned> KillIndices;
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    /// The index of the most recent complete def (proceeding bottom
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    /// up), or ~0u if the register is live.
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    std::vector<unsigned> DefIndices;
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  public:
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    AggressiveAntiDepState(const unsigned TargetRegs, MachineBasicBlock *BB);
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    /// Return the kill indices.
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    std::vector<unsigned> &GetKillIndices() { return KillIndices; }
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    /// Return the define indices.
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    std::vector<unsigned> &GetDefIndices() { return DefIndices; }
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    /// Return the RegRefs map.
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    std::multimap<unsigned, RegisterReference>& GetRegRefs() { return RegRefs; }
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    // Get the group for a register. The returned value is
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    // the index of the GroupNode representing the group.
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    unsigned GetGroup(unsigned Reg);
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    // Return a vector of the registers belonging to a group.
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    // If RegRefs is non-NULL then only included referenced registers.
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    void GetGroupRegs(
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       unsigned Group,
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       std::vector<unsigned> &Regs,
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       std::multimap<unsigned,
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         AggressiveAntiDepState::RegisterReference> *RegRefs);
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    // Union Reg1's and Reg2's groups to form a new group.
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    // Return the index of the GroupNode representing the group.
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    unsigned UnionGroups(unsigned Reg1, unsigned Reg2);
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    // Remove a register from its current group and place
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    // it alone in its own group. Return the index of the GroupNode
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    // representing the registers new group.
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    unsigned LeaveGroup(unsigned Reg);
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    /// Return true if Reg is live.
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    bool IsLive(unsigned Reg);
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  };
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  class LLVM_LIBRARY_VISIBILITY AggressiveAntiDepBreaker
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      : public AntiDepBreaker {
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    MachineFunction& MF;
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    MachineRegisterInfo &MRI;
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    const TargetInstrInfo *TII;
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    const TargetRegisterInfo *TRI;
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    const RegisterClassInfo &RegClassInfo;
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    /// The set of registers that should only be
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    /// renamed if they are on the critical path.
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    BitVector CriticalPathSet;
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    /// The state used to identify and rename anti-dependence registers.
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    AggressiveAntiDepState *State;
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  public:
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    AggressiveAntiDepBreaker(MachineFunction& MFi,
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                          const RegisterClassInfo &RCI,
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                          TargetSubtargetInfo::RegClassVector& CriticalPathRCs);
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    ~AggressiveAntiDepBreaker() override;
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    /// Initialize anti-dep breaking for a new basic block.
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    void StartBlock(MachineBasicBlock *BB) override;
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    /// Identifiy anti-dependencies along the critical path
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    /// of the ScheduleDAG and break them by renaming registers.
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    ///
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    unsigned BreakAntiDependencies(const std::vector<SUnit>& SUnits,
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                                   MachineBasicBlock::iterator Begin,
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                                   MachineBasicBlock::iterator End,
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                                   unsigned InsertPosIndex,
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                                   DbgValueVector &DbgValues) override;
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    /// Update liveness information to account for the current
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    /// instruction, which will not be scheduled.
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    ///
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    void Observe(MachineInstr &MI, unsigned Count,
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                 unsigned InsertPosIndex) override;
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    /// Finish anti-dep breaking for a basic block.
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    void FinishBlock() override;
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  private:
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    /// Keep track of a position in the allocation order for each regclass.
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    typedef std::map<const TargetRegisterClass *, unsigned> RenameOrderType;
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    /// Return true if MO represents a register
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    /// that is both implicitly used and defined in MI
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    bool IsImplicitDefUse(MachineInstr &MI, MachineOperand &MO);
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    /// If MI implicitly def/uses a register, then
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    /// return that register and all subregisters.
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    void GetPassthruRegs(MachineInstr &MI, std::set<unsigned> &PassthruRegs);
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    void HandleLastUse(unsigned Reg, unsigned KillIdx, const char *tag,
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                       const char *header = nullptr,
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                       const char *footer = nullptr);
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    void PrescanInstruction(MachineInstr &MI, unsigned Count,
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                            std::set<unsigned> &PassthruRegs);
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    void ScanInstruction(MachineInstr &MI, unsigned Count);
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    BitVector GetRenameRegisters(unsigned Reg);
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    bool FindSuitableFreeRegisters(unsigned AntiDepGroupIndex,
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                                   RenameOrderType& RenameOrder,
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                                   std::map<unsigned, unsigned> &RenameMap);
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  };
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}
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#endif