/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/llvm/lib/CodeGen/ExpandPostRAPseudos.cpp
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1 | | //===-- ExpandPostRAPseudos.cpp - Pseudo instruction expansion pass -------===// |
2 | | // |
3 | | // The LLVM Compiler Infrastructure |
4 | | // |
5 | | // This file is distributed under the University of Illinois Open Source |
6 | | // License. See LICENSE.TXT for details. |
7 | | // |
8 | | //===----------------------------------------------------------------------===// |
9 | | // |
10 | | // This file defines a pass that expands COPY and SUBREG_TO_REG pseudo |
11 | | // instructions after register allocation. |
12 | | // |
13 | | //===----------------------------------------------------------------------===// |
14 | | |
15 | | #include "llvm/CodeGen/MachineFunctionPass.h" |
16 | | #include "llvm/CodeGen/MachineInstr.h" |
17 | | #include "llvm/CodeGen/MachineInstrBuilder.h" |
18 | | #include "llvm/CodeGen/MachineRegisterInfo.h" |
19 | | #include "llvm/CodeGen/Passes.h" |
20 | | #include "llvm/Support/Debug.h" |
21 | | #include "llvm/Support/raw_ostream.h" |
22 | | #include "llvm/Target/TargetInstrInfo.h" |
23 | | #include "llvm/Target/TargetRegisterInfo.h" |
24 | | #include "llvm/Target/TargetSubtargetInfo.h" |
25 | | |
26 | | using namespace llvm; |
27 | | |
28 | | #define DEBUG_TYPE "postrapseudos" |
29 | | |
30 | | namespace { |
31 | | struct ExpandPostRA : public MachineFunctionPass { |
32 | | private: |
33 | | const TargetRegisterInfo *TRI; |
34 | | const TargetInstrInfo *TII; |
35 | | |
36 | | public: |
37 | | static char ID; // Pass identification, replacement for typeid |
38 | 33.5k | ExpandPostRA() : MachineFunctionPass(ID) {} |
39 | | |
40 | 33.4k | void getAnalysisUsage(AnalysisUsage &AU) const override { |
41 | 33.4k | AU.setPreservesCFG(); |
42 | 33.4k | AU.addPreservedID(MachineLoopInfoID); |
43 | 33.4k | AU.addPreservedID(MachineDominatorsID); |
44 | 33.4k | MachineFunctionPass::getAnalysisUsage(AU); |
45 | 33.4k | } |
46 | | |
47 | | /// runOnMachineFunction - pass entry point |
48 | | bool runOnMachineFunction(MachineFunction&) override; |
49 | | |
50 | | private: |
51 | | bool LowerSubregToReg(MachineInstr *MI); |
52 | | bool LowerCopy(MachineInstr *MI); |
53 | | |
54 | | void TransferImplicitOperands(MachineInstr *MI); |
55 | | }; |
56 | | } // end anonymous namespace |
57 | | |
58 | | char ExpandPostRA::ID = 0; |
59 | | char &llvm::ExpandPostRAPseudosID = ExpandPostRA::ID; |
60 | | |
61 | | INITIALIZE_PASS(ExpandPostRA, DEBUG_TYPE, |
62 | | "Post-RA pseudo instruction expansion pass", false, false) |
63 | | |
64 | | /// TransferImplicitOperands - MI is a pseudo-instruction, and the lowered |
65 | | /// replacement instructions immediately precede it. Copy any implicit |
66 | | /// operands from MI to the replacement instruction. |
67 | 155k | void ExpandPostRA::TransferImplicitOperands(MachineInstr *MI) { |
68 | 155k | MachineBasicBlock::iterator CopyMI = MI; |
69 | 155k | --CopyMI; |
70 | 155k | |
71 | 155k | for (const MachineOperand &MO : MI->implicit_operands()) |
72 | 156k | if (156k MO.isReg()156k ) |
73 | 156k | CopyMI->addOperand(MO); |
74 | 155k | } |
75 | | |
76 | 204 | bool ExpandPostRA::LowerSubregToReg(MachineInstr *MI) { |
77 | 204 | MachineBasicBlock *MBB = MI->getParent(); |
78 | 204 | assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) && |
79 | 204 | MI->getOperand(1).isImm() && |
80 | 204 | (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) && |
81 | 204 | MI->getOperand(3).isImm() && "Invalid subreg_to_reg"); |
82 | 204 | |
83 | 204 | unsigned DstReg = MI->getOperand(0).getReg(); |
84 | 204 | unsigned InsReg = MI->getOperand(2).getReg(); |
85 | 204 | assert(!MI->getOperand(2).getSubReg() && "SubIdx on physreg?"); |
86 | 204 | unsigned SubIdx = MI->getOperand(3).getImm(); |
87 | 204 | |
88 | 204 | assert(SubIdx != 0 && "Invalid index for insert_subreg"); |
89 | 204 | unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx); |
90 | 204 | |
91 | 204 | assert(TargetRegisterInfo::isPhysicalRegister(DstReg) && |
92 | 204 | "Insert destination must be in a physical register"); |
93 | 204 | assert(TargetRegisterInfo::isPhysicalRegister(InsReg) && |
94 | 204 | "Inserted value must be in a physical register"); |
95 | 204 | |
96 | 204 | DEBUG(dbgs() << "subreg: CONVERTING: " << *MI); |
97 | 204 | |
98 | 204 | if (MI->allDefsAreDead()204 ) { |
99 | 0 | MI->setDesc(TII->get(TargetOpcode::KILL)); |
100 | 0 | DEBUG(dbgs() << "subreg: replaced by: " << *MI); |
101 | 0 | return true; |
102 | 0 | } |
103 | 204 | |
104 | 204 | if (204 DstSubReg == InsReg204 ) { |
105 | 19 | // No need to insert an identity copy instruction. |
106 | 19 | // Watch out for case like this: |
107 | 19 | // %RAX<def> = SUBREG_TO_REG 0, %EAX<kill>, 3 |
108 | 19 | // We must leave %RAX live. |
109 | 19 | if (DstReg != InsReg19 ) { |
110 | 19 | MI->setDesc(TII->get(TargetOpcode::KILL)); |
111 | 19 | MI->RemoveOperand(3); // SubIdx |
112 | 19 | MI->RemoveOperand(1); // Imm |
113 | 19 | DEBUG(dbgs() << "subreg: replace by: " << *MI); |
114 | 19 | return true; |
115 | 19 | } |
116 | 0 | DEBUG0 (dbgs() << "subreg: eliminated!"); |
117 | 204 | } else { |
118 | 185 | TII->copyPhysReg(*MBB, MI, MI->getDebugLoc(), DstSubReg, InsReg, |
119 | 185 | MI->getOperand(2).isKill()); |
120 | 185 | |
121 | 185 | // Implicitly define DstReg for subsequent uses. |
122 | 185 | MachineBasicBlock::iterator CopyMI = MI; |
123 | 185 | --CopyMI; |
124 | 185 | CopyMI->addRegisterDefined(DstReg); |
125 | 185 | DEBUG(dbgs() << "subreg: " << *CopyMI); |
126 | 185 | } |
127 | 204 | |
128 | 185 | DEBUG185 (dbgs() << '\n'); |
129 | 185 | MBB->erase(MI); |
130 | 185 | return true; |
131 | 204 | } |
132 | | |
133 | 3.72M | bool ExpandPostRA::LowerCopy(MachineInstr *MI) { |
134 | 3.72M | |
135 | 3.72M | if (MI->allDefsAreDead()3.72M ) { |
136 | 316 | DEBUG(dbgs() << "dead copy: " << *MI); |
137 | 316 | MI->setDesc(TII->get(TargetOpcode::KILL)); |
138 | 316 | DEBUG(dbgs() << "replaced by: " << *MI); |
139 | 316 | return true; |
140 | 316 | } |
141 | 3.72M | |
142 | 3.72M | MachineOperand &DstMO = MI->getOperand(0); |
143 | 3.72M | MachineOperand &SrcMO = MI->getOperand(1); |
144 | 3.72M | |
145 | 3.72M | bool IdentityCopy = (SrcMO.getReg() == DstMO.getReg()); |
146 | 3.72M | if (IdentityCopy || 3.72M SrcMO.isUndef()3.72M ) { |
147 | 1 | DEBUG(dbgs() << (IdentityCopy ? "identity copy: " : "undef copy: ") << *MI); |
148 | 1 | // No need to insert an identity copy instruction, but replace with a KILL |
149 | 1 | // if liveness is changed. |
150 | 1 | if (SrcMO.isUndef() || 1 MI->getNumOperands() > 20 ) { |
151 | 1 | // We must make sure the super-register gets killed. Replace the |
152 | 1 | // instruction with KILL. |
153 | 1 | MI->setDesc(TII->get(TargetOpcode::KILL)); |
154 | 1 | DEBUG(dbgs() << "replaced by: " << *MI); |
155 | 1 | return true; |
156 | 1 | } |
157 | 0 | // Vanilla identity copy. |
158 | 0 | MI->eraseFromParent(); |
159 | 0 | return true; |
160 | 0 | } |
161 | 3.72M | |
162 | 3.72M | DEBUG3.72M (dbgs() << "real copy: " << *MI); |
163 | 3.72M | TII->copyPhysReg(*MI->getParent(), MI, MI->getDebugLoc(), |
164 | 3.72M | DstMO.getReg(), SrcMO.getReg(), SrcMO.isKill()); |
165 | 3.72M | |
166 | 3.72M | if (MI->getNumOperands() > 2) |
167 | 155k | TransferImplicitOperands(MI); |
168 | 3.72M | DEBUG({ |
169 | 3.72M | MachineBasicBlock::iterator dMI = MI; |
170 | 3.72M | dbgs() << "replaced by: " << *(--dMI); |
171 | 3.72M | }); |
172 | 3.72M | MI->eraseFromParent(); |
173 | 3.72M | return true; |
174 | 3.72M | } |
175 | | |
176 | | /// runOnMachineFunction - Reduce subregister inserts and extracts to register |
177 | | /// copies. |
178 | | /// |
179 | 595k | bool ExpandPostRA::runOnMachineFunction(MachineFunction &MF) { |
180 | 595k | DEBUG(dbgs() << "Machine Function\n" |
181 | 595k | << "********** EXPANDING POST-RA PSEUDO INSTRS **********\n" |
182 | 595k | << "********** Function: " << MF.getName() << '\n'); |
183 | 595k | TRI = MF.getSubtarget().getRegisterInfo(); |
184 | 595k | TII = MF.getSubtarget().getInstrInfo(); |
185 | 595k | |
186 | 595k | bool MadeChange = false; |
187 | 595k | |
188 | 595k | for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end(); |
189 | 4.58M | mbbi != mbbe4.58M ; ++mbbi3.99M ) { |
190 | 3.99M | for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end(); |
191 | 28.1M | mi != me28.1M ;) { |
192 | 24.1M | MachineInstr &MI = *mi; |
193 | 24.1M | // Advance iterator here because MI may be erased. |
194 | 24.1M | ++mi; |
195 | 24.1M | |
196 | 24.1M | // Only expand pseudos. |
197 | 24.1M | if (!MI.isPseudo()) |
198 | 19.6M | continue; |
199 | 4.49M | |
200 | 4.49M | // Give targets a chance to expand even standard pseudos. |
201 | 4.49M | if (4.49M TII->expandPostRAPseudo(MI)4.49M ) { |
202 | 54.7k | MadeChange = true; |
203 | 54.7k | continue; |
204 | 54.7k | } |
205 | 4.44M | |
206 | 4.44M | // Expand standard pseudos. |
207 | 4.44M | switch (MI.getOpcode()) { |
208 | 204 | case TargetOpcode::SUBREG_TO_REG: |
209 | 204 | MadeChange |= LowerSubregToReg(&MI); |
210 | 204 | break; |
211 | 3.72M | case TargetOpcode::COPY: |
212 | 3.72M | MadeChange |= LowerCopy(&MI); |
213 | 3.72M | break; |
214 | 840 | case TargetOpcode::DBG_VALUE: |
215 | 840 | continue; |
216 | 0 | case TargetOpcode::INSERT_SUBREG: |
217 | 0 | case TargetOpcode::EXTRACT_SUBREG: |
218 | 0 | llvm_unreachable("Sub-register pseudos should have been eliminated."); |
219 | 24.1M | } |
220 | 24.1M | } |
221 | 3.99M | } |
222 | 595k | |
223 | 595k | return MadeChange; |
224 | 595k | } |