/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/llvm/lib/CodeGen/LiveRangeEdit.cpp
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1 | | //===-- LiveRangeEdit.cpp - Basic tools for editing a register live range -===// |
2 | | // |
3 | | // The LLVM Compiler Infrastructure |
4 | | // |
5 | | // This file is distributed under the University of Illinois Open Source |
6 | | // License. See LICENSE.TXT for details. |
7 | | // |
8 | | //===----------------------------------------------------------------------===// |
9 | | // |
10 | | // The LiveRangeEdit class represents changes done to a virtual register when it |
11 | | // is spilled or split. |
12 | | //===----------------------------------------------------------------------===// |
13 | | |
14 | | #include "llvm/CodeGen/LiveRangeEdit.h" |
15 | | #include "llvm/ADT/Statistic.h" |
16 | | #include "llvm/CodeGen/CalcSpillWeights.h" |
17 | | #include "llvm/CodeGen/LiveIntervalAnalysis.h" |
18 | | #include "llvm/CodeGen/MachineRegisterInfo.h" |
19 | | #include "llvm/CodeGen/VirtRegMap.h" |
20 | | #include "llvm/Support/Debug.h" |
21 | | #include "llvm/Support/raw_ostream.h" |
22 | | #include "llvm/Target/TargetInstrInfo.h" |
23 | | |
24 | | using namespace llvm; |
25 | | |
26 | | #define DEBUG_TYPE "regalloc" |
27 | | |
28 | | STATISTIC(NumDCEDeleted, "Number of instructions deleted by DCE"); |
29 | | STATISTIC(NumDCEFoldedLoads, "Number of single use loads folded after DCE"); |
30 | | STATISTIC(NumFracRanges, "Number of live ranges fractured by DCE"); |
31 | | |
32 | 0 | void LiveRangeEdit::Delegate::anchor() { } |
33 | | |
34 | 420k | LiveInterval &LiveRangeEdit::createEmptyIntervalFrom(unsigned OldReg) { |
35 | 420k | unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); |
36 | 420k | if (VRM420k ) { |
37 | 420k | VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg)); |
38 | 420k | } |
39 | 420k | LiveInterval &LI = LIS.createEmptyInterval(VReg); |
40 | 420k | if (Parent && 420k !Parent->isSpillable()420k ) |
41 | 0 | LI.markNotSpillable(); |
42 | 420k | // Create empty subranges if the OldReg's interval has them. Do not create |
43 | 420k | // the main range here---it will be constructed later after the subranges |
44 | 420k | // have been finalized. |
45 | 420k | LiveInterval &OldLI = LIS.getInterval(OldReg); |
46 | 420k | VNInfo::Allocator &Alloc = LIS.getVNInfoAllocator(); |
47 | 420k | for (LiveInterval::SubRange &S : OldLI.subranges()) |
48 | 192 | LI.createSubRange(Alloc, S.LaneMask); |
49 | 420k | return LI; |
50 | 420k | } |
51 | | |
52 | 306k | unsigned LiveRangeEdit::createFrom(unsigned OldReg) { |
53 | 306k | unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); |
54 | 306k | if (VRM306k ) { |
55 | 306k | VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg)); |
56 | 306k | } |
57 | 306k | // FIXME: Getting the interval here actually computes it. |
58 | 306k | // In theory, this may not be what we want, but in practice |
59 | 306k | // the createEmptyIntervalFrom API is used when this is not |
60 | 306k | // the case. Generally speaking we just want to annotate the |
61 | 306k | // LiveInterval when it gets created but we cannot do that at |
62 | 306k | // the moment. |
63 | 306k | if (Parent && 306k !Parent->isSpillable()306k ) |
64 | 0 | LIS.getInterval(VReg).markNotSpillable(); |
65 | 306k | return VReg; |
66 | 306k | } |
67 | | |
68 | | bool LiveRangeEdit::checkRematerializable(VNInfo *VNI, |
69 | | const MachineInstr *DefMI, |
70 | 593k | AliasAnalysis *aa) { |
71 | 593k | assert(DefMI && "Missing instruction"); |
72 | 593k | ScannedRemattable = true; |
73 | 593k | if (!TII.isTriviallyReMaterializable(*DefMI, aa)) |
74 | 316k | return false; |
75 | 276k | Remattable.insert(VNI); |
76 | 276k | return true; |
77 | 276k | } |
78 | | |
79 | 530k | void LiveRangeEdit::scanRemattable(AliasAnalysis *aa) { |
80 | 641k | for (VNInfo *VNI : getParent().valnos) { |
81 | 641k | if (VNI->isUnused()) |
82 | 60 | continue; |
83 | 641k | unsigned Original = VRM->getOriginal(getReg()); |
84 | 641k | LiveInterval &OrigLI = LIS.getInterval(Original); |
85 | 641k | VNInfo *OrigVNI = OrigLI.getVNInfoAt(VNI->def); |
86 | 641k | if (!OrigVNI) |
87 | 0 | continue; |
88 | 641k | MachineInstr *DefMI = LIS.getInstructionFromIndex(OrigVNI->def); |
89 | 641k | if (!DefMI) |
90 | 48.2k | continue; |
91 | 593k | checkRematerializable(OrigVNI, DefMI, aa); |
92 | 593k | } |
93 | 530k | ScannedRemattable = true; |
94 | 530k | } |
95 | | |
96 | 530k | bool LiveRangeEdit::anyRematerializable(AliasAnalysis *aa) { |
97 | 530k | if (!ScannedRemattable) |
98 | 530k | scanRemattable(aa); |
99 | 530k | return !Remattable.empty(); |
100 | 530k | } |
101 | | |
102 | | /// allUsesAvailableAt - Return true if all registers used by OrigMI at |
103 | | /// OrigIdx are also available with the same value at UseIdx. |
104 | | bool LiveRangeEdit::allUsesAvailableAt(const MachineInstr *OrigMI, |
105 | | SlotIndex OrigIdx, |
106 | 219k | SlotIndex UseIdx) const { |
107 | 219k | OrigIdx = OrigIdx.getRegSlot(true); |
108 | 219k | UseIdx = UseIdx.getRegSlot(true); |
109 | 819k | for (unsigned i = 0, e = OrigMI->getNumOperands(); i != e819k ; ++i599k ) { |
110 | 599k | const MachineOperand &MO = OrigMI->getOperand(i); |
111 | 599k | if (!MO.isReg() || 599k !MO.getReg()238k || !MO.readsReg()222k ) |
112 | 598k | continue; |
113 | 1.45k | |
114 | 1.45k | // We can't remat physreg uses, unless it is a constant. |
115 | 1.45k | if (1.45k TargetRegisterInfo::isPhysicalRegister(MO.getReg())1.45k ) { |
116 | 843 | if (MRI.isConstantPhysReg(MO.getReg())) |
117 | 843 | continue; |
118 | 0 | return false; |
119 | 0 | } |
120 | 614 | |
121 | 614 | LiveInterval &li = LIS.getInterval(MO.getReg()); |
122 | 614 | const VNInfo *OVNI = li.getVNInfoAt(OrigIdx); |
123 | 614 | if (!OVNI) |
124 | 0 | continue; |
125 | 614 | |
126 | 614 | // Don't allow rematerialization immediately after the original def. |
127 | 614 | // It would be incorrect if OrigMI redefines the register. |
128 | 614 | // See PR14098. |
129 | 614 | if (614 SlotIndex::isSameInstr(OrigIdx, UseIdx)614 ) |
130 | 1 | return false; |
131 | 613 | |
132 | 613 | if (613 OVNI != li.getVNInfoAt(UseIdx)613 ) |
133 | 73 | return false; |
134 | 599k | } |
135 | 219k | return true; |
136 | 219k | } |
137 | | |
138 | | bool LiveRangeEdit::canRematerializeAt(Remat &RM, VNInfo *OrigVNI, |
139 | 581k | SlotIndex UseIdx, bool cheapAsAMove) { |
140 | 581k | assert(ScannedRemattable && "Call anyRematerializable first"); |
141 | 581k | |
142 | 581k | // Use scanRemattable info. |
143 | 581k | if (!Remattable.count(OrigVNI)) |
144 | 292k | return false; |
145 | 289k | |
146 | 289k | // No defining instruction provided. |
147 | 289k | SlotIndex DefIdx; |
148 | 289k | assert(RM.OrigMI && "No defining instruction for remattable value"); |
149 | 289k | DefIdx = LIS.getInstructionIndex(*RM.OrigMI); |
150 | 289k | |
151 | 289k | // If only cheap remats were requested, bail out early. |
152 | 289k | if (cheapAsAMove && 289k !TII.isAsCheapAsAMove(*RM.OrigMI)114k ) |
153 | 69.7k | return false; |
154 | 219k | |
155 | 219k | // Verify that all used registers are available with the same values. |
156 | 219k | if (219k !allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx)219k ) |
157 | 74 | return false; |
158 | 219k | |
159 | 219k | return true; |
160 | 219k | } |
161 | | |
162 | | SlotIndex LiveRangeEdit::rematerializeAt(MachineBasicBlock &MBB, |
163 | | MachineBasicBlock::iterator MI, |
164 | | unsigned DestReg, |
165 | | const Remat &RM, |
166 | | const TargetRegisterInfo &tri, |
167 | 218k | bool Late) { |
168 | 218k | assert(RM.OrigMI && "Invalid remat"); |
169 | 218k | TII.reMaterialize(MBB, MI, DestReg, 0, *RM.OrigMI, tri); |
170 | 218k | // DestReg of the cloned instruction cannot be Dead. Set isDead of DestReg |
171 | 218k | // to false anyway in case the isDead flag of RM.OrigMI's dest register |
172 | 218k | // is true. |
173 | 218k | (*--MI).getOperand(0).setIsDead(false); |
174 | 218k | Rematted.insert(RM.ParentVNI); |
175 | 218k | return LIS.getSlotIndexes()->insertMachineInstrInMaps(*MI, Late).getRegSlot(); |
176 | 218k | } |
177 | | |
178 | 948k | void LiveRangeEdit::eraseVirtReg(unsigned Reg) { |
179 | 948k | if (TheDelegate && 948k TheDelegate->LRE_CanEraseVirtReg(Reg)948k ) |
180 | 501k | LIS.removeInterval(Reg); |
181 | 948k | } |
182 | | |
183 | | bool LiveRangeEdit::foldAsLoad(LiveInterval *LI, |
184 | 50.0k | SmallVectorImpl<MachineInstr*> &Dead) { |
185 | 50.0k | MachineInstr *DefMI = nullptr, *UseMI = nullptr; |
186 | 50.0k | |
187 | 50.0k | // Check that there is a single def and a single use. |
188 | 53.5k | for (MachineOperand &MO : MRI.reg_nodbg_operands(LI->reg)) { |
189 | 53.5k | MachineInstr *MI = MO.getParent(); |
190 | 53.5k | if (MO.isDef()53.5k ) { |
191 | 50.7k | if (DefMI && 50.7k DefMI != MI947 ) |
192 | 947 | return false; |
193 | 49.7k | if (49.7k !MI->canFoldAsLoad()49.7k ) |
194 | 47.0k | return false; |
195 | 2.73k | DefMI = MI; |
196 | 53.5k | } else if (2.86k !MO.isUndef()2.86k ) { |
197 | 2.86k | if (UseMI && 2.86k UseMI != MI1.15k ) |
198 | 1.03k | return false; |
199 | 1.82k | // FIXME: Targets don't know how to fold subreg uses. |
200 | 1.82k | if (1.82k MO.getSubReg()1.82k ) |
201 | 3 | return false; |
202 | 1.82k | UseMI = MI; |
203 | 1.82k | } |
204 | 53.5k | } |
205 | 1.05k | if (1.05k !DefMI || 1.05k !UseMI748 ) |
206 | 388 | return false; |
207 | 669 | |
208 | 669 | // Since we're moving the DefMI load, make sure we're not extending any live |
209 | 669 | // ranges. |
210 | 669 | if (669 !allUsesAvailableAt(DefMI, LIS.getInstructionIndex(*DefMI), |
211 | 669 | LIS.getInstructionIndex(*UseMI))) |
212 | 0 | return false; |
213 | 669 | |
214 | 669 | // We also need to make sure it is safe to move the load. |
215 | 669 | // Assume there are stores between DefMI and UseMI. |
216 | 669 | bool SawStore = true; |
217 | 669 | if (!DefMI->isSafeToMove(nullptr, SawStore)) |
218 | 31 | return false; |
219 | 638 | |
220 | 638 | DEBUG638 (dbgs() << "Try to fold single def: " << *DefMI |
221 | 638 | << " into single use: " << *UseMI); |
222 | 638 | |
223 | 638 | SmallVector<unsigned, 8> Ops; |
224 | 638 | if (UseMI->readsWritesVirtualRegister(LI->reg, &Ops).second) |
225 | 0 | return false; |
226 | 638 | |
227 | 638 | MachineInstr *FoldMI = TII.foldMemoryOperand(*UseMI, Ops, *DefMI, &LIS); |
228 | 638 | if (!FoldMI) |
229 | 478 | return false; |
230 | 160 | DEBUG160 (dbgs() << " folded: " << *FoldMI); |
231 | 160 | LIS.ReplaceMachineInstrInMaps(*UseMI, *FoldMI); |
232 | 160 | UseMI->eraseFromParent(); |
233 | 160 | DefMI->addRegisterDead(LI->reg, nullptr); |
234 | 160 | Dead.push_back(DefMI); |
235 | 160 | ++NumDCEFoldedLoads; |
236 | 160 | return true; |
237 | 160 | } |
238 | | |
239 | | bool LiveRangeEdit::useIsKill(const LiveInterval &LI, |
240 | 18.8k | const MachineOperand &MO) const { |
241 | 18.8k | const MachineInstr &MI = *MO.getParent(); |
242 | 18.8k | SlotIndex Idx = LIS.getInstructionIndex(MI).getRegSlot(); |
243 | 18.8k | if (LI.Query(Idx).isKill()) |
244 | 16.3k | return true; |
245 | 2.47k | const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo(); |
246 | 2.47k | unsigned SubReg = MO.getSubReg(); |
247 | 2.47k | LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubReg); |
248 | 0 | for (const LiveInterval::SubRange &S : LI.subranges()) { |
249 | 0 | if ((S.LaneMask & LaneMask).any() && 0 S.Query(Idx).isKill()0 ) |
250 | 0 | return true; |
251 | 2.47k | } |
252 | 2.47k | return false; |
253 | 2.47k | } |
254 | | |
255 | | /// Find all live intervals that need to shrink, then remove the instruction. |
256 | | void LiveRangeEdit::eliminateDeadDef(MachineInstr *MI, ToShrinkSet &ToShrink, |
257 | 693k | AliasAnalysis *AA) { |
258 | 693k | assert(MI->allDefsAreDead() && "Def isn't really dead"); |
259 | 693k | SlotIndex Idx = LIS.getInstructionIndex(*MI).getRegSlot(); |
260 | 693k | |
261 | 693k | // Never delete a bundled instruction. |
262 | 693k | if (MI->isBundled()693k ) { |
263 | 2 | return; |
264 | 2 | } |
265 | 693k | // Never delete inline asm. |
266 | 693k | if (693k MI->isInlineAsm()693k ) { |
267 | 0 | DEBUG(dbgs() << "Won't delete: " << Idx << '\t' << *MI); |
268 | 0 | return; |
269 | 0 | } |
270 | 693k | |
271 | 693k | // Use the same criteria as DeadMachineInstructionElim. |
272 | 693k | bool SawStore = false; |
273 | 693k | if (!MI->isSafeToMove(nullptr, SawStore)693k ) { |
274 | 0 | DEBUG(dbgs() << "Can't delete: " << Idx << '\t' << *MI); |
275 | 0 | return; |
276 | 0 | } |
277 | 693k | |
278 | 693k | DEBUG693k (dbgs() << "Deleting dead def " << Idx << '\t' << *MI); |
279 | 693k | |
280 | 693k | // Collect virtual registers to be erased after MI is gone. |
281 | 693k | SmallVector<unsigned, 8> RegsToErase; |
282 | 693k | bool ReadsPhysRegs = false; |
283 | 693k | bool isOrigDef = false; |
284 | 693k | unsigned Dest; |
285 | 693k | // Only optimize rematerialize case when the instruction has one def, since |
286 | 693k | // otherwise we could leave some dead defs in the code. This case is |
287 | 693k | // extremely rare. |
288 | 693k | if (VRM && 693k MI->getOperand(0).isReg()199k && MI->getOperand(0).isDef()197k && |
289 | 693k | MI->getDesc().getNumDefs() == 1180k ) { |
290 | 180k | Dest = MI->getOperand(0).getReg(); |
291 | 180k | unsigned Original = VRM->getOriginal(Dest); |
292 | 180k | LiveInterval &OrigLI = LIS.getInterval(Original); |
293 | 180k | VNInfo *OrigVNI = OrigLI.getVNInfoAt(Idx); |
294 | 180k | // The original live-range may have been shrunk to |
295 | 180k | // an empty live-range. It happens when it is dead, but |
296 | 180k | // we still keep it around to be able to rematerialize |
297 | 180k | // other values that depend on it. |
298 | 180k | if (OrigVNI) |
299 | 180k | isOrigDef = SlotIndex::isSameInstr(OrigVNI->def, Idx); |
300 | 180k | } |
301 | 693k | |
302 | 693k | // Check for live intervals that may shrink |
303 | 693k | for (MachineInstr::mop_iterator MOI = MI->operands_begin(), |
304 | 2.35M | MOE = MI->operands_end(); MOI != MOE2.35M ; ++MOI1.66M ) { |
305 | 1.66M | if (!MOI->isReg()) |
306 | 898k | continue; |
307 | 761k | unsigned Reg = MOI->getReg(); |
308 | 761k | if (!TargetRegisterInfo::isVirtualRegister(Reg)761k ) { |
309 | 25.1k | // Check if MI reads any unreserved physregs. |
310 | 25.1k | if (Reg && 25.1k MOI->readsReg()6.60k && !MRI.isReserved(Reg)1.66k ) |
311 | 20 | ReadsPhysRegs = true; |
312 | 25.1k | else if (25.1k MOI->isDef()25.1k ) |
313 | 4.94k | LIS.removePhysRegDefAt(Reg, Idx); |
314 | 25.1k | continue; |
315 | 25.1k | } |
316 | 736k | LiveInterval &LI = LIS.getInterval(Reg); |
317 | 736k | |
318 | 736k | // Shrink read registers, unless it is likely to be expensive and |
319 | 736k | // unlikely to change anything. We typically don't want to shrink the |
320 | 736k | // PIC base register that has lots of uses everywhere. |
321 | 736k | // Always shrink COPY uses that probably come from live range splitting. |
322 | 736k | if ((MI->readsVirtualRegister(Reg) && 736k (MI->isCopy() || 61.3k MOI->isDef()19.0k )) || |
323 | 693k | (MOI->readsReg() && 693k (MRI.hasOneNonDBGUse(Reg) || 19.0k useIsKill(LI, *MOI)18.8k ))) |
324 | 58.8k | ToShrink.insert(&LI); |
325 | 736k | |
326 | 736k | // Remove defined value. |
327 | 736k | if (MOI->isDef()736k ) { |
328 | 674k | if (TheDelegate && 674k LI.getVNInfoAt(Idx) != nullptr674k ) |
329 | 674k | TheDelegate->LRE_WillShrinkVirtReg(LI.reg); |
330 | 674k | LIS.removeVRegDefAt(LI, Idx); |
331 | 674k | if (LI.empty()) |
332 | 659k | RegsToErase.push_back(Reg); |
333 | 674k | } |
334 | 1.66M | } |
335 | 693k | |
336 | 693k | // Currently, we don't support DCE of physreg live ranges. If MI reads |
337 | 693k | // any unreserved physregs, don't erase the instruction, but turn it into |
338 | 693k | // a KILL instead. This way, the physreg live ranges don't end up |
339 | 693k | // dangling. |
340 | 693k | // FIXME: It would be better to have something like shrinkToUses() for |
341 | 693k | // physregs. That could potentially enable more DCE and it would free up |
342 | 693k | // the physreg. It would not happen often, though. |
343 | 693k | if (ReadsPhysRegs693k ) { |
344 | 20 | MI->setDesc(TII.get(TargetOpcode::KILL)); |
345 | 20 | // Remove all operands that aren't physregs. |
346 | 60 | for (unsigned i = MI->getNumOperands(); i60 ; --i40 ) { |
347 | 40 | const MachineOperand &MO = MI->getOperand(i-1); |
348 | 40 | if (MO.isReg() && 40 TargetRegisterInfo::isPhysicalRegister(MO.getReg())40 ) |
349 | 20 | continue; |
350 | 20 | MI->RemoveOperand(i-1); |
351 | 20 | } |
352 | 20 | DEBUG(dbgs() << "Converted physregs to:\t" << *MI); |
353 | 693k | } else { |
354 | 693k | // If the dest of MI is an original reg and MI is reMaterializable, |
355 | 693k | // don't delete the inst. Replace the dest with a new reg, and keep |
356 | 693k | // the inst for remat of other siblings. The inst is saved in |
357 | 693k | // LiveRangeEdit::DeadRemats and will be deleted after all the |
358 | 693k | // allocations of the func are done. |
359 | 693k | if (isOrigDef && 693k DeadRemats123k && TII.isTriviallyReMaterializable(*MI, AA)123k ) { |
360 | 123k | LiveInterval &NewLI = createEmptyIntervalFrom(Dest); |
361 | 123k | NewLI.removeEmptySubRanges(); |
362 | 123k | VNInfo *VNI = NewLI.getNextValue(Idx, LIS.getVNInfoAllocator()); |
363 | 123k | NewLI.addSegment(LiveInterval::Segment(Idx, Idx.getDeadSlot(), VNI)); |
364 | 123k | pop_back(); |
365 | 123k | markDeadRemat(MI); |
366 | 123k | const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo(); |
367 | 123k | MI->substituteRegister(Dest, NewLI.reg, 0, TRI); |
368 | 123k | MI->getOperand(0).setIsDead(true); |
369 | 693k | } else { |
370 | 570k | if (TheDelegate) |
371 | 570k | TheDelegate->LRE_WillEraseInstruction(MI); |
372 | 570k | LIS.RemoveMachineInstrFromMaps(*MI); |
373 | 570k | MI->eraseFromParent(); |
374 | 570k | ++NumDCEDeleted; |
375 | 570k | } |
376 | 693k | } |
377 | 693k | |
378 | 693k | // Erase any virtregs that are now empty and unused. There may be <undef> |
379 | 693k | // uses around. Keep the empty live range in that case. |
380 | 1.35M | for (unsigned i = 0, e = RegsToErase.size(); i != e1.35M ; ++i659k ) { |
381 | 659k | unsigned Reg = RegsToErase[i]; |
382 | 659k | if (LIS.hasInterval(Reg) && 659k MRI.reg_nodbg_empty(Reg)659k ) { |
383 | 659k | ToShrink.remove(&LIS.getInterval(Reg)); |
384 | 659k | eraseVirtReg(Reg); |
385 | 659k | } |
386 | 659k | } |
387 | 693k | } |
388 | | |
389 | | void LiveRangeEdit::eliminateDeadDefs(SmallVectorImpl<MachineInstr *> &Dead, |
390 | | ArrayRef<unsigned> RegsBeingSpilled, |
391 | 791k | AliasAnalysis *AA) { |
392 | 791k | ToShrinkSet ToShrink; |
393 | 791k | |
394 | 841k | for (;;) { |
395 | 841k | // Erase all dead defs. |
396 | 1.53M | while (!Dead.empty()) |
397 | 693k | eliminateDeadDef(Dead.pop_back_val(), ToShrink, AA); |
398 | 841k | |
399 | 841k | if (ToShrink.empty()) |
400 | 791k | break; |
401 | 50.0k | |
402 | 50.0k | // Shrink just one live interval. Then delete new dead defs. |
403 | 50.0k | LiveInterval *LI = ToShrink.back(); |
404 | 50.0k | ToShrink.pop_back(); |
405 | 50.0k | if (foldAsLoad(LI, Dead)) |
406 | 160 | continue; |
407 | 49.9k | unsigned VReg = LI->reg; |
408 | 49.9k | if (TheDelegate) |
409 | 49.9k | TheDelegate->LRE_WillShrinkVirtReg(VReg); |
410 | 49.9k | if (!LIS.shrinkToUses(LI, &Dead)) |
411 | 45.9k | continue; |
412 | 3.90k | |
413 | 3.90k | // Don't create new intervals for a register being spilled. |
414 | 3.90k | // The new intervals would have to be spilled anyway so its not worth it. |
415 | 3.90k | // Also they currently aren't spilled so creating them and not spilling |
416 | 3.90k | // them results in incorrect code. |
417 | 3.90k | bool BeingSpilled = false; |
418 | 4.29k | for (unsigned i = 0, e = RegsBeingSpilled.size(); i != e4.29k ; ++i391 ) { |
419 | 395 | if (VReg == RegsBeingSpilled[i]395 ) { |
420 | 4 | BeingSpilled = true; |
421 | 4 | break; |
422 | 4 | } |
423 | 395 | } |
424 | 3.90k | |
425 | 3.90k | if (BeingSpilled3.90k ) continue4 ; |
426 | 3.90k | |
427 | 3.90k | // LI may have been separated, create new intervals. |
428 | 3.90k | LI->RenumberValues(); |
429 | 3.90k | SmallVector<LiveInterval*, 8> SplitLIs; |
430 | 3.90k | LIS.splitSeparateComponents(*LI, SplitLIs); |
431 | 3.90k | if (!SplitLIs.empty()) |
432 | 3.75k | ++NumFracRanges; |
433 | 3.90k | |
434 | 3.90k | unsigned Original = VRM ? VRM->getOriginal(VReg)3.89k : 05 ; |
435 | 4.37k | for (const LiveInterval *SplitLI : SplitLIs) { |
436 | 4.37k | // If LI is an original interval that hasn't been split yet, make the new |
437 | 4.37k | // intervals their own originals instead of referring to LI. The original |
438 | 4.37k | // interval must contain all the split products, and LI doesn't. |
439 | 4.37k | if (Original != VReg && 4.37k Original != 04.37k ) |
440 | 4.36k | VRM->setIsSplitFromReg(SplitLI->reg, Original); |
441 | 4.37k | if (TheDelegate) |
442 | 4.37k | TheDelegate->LRE_DidCloneVirtReg(SplitLI->reg, VReg); |
443 | 4.37k | } |
444 | 841k | } |
445 | 791k | } |
446 | | |
447 | | // Keep track of new virtual registers created via |
448 | | // MachineRegisterInfo::createVirtualRegister. |
449 | | void |
450 | | LiveRangeEdit::MRI_NoteNewVirtualRegister(unsigned VReg) |
451 | 771k | { |
452 | 771k | if (VRM) |
453 | 771k | VRM->grow(); |
454 | 771k | |
455 | 771k | NewRegs.push_back(VReg); |
456 | 771k | } |
457 | | |
458 | | void |
459 | | LiveRangeEdit::calculateRegClassAndHint(MachineFunction &MF, |
460 | | const MachineLoopInfo &Loops, |
461 | 410k | const MachineBlockFrequencyInfo &MBFI) { |
462 | 410k | VirtRegAuxInfo VRAI(MF, LIS, VRM, Loops, MBFI); |
463 | 1.05M | for (unsigned I = 0, Size = size(); I < Size1.05M ; ++I644k ) { |
464 | 644k | LiveInterval &LI = LIS.getInterval(get(I)); |
465 | 644k | if (MRI.recomputeRegClass(LI.reg)) |
466 | 644k | DEBUG({ |
467 | 644k | const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); |
468 | 644k | dbgs() << "Inflated " << PrintReg(LI.reg) << " to " |
469 | 644k | << TRI->getRegClassName(MRI.getRegClass(LI.reg)) << '\n'; |
470 | 644k | }); |
471 | 644k | VRAI.calculateSpillWeightAndHint(LI); |
472 | 644k | } |
473 | 410k | } |