/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/llvm/lib/Target/AMDGPU/AMDGPURegisterInfo.cpp
Line | Count | Source (jump to first uncovered line) |
1 | | //===-- AMDGPURegisterInfo.cpp - AMDGPU Register Information -------------===// |
2 | | // |
3 | | // The LLVM Compiler Infrastructure |
4 | | // |
5 | | // This file is distributed under the University of Illinois Open Source |
6 | | // License. See LICENSE.TXT for details. |
7 | | // |
8 | | //===----------------------------------------------------------------------===// |
9 | | // |
10 | | /// \file |
11 | | /// \brief Parent TargetRegisterInfo class common to all hw codegen targets. |
12 | | // |
13 | | //===----------------------------------------------------------------------===// |
14 | | |
15 | | #include "AMDGPURegisterInfo.h" |
16 | | #include "AMDGPUTargetMachine.h" |
17 | | #include "SIRegisterInfo.h" |
18 | | |
19 | | using namespace llvm; |
20 | | |
21 | 2.06k | AMDGPURegisterInfo::AMDGPURegisterInfo() : AMDGPUGenRegisterInfo(0) {} |
22 | | |
23 | | //===----------------------------------------------------------------------===// |
24 | | // Function handling callbacks - Functions are a seldom used feature of GPUS, so |
25 | | // they are not supported at this time. |
26 | | //===----------------------------------------------------------------------===// |
27 | | |
28 | 63.1k | unsigned AMDGPURegisterInfo::getSubRegFromChannel(unsigned Channel) const { |
29 | 63.1k | static const unsigned SubRegs[] = { |
30 | 63.1k | AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, AMDGPU::sub4, |
31 | 63.1k | AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, AMDGPU::sub8, AMDGPU::sub9, |
32 | 63.1k | AMDGPU::sub10, AMDGPU::sub11, AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, |
33 | 63.1k | AMDGPU::sub15 |
34 | 63.1k | }; |
35 | 63.1k | |
36 | 63.1k | assert(Channel < array_lengthof(SubRegs)); |
37 | 63.1k | return SubRegs[Channel]; |
38 | 63.1k | } |
39 | | |
40 | | #define GET_REGINFO_TARGET_DESC |
41 | | #include "AMDGPUGenRegisterInfo.inc" |
42 | | |
43 | | // Forced to be here by one .inc |
44 | | const MCPhysReg *SIRegisterInfo::getCalleeSavedRegs( |
45 | 336k | const MachineFunction *MF) const { |
46 | 336k | CallingConv::ID CC = MF->getFunction()->getCallingConv(); |
47 | 336k | switch (CC) { |
48 | 19.4k | case CallingConv::C: |
49 | 19.4k | case CallingConv::Fast: |
50 | 19.4k | case CallingConv::Cold: |
51 | 19.4k | return CSR_AMDGPU_HighRegs_SaveList; |
52 | 316k | default: { |
53 | 316k | // Dummy to not crash RegisterClassInfo. |
54 | 316k | static const MCPhysReg NoCalleeSavedReg = AMDGPU::NoRegister; |
55 | 316k | return &NoCalleeSavedReg; |
56 | 0 | } |
57 | 336k | } |
58 | 336k | } |
59 | | |
60 | | const MCPhysReg * |
61 | 1.69k | SIRegisterInfo::getCalleeSavedRegsViaCopy(const MachineFunction *MF) const { |
62 | 1.69k | return nullptr; |
63 | 1.69k | } |
64 | | |
65 | | const uint32_t *SIRegisterInfo::getCallPreservedMask(const MachineFunction &MF, |
66 | 506 | CallingConv::ID CC) const { |
67 | 506 | switch (CC) { |
68 | 501 | case CallingConv::C: |
69 | 501 | case CallingConv::Fast: |
70 | 501 | case CallingConv::Cold: |
71 | 501 | return CSR_AMDGPU_HighRegs_RegMask; |
72 | 5 | default: |
73 | 5 | return nullptr; |
74 | 0 | } |
75 | 0 | } |
76 | | |
77 | 97 | unsigned SIRegisterInfo::getFrameRegister(const MachineFunction &MF) const { |
78 | 97 | return AMDGPU::NoRegister; |
79 | 97 | } |