Coverage Report

Created: 2017-10-03 07:32

/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
Line
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Source
1
//===-- ARMBaseRegisterInfo.h - ARM Register Information Impl ---*- C++ -*-===//
2
//
3
//                     The LLVM Compiler Infrastructure
4
//
5
// This file is distributed under the University of Illinois Open Source
6
// License. See LICENSE.TXT for details.
7
//
8
//===----------------------------------------------------------------------===//
9
//
10
// This file contains the base ARM implementation of TargetRegisterInfo class.
11
//
12
//===----------------------------------------------------------------------===//
13
14
#ifndef LLVM_LIB_TARGET_ARM_ARMBASEREGISTERINFO_H
15
#define LLVM_LIB_TARGET_ARM_ARMBASEREGISTERINFO_H
16
17
#include "MCTargetDesc/ARMBaseInfo.h"
18
#include "llvm/CodeGen/MachineBasicBlock.h"
19
#include "llvm/CodeGen/MachineInstr.h"
20
#include "llvm/IR/CallingConv.h"
21
#include "llvm/MC/MCRegisterInfo.h"
22
#include "llvm/Target/TargetRegisterInfo.h"
23
#include <cstdint>
24
25
#define GET_REGINFO_HEADER
26
#include "ARMGenRegisterInfo.inc"
27
28
namespace llvm {
29
30
/// Register allocation hints.
31
namespace ARMRI {
32
33
  enum {
34
    RegPairOdd  = 1,
35
    RegPairEven = 2
36
  };
37
38
} // end namespace ARMRI
39
40
/// isARMArea1Register - Returns true if the register is a low register (r0-r7)
41
/// or a stack/pc register that we should push/pop.
42
50.5k
static inline bool isARMArea1Register(unsigned Reg, bool isIOS) {
43
50.5k
  using namespace ARM;
44
50.5k
45
50.5k
  switch (Reg) {
46
38.2k
    
case R0: 38.2k
case R1: 38.2k
case R2: 38.2k
case R3:
47
38.2k
    
case R4: 38.2k
case R5: 38.2k
case R6: 38.2k
case R7:
48
38.2k
    
case LR: 38.2k
case SP: 38.2k
case PC:
49
38.2k
      return true;
50
9.29k
    
case R8: 9.29k
case R9: 9.29k
case R10: 9.29k
case R11: 9.29k
case R12:
51
9.29k
      // For iOS we want r7 and lr to be next to each other.
52
9.29k
      return !isIOS;
53
2.92k
    default:
54
2.92k
      return false;
55
50.5k
  }
56
50.5k
}
Unexecuted instantiation: A15SDOptimizer.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: ARMTargetStreamer.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: ARMELFStreamer.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: ARMInstPrinter.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: Thumb2SizeReduction.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: Thumb2InstrInfo.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: Thumb2ITBlockPass.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: ThumbRegisterInfo.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: Thumb1InstrInfo.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: Thumb1FrameLowering.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: MLxExpansionPass.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: ARMTargetTransformInfo.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: ARMTargetObjectFile.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: ARMTargetMachine.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: ARMSubtarget.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: ARMSelectionDAGInfo.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: ARMRegisterBankInfo.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: ARMOptimizeBarriersPass.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: ARMRegisterInfo.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: ARMMacroFusion.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: ARMMachineFunctionInfo.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: ARMMCInstLower.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: ARMLoadStoreOptimizer.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: ARMLegalizerInfo.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: ARMInstrInfo.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: ARMISelLowering.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: ARMISelDAGToDAG.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: ARMInstructionSelector.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: ARMHazardRecognizer.cpp:llvm::isARMArea1Register(unsigned int, bool)
ARMFrameLowering.cpp:llvm::isARMArea1Register(unsigned int, bool)
Line
Count
Source
42
50.5k
static inline bool isARMArea1Register(unsigned Reg, bool isIOS) {
43
50.5k
  using namespace ARM;
44
50.5k
45
50.5k
  switch (Reg) {
46
38.2k
    
case R0: 38.2k
case R1: 38.2k
case R2: 38.2k
case R3:
47
38.2k
    
case R4: 38.2k
case R5: 38.2k
case R6: 38.2k
case R7:
48
38.2k
    
case LR: 38.2k
case SP: 38.2k
case PC:
49
38.2k
      return true;
50
9.29k
    
case R8: 9.29k
case R9: 9.29k
case R10: 9.29k
case R11: 9.29k
case R12:
51
9.29k
      // For iOS we want r7 and lr to be next to each other.
52
9.29k
      return !isIOS;
53
2.92k
    default:
54
2.92k
      return false;
55
50.5k
  }
56
50.5k
}
Unexecuted instantiation: ARMFastISel.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: ARMExpandPseudoInsts.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: ARMConstantIslandPass.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: ARMCallLowering.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: ARMBaseRegisterInfo.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: ARMBaseInstrInfo.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: ARMAsmPrinter.cpp:llvm::isARMArea1Register(unsigned int, bool)
57
58
50.5k
static inline bool isARMArea2Register(unsigned Reg, bool isIOS) {
59
50.5k
  using namespace ARM;
60
50.5k
61
50.5k
  switch (Reg) {
62
9.29k
    
case R8: 9.29k
case R9: 9.29k
case R10: 9.29k
case R11: 9.29k
case R12:
63
9.29k
      // iOS has this second area.
64
9.29k
      return isIOS;
65
41.2k
    default:
66
41.2k
      return false;
67
50.5k
  }
68
50.5k
}
Unexecuted instantiation: A15SDOptimizer.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: ARMMacroFusion.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: ARMAsmPrinter.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: ARMBaseInstrInfo.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: ARMBaseRegisterInfo.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: ARMCallLowering.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: ARMConstantIslandPass.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: ARMExpandPseudoInsts.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: ARMFastISel.cpp:llvm::isARMArea2Register(unsigned int, bool)
ARMFrameLowering.cpp:llvm::isARMArea2Register(unsigned int, bool)
Line
Count
Source
58
50.5k
static inline bool isARMArea2Register(unsigned Reg, bool isIOS) {
59
50.5k
  using namespace ARM;
60
50.5k
61
50.5k
  switch (Reg) {
62
9.29k
    
case R8: 9.29k
case R9: 9.29k
case R10: 9.29k
case R11: 9.29k
case R12:
63
9.29k
      // iOS has this second area.
64
9.29k
      return isIOS;
65
41.2k
    default:
66
41.2k
      return false;
67
50.5k
  }
68
50.5k
}
Unexecuted instantiation: ARMHazardRecognizer.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: ARMInstructionSelector.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: ARMISelDAGToDAG.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: ARMISelLowering.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: ARMInstrInfo.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: ARMLegalizerInfo.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: ARMLoadStoreOptimizer.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: ARMMCInstLower.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: ARMMachineFunctionInfo.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: ARMRegisterInfo.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: ARMOptimizeBarriersPass.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: ARMRegisterBankInfo.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: ARMSelectionDAGInfo.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: ARMSubtarget.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: ARMTargetMachine.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: ARMTargetObjectFile.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: ARMTargetTransformInfo.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: MLxExpansionPass.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: Thumb1FrameLowering.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: Thumb1InstrInfo.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: ThumbRegisterInfo.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: Thumb2ITBlockPass.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: Thumb2InstrInfo.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: Thumb2SizeReduction.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: ARMInstPrinter.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: ARMELFStreamer.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: ARMTargetStreamer.cpp:llvm::isARMArea2Register(unsigned int, bool)
69
70
50.5k
static inline bool isARMArea3Register(unsigned Reg, bool isIOS) {
71
50.5k
  using namespace ARM;
72
50.5k
73
50.5k
  switch (Reg) {
74
2.97k
    
case D15: 2.97k
case D14: 2.97k
case D13: 2.97k
case D12:
75
2.97k
    
case D11: 2.97k
case D10: 2.97k
case D9: 2.97k
case D8:
76
2.97k
    
case D7: 2.97k
case D6: 2.97k
case D5: 2.97k
case D4:
77
2.97k
    
case D3: 2.97k
case D2: 2.97k
case D1: 2.97k
case D0:
78
2.97k
    
case D31: 2.97k
case D30: 2.97k
case D29: 2.97k
case D28:
79
2.97k
    
case D27: 2.97k
case D26: 2.97k
case D25: 2.97k
case D24:
80
2.97k
    
case D23: 2.97k
case D22: 2.97k
case D21: 2.97k
case D20:
81
2.97k
    
case D19: 2.97k
case D18: 2.97k
case D17: 2.97k
case D16:
82
2.97k
      return true;
83
47.5k
    default:
84
47.5k
      return false;
85
50.5k
  }
86
50.5k
}
Unexecuted instantiation: ARMTargetStreamer.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: A15SDOptimizer.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: ARMELFStreamer.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: ARMInstPrinter.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: Thumb2SizeReduction.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: Thumb2InstrInfo.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: Thumb2ITBlockPass.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: ThumbRegisterInfo.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: Thumb1InstrInfo.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: Thumb1FrameLowering.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: MLxExpansionPass.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: ARMTargetTransformInfo.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: ARMTargetObjectFile.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: ARMTargetMachine.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: ARMSubtarget.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: ARMSelectionDAGInfo.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: ARMRegisterBankInfo.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: ARMOptimizeBarriersPass.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: ARMRegisterInfo.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: ARMMacroFusion.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: ARMMachineFunctionInfo.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: ARMMCInstLower.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: ARMLoadStoreOptimizer.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: ARMLegalizerInfo.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: ARMInstrInfo.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: ARMISelLowering.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: ARMISelDAGToDAG.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: ARMInstructionSelector.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: ARMHazardRecognizer.cpp:llvm::isARMArea3Register(unsigned int, bool)
ARMFrameLowering.cpp:llvm::isARMArea3Register(unsigned int, bool)
Line
Count
Source
70
50.5k
static inline bool isARMArea3Register(unsigned Reg, bool isIOS) {
71
50.5k
  using namespace ARM;
72
50.5k
73
50.5k
  switch (Reg) {
74
2.97k
    
case D15: 2.97k
case D14: 2.97k
case D13: 2.97k
case D12:
75
2.97k
    
case D11: 2.97k
case D10: 2.97k
case D9: 2.97k
case D8:
76
2.97k
    
case D7: 2.97k
case D6: 2.97k
case D5: 2.97k
case D4:
77
2.97k
    
case D3: 2.97k
case D2: 2.97k
case D1: 2.97k
case D0:
78
2.97k
    
case D31: 2.97k
case D30: 2.97k
case D29: 2.97k
case D28:
79
2.97k
    
case D27: 2.97k
case D26: 2.97k
case D25: 2.97k
case D24:
80
2.97k
    
case D23: 2.97k
case D22: 2.97k
case D21: 2.97k
case D20:
81
2.97k
    
case D19: 2.97k
case D18: 2.97k
case D17: 2.97k
case D16:
82
2.97k
      return true;
83
47.5k
    default:
84
47.5k
      return false;
85
50.5k
  }
86
50.5k
}
Unexecuted instantiation: ARMFastISel.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: ARMExpandPseudoInsts.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: ARMConstantIslandPass.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: ARMCallLowering.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: ARMBaseRegisterInfo.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: ARMBaseInstrInfo.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: ARMAsmPrinter.cpp:llvm::isARMArea3Register(unsigned int, bool)
87
88
static inline bool isCalleeSavedRegister(unsigned Reg,
89
6.41k
                                         const MCPhysReg *CSRegs) {
90
46.9k
  for (unsigned i = 0; 
CSRegs[i]46.9k
;
++i40.5k
)
91
46.6k
    
if (46.6k
Reg == CSRegs[i]46.6k
)
92
6.09k
      return true;
93
324
  return false;
94
6.41k
}
Unexecuted instantiation: ARMTargetStreamer.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
ARMBaseInstrInfo.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Line
Count
Source
89
431
                                         const MCPhysReg *CSRegs) {
90
5.92k
  for (unsigned i = 0; 
CSRegs[i]5.92k
;
++i5.49k
)
91
5.61k
    
if (5.61k
Reg == CSRegs[i]5.61k
)
92
125
      return true;
93
306
  return false;
94
431
}
Unexecuted instantiation: ARMBaseRegisterInfo.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Unexecuted instantiation: ARMCallLowering.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Unexecuted instantiation: ARMConstantIslandPass.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Unexecuted instantiation: ARMExpandPseudoInsts.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Unexecuted instantiation: ARMFastISel.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
ARMFrameLowering.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Line
Count
Source
89
5.96k
                                         const MCPhysReg *CSRegs) {
90
40.7k
  for (unsigned i = 0; 
CSRegs[i]40.7k
;
++i34.7k
)
91
40.7k
    
if (40.7k
Reg == CSRegs[i]40.7k
)
92
5.96k
      return true;
93
0
  return false;
94
5.96k
}
Unexecuted instantiation: ARMHazardRecognizer.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Unexecuted instantiation: ARMInstructionSelector.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Unexecuted instantiation: ARMISelDAGToDAG.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Unexecuted instantiation: ARMISelLowering.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Unexecuted instantiation: ARMInstrInfo.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Unexecuted instantiation: ARMLegalizerInfo.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Unexecuted instantiation: ARMLoadStoreOptimizer.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Unexecuted instantiation: ARMMCInstLower.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Unexecuted instantiation: ARMMachineFunctionInfo.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Unexecuted instantiation: ARMMacroFusion.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Unexecuted instantiation: A15SDOptimizer.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Unexecuted instantiation: ARMRegisterInfo.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Unexecuted instantiation: ARMOptimizeBarriersPass.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Unexecuted instantiation: ARMRegisterBankInfo.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Unexecuted instantiation: ARMSelectionDAGInfo.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Unexecuted instantiation: ARMSubtarget.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Unexecuted instantiation: ARMTargetMachine.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Unexecuted instantiation: ARMTargetObjectFile.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Unexecuted instantiation: ARMTargetTransformInfo.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Unexecuted instantiation: MLxExpansionPass.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Thumb1FrameLowering.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Line
Count
Source
89
18
                                         const MCPhysReg *CSRegs) {
90
324
  for (unsigned i = 0; 
CSRegs[i]324
;
++i306
)
91
306
    
if (306
Reg == CSRegs[i]306
)
92
0
      return true;
93
18
  return false;
94
18
}
Unexecuted instantiation: Thumb1InstrInfo.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Unexecuted instantiation: ThumbRegisterInfo.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Unexecuted instantiation: Thumb2ITBlockPass.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Unexecuted instantiation: Thumb2InstrInfo.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Unexecuted instantiation: Thumb2SizeReduction.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Unexecuted instantiation: ARMInstPrinter.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Unexecuted instantiation: ARMELFStreamer.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Unexecuted instantiation: ARMAsmPrinter.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
95
96
class ARMBaseRegisterInfo : public ARMGenRegisterInfo {
97
protected:
98
  /// BasePtr - ARM physical register used as a base ptr in complex stack
99
  /// frames. I.e., when we need a 3rd base, not just SP and FP, due to
100
  /// variable size stack objects.
101
  unsigned BasePtr = ARM::R6;
102
103
  // Can be only subclassed.
104
  explicit ARMBaseRegisterInfo();
105
106
  // Return the opcode that implements 'Op', or 0 if no opcode
107
  unsigned getOpcode(int Op) const;
108
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public:
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  /// Code Generation virtual methods...
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  const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
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  const MCPhysReg *
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  getCalleeSavedRegsViaCopy(const MachineFunction *MF) const;
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  const uint32_t *getCallPreservedMask(const MachineFunction &MF,
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                                       CallingConv::ID) const override;
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  const uint32_t *getNoPreservedMask() const override;
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  const uint32_t *getTLSCallPreservedMask(const MachineFunction &MF) const;
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  const uint32_t *getSjLjDispatchPreservedMask(const MachineFunction &MF) const;
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  /// getThisReturnPreservedMask - Returns a call preserved mask specific to the
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  /// case that 'returned' is on an i32 first argument if the calling convention
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  /// is one that can (partially) model this attribute with a preserved mask
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  /// (i.e. it is a calling convention that uses the same register for the first
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  /// i32 argument and an i32 return value)
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  ///
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  /// Should return NULL in the case that the calling convention does not have
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  /// this property
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  const uint32_t *getThisReturnPreservedMask(const MachineFunction &MF,
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                                             CallingConv::ID) const;
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  BitVector getReservedRegs(const MachineFunction &MF) const override;
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  const TargetRegisterClass *
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  getPointerRegClass(const MachineFunction &MF,
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                     unsigned Kind = 0) const override;
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  const TargetRegisterClass *
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  getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
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  const TargetRegisterClass *
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  getLargestLegalSuperClass(const TargetRegisterClass *RC,
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                            const MachineFunction &MF) const override;
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  unsigned getRegPressureLimit(const TargetRegisterClass *RC,
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                               MachineFunction &MF) const override;
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  void getRegAllocationHints(unsigned VirtReg,
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                             ArrayRef<MCPhysReg> Order,
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                             SmallVectorImpl<MCPhysReg> &Hints,
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                             const MachineFunction &MF,
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                             const VirtRegMap *VRM,
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                             const LiveRegMatrix *Matrix) const override;
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  void updateRegAllocHint(unsigned Reg, unsigned NewReg,
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                          MachineFunction &MF) const override;
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  bool hasBasePointer(const MachineFunction &MF) const;
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  bool canRealignStack(const MachineFunction &MF) const override;
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  int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
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                                   int Idx) const override;
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  bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
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  void materializeFrameBaseRegister(MachineBasicBlock *MBB,
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                                    unsigned BaseReg, int FrameIdx,
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                                    int64_t Offset) const override;
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  void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
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                         int64_t Offset) const override;
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  bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
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                          int64_t Offset) const override;
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  bool cannotEliminateFrame(const MachineFunction &MF) const;
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  // Debug information queries.
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  unsigned getFrameRegister(const MachineFunction &MF) const override;
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1.57k
  unsigned getBaseRegister() const { return BasePtr; }
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  bool isLowRegister(unsigned Reg) const;
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  /// emitLoadConstPool - Emits a load from constpool to materialize the
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  /// specified immediate.
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  virtual void
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  emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
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                    const DebugLoc &dl, unsigned DestReg, unsigned SubIdx,
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                    int Val, ARMCC::CondCodes Pred = ARMCC::AL,
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                    unsigned PredReg = 0,
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                    unsigned MIFlags = MachineInstr::NoFlags) const;
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  /// Code Generation virtual methods...
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  bool requiresRegisterScavenging(const MachineFunction &MF) const override;
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  bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override;
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  bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
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  bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override;
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  void eliminateFrameIndex(MachineBasicBlock::iterator II,
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                           int SPAdj, unsigned FIOperandNum,
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                           RegScavenger *RS = nullptr) const override;
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  /// \brief SrcRC and DstRC will be morphed into NewRC if this returns true
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  bool shouldCoalesce(MachineInstr *MI,
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                      const TargetRegisterClass *SrcRC,
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                      unsigned SubReg,
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                      const TargetRegisterClass *DstRC,
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                      unsigned DstSubReg,
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                      const TargetRegisterClass *NewRC) const override;
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_ARM_ARMBASEREGISTERINFO_H