Coverage Report

Created: 2017-10-03 07:32

/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/llvm/lib/Target/ARM/ARMSubtarget.h
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//===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===//
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//
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//                     The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the ARM specific subclass of TargetSubtargetInfo.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
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#define LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
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#include "ARMBaseInstrInfo.h"
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#include "ARMBaseRegisterInfo.h"
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#include "ARMConstantPoolValue.h"
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#include "ARMFrameLowering.h"
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#include "ARMISelLowering.h"
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#include "ARMSelectionDAGInfo.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/CodeGen/GlobalISel/CallLowering.h"
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#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
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#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
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#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/MC/MCInstrItineraries.h"
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#include "llvm/MC/MCSchedule.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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#include <memory>
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#include <string>
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#define GET_SUBTARGETINFO_HEADER
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#include "ARMGenSubtargetInfo.inc"
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namespace llvm {
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class ARMBaseTargetMachine;
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class GlobalValue;
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class StringRef;
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class ARMSubtarget : public ARMGenSubtargetInfo {
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protected:
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  enum ARMProcFamilyEnum {
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    Others,
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    CortexA12,
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    CortexA15,
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    CortexA17,
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    CortexA32,
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    CortexA35,
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    CortexA5,
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    CortexA53,
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    CortexA55,
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    CortexA57,
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    CortexA7,
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    CortexA72,
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    CortexA73,
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    CortexA75,
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    CortexA8,
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    CortexA9,
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    CortexM3,
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    CortexR4,
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    CortexR4F,
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    CortexR5,
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    CortexR52,
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    CortexR7,
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    ExynosM1,
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    Krait,
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    Kryo,
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    Swift
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  };
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  enum ARMProcClassEnum {
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    None,
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    AClass,
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    MClass,
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    RClass
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  };
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  enum ARMArchEnum {
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    ARMv2,
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    ARMv2a,
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    ARMv3,
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    ARMv3m,
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    ARMv4,
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    ARMv4t,
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    ARMv5,
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    ARMv5t,
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    ARMv5te,
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    ARMv5tej,
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    ARMv6,
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    ARMv6k,
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    ARMv6kz,
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    ARMv6m,
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    ARMv6sm,
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    ARMv6t2,
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    ARMv7a,
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    ARMv7em,
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    ARMv7m,
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    ARMv7r,
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    ARMv7ve,
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    ARMv81a,
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    ARMv82a,
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    ARMv83a,
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    ARMv8a,
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    ARMv8mBaseline,
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    ARMv8mMainline,
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    ARMv8r
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  };
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public:
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  /// What kind of timing do load multiple/store multiple instructions have.
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  enum ARMLdStMultipleTiming {
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    /// Can load/store 2 registers/cycle.
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    DoubleIssue,
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    /// Can load/store 2 registers/cycle, but needs an extra cycle if the access
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    /// is not 64-bit aligned.
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    DoubleIssueCheckUnalignedAccess,
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    /// Can load/store 1 register/cycle.
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    SingleIssue,
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    /// Can load/store 1 register/cycle, but needs an extra cycle for address
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    /// computation and potentially also for register writeback.
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    SingleIssuePlusExtras,
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  };
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protected:
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  /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
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  ARMProcFamilyEnum ARMProcFamily = Others;
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  /// ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
134
  ARMProcClassEnum ARMProcClass = None;
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136
  /// ARMArch - ARM architecture
137
  ARMArchEnum ARMArch = ARMv4t;
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  /// HasV4TOps, HasV5TOps, HasV5TEOps,
140
  /// HasV6Ops, HasV6MOps, HasV6KOps, HasV6T2Ops, HasV7Ops, HasV8Ops -
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  /// Specify whether target support specific ARM ISA variants.
142
  bool HasV4TOps = false;
143
  bool HasV5TOps = false;
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  bool HasV5TEOps = false;
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  bool HasV6Ops = false;
146
  bool HasV6MOps = false;
147
  bool HasV6KOps = false;
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  bool HasV6T2Ops = false;
149
  bool HasV7Ops = false;
150
  bool HasV8Ops = false;
151
  bool HasV8_1aOps = false;
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  bool HasV8_2aOps = false;
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  bool HasV8_3aOps = false;
154
  bool HasV8MBaselineOps = false;
155
  bool HasV8MMainlineOps = false;
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  /// HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what
158
  /// floating point ISAs are supported.
159
  bool HasVFPv2 = false;
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  bool HasVFPv3 = false;
161
  bool HasVFPv4 = false;
162
  bool HasFPARMv8 = false;
163
  bool HasNEON = false;
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  /// HasDotProd - True if the ARMv8.2A dot product instructions are supported.
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  bool HasDotProd = false;
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  /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
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  /// specified. Use the method useNEONForSinglePrecisionFP() to
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  /// determine if NEON should actually be used.
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  bool UseNEONForSinglePrecisionFP = false;
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  /// UseMulOps - True if non-microcoded fused integer multiply-add and
174
  /// multiply-subtract instructions should be used.
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  bool UseMulOps = false;
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  /// SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates
178
  /// whether the FP VML[AS] instructions are slow (if so, don't use them).
179
  bool SlowFPVMLx = false;
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  /// HasVMLxForwarding - If true, NEON has special multiplier accumulator
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  /// forwarding to allow mul + mla being issued back to back.
183
  bool HasVMLxForwarding = false;
184
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  /// SlowFPBrcc - True if floating point compare + branch is slow.
186
  bool SlowFPBrcc = false;
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  /// InThumbMode - True if compiling for Thumb, false for ARM.
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  bool InThumbMode = false;
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  /// UseSoftFloat - True if we're using software floating point features.
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  bool UseSoftFloat = false;
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  /// UseMISched - True if MachineScheduler should be used for this subtarget.
195
  bool UseMISched = false;
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  /// DisablePostRAScheduler - False if scheduling should happen again after
198
  /// register allocation.
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  bool DisablePostRAScheduler = false;
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  /// HasThumb2 - True if Thumb2 instructions are supported.
202
  bool HasThumb2 = false;
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  /// NoARM - True if subtarget does not support ARM mode execution.
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  bool NoARM = false;
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  /// ReserveR9 - True if R9 is not available as a general purpose register.
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  bool ReserveR9 = false;
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  /// NoMovt - True if MOVT / MOVW pairs are not used for materialization of
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  /// 32-bit imms (including global addresses).
212
  bool NoMovt = false;
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  /// SupportsTailCall - True if the OS supports tail call. The dynamic linker
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  /// must be able to synthesize call stubs for interworking between ARM and
216
  /// Thumb.
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  bool SupportsTailCall = false;
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  /// HasFP16 - True if subtarget supports half-precision FP conversions
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  bool HasFP16 = false;
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  /// HasFullFP16 - True if subtarget supports half-precision FP operations
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  bool HasFullFP16 = false;
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  /// HasD16 - True if subtarget is limited to 16 double precision
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  /// FP registers for VFPv3.
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  bool HasD16 = false;
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  /// HasHardwareDivide - True if subtarget supports [su]div in Thumb mode
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  bool HasHardwareDivideInThumb = false;
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  /// HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode
233
  bool HasHardwareDivideInARM = false;
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  /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier
236
  /// instructions.
237
  bool HasDataBarrier = false;
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  /// HasV7Clrex - True if the subtarget supports CLREX instructions
240
  bool HasV7Clrex = false;
241
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  /// HasAcquireRelease - True if the subtarget supports v8 atomics (LDA/LDAEX etc)
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  /// instructions
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  bool HasAcquireRelease = false;
245
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  /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions
247
  /// over 16-bit ones.
248
  bool Pref32BitThumb = false;
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  /// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions
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  /// that partially update CPSR and add false dependency on the previous
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  /// CPSR setting instruction.
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  bool AvoidCPSRPartialUpdate = false;
254
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  /// CheapPredicableCPSRDef - If true, disable +1 predication cost
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  /// for instructions updating CPSR. Enabled for Cortex-A57.
257
  bool CheapPredicableCPSRDef = false;
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  /// AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting
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  /// movs with shifter operand (i.e. asr, lsl, lsr).
261
  bool AvoidMOVsShifterOperand = false;
262
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  /// HasRetAddrStack - Some processors perform return stack prediction. CodeGen should
264
  /// avoid issue "normal" call instructions to callees which do not return.
265
  bool HasRetAddrStack = false;
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  /// HasBranchPredictor - True if the subtarget has a branch predictor. Having
268
  /// a branch predictor or not changes the expected cost of taking a branch
269
  /// which affects the choice of whether to use predicated instructions.
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  bool HasBranchPredictor = true;
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  /// HasMPExtension - True if the subtarget supports Multiprocessing
273
  /// extension (ARMv7 only).
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  bool HasMPExtension = false;
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  /// HasVirtualization - True if the subtarget supports the Virtualization
277
  /// extension.
278
  bool HasVirtualization = false;
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  /// FPOnlySP - If true, the floating point unit only supports single
281
  /// precision.
282
  bool FPOnlySP = false;
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  /// If true, the processor supports the Performance Monitor Extensions. These
285
  /// include a generic cycle-counter as well as more fine-grained (often
286
  /// implementation-specific) events.
287
  bool HasPerfMon = false;
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  /// HasTrustZone - if true, processor supports TrustZone security extensions
290
  bool HasTrustZone = false;
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292
  /// Has8MSecExt - if true, processor supports ARMv8-M Security Extensions
293
  bool Has8MSecExt = false;
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295
  /// HasCrypto - if true, processor supports Cryptography extensions
296
  bool HasCrypto = false;
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  /// HasCRC - if true, processor supports CRC instructions
299
  bool HasCRC = false;
300
301
  /// HasRAS - if true, the processor supports RAS extensions
302
  bool HasRAS = false;
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304
  /// If true, the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are
305
  /// particularly effective at zeroing a VFP register.
306
  bool HasZeroCycleZeroing = false;
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308
  /// HasFPAO - if true, processor  does positive address offset computation faster
309
  bool HasFPAO = false;
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  /// HasFuseAES - if true, processor executes back to back AES instruction
312
  /// pairs faster.
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  bool HasFuseAES = false;
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315
  /// If true, if conversion may decide to leave some instructions unpredicated.
316
  bool IsProfitableToUnpredicate = false;
317
318
  /// If true, VMOV will be favored over VGETLNi32.
319
  bool HasSlowVGETLNi32 = false;
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321
  /// If true, VMOV will be favored over VDUP.
322
  bool HasSlowVDUP32 = false;
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  /// If true, VMOVSR will be favored over VMOVDRR.
325
  bool PreferVMOVSR = false;
326
327
  /// If true, ISHST barriers will be used for Release semantics.
328
  bool PreferISHST = false;
329
330
  /// If true, a VLDM/VSTM starting with an odd register number is considered to
331
  /// take more microops than single VLDRS/VSTRS.
332
  bool SlowOddRegister = false;
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  /// If true, loading into a D subregister will be penalized.
335
  bool SlowLoadDSubregister = false;
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  /// If true, the AGU and NEON/FPU units are multiplexed.
338
  bool HasMuxedUnits = false;
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  /// If true, VMOVS will never be widened to VMOVD
341
  bool DontWidenVMOVS = false;
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343
  /// If true, run the MLx expansion pass.
344
  bool ExpandMLx = false;
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  /// If true, VFP/NEON VMLA/VMLS have special RAW hazards.
347
  bool HasVMLxHazards = false;
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  // If true, read thread pointer from coprocessor register.
350
  bool ReadTPHard = false;
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  /// If true, VMOVRS, VMOVSR and VMOVS will be converted from VFP to NEON.
353
  bool UseNEONForFPMovs = false;
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355
  /// If true, VLDn instructions take an extra cycle for unaligned accesses.
356
  bool CheckVLDnAlign = false;
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  /// If true, VFP instructions are not pipelined.
359
  bool NonpipelinedVFP = false;
360
361
  /// StrictAlign - If true, the subtarget disallows unaligned memory
362
  /// accesses for some types.  For details, see
363
  /// ARMTargetLowering::allowsMisalignedMemoryAccesses().
364
  bool StrictAlign = false;
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  /// RestrictIT - If true, the subtarget disallows generation of deprecated IT
367
  ///  blocks to conform to ARMv8 rule.
368
  bool RestrictIT = false;
369
370
  /// HasDSP - If true, the subtarget supports the DSP (saturating arith
371
  /// and such) instructions.
372
  bool HasDSP = false;
373
374
  /// NaCl TRAP instruction is generated instead of the regular TRAP.
375
  bool UseNaClTrap = false;
376
377
  /// Generate calls via indirect call instructions.
378
  bool GenLongCalls = false;
379
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  /// Generate code that does not contain data access to code sections.
381
  bool GenExecuteOnly = false;
382
383
  /// Target machine allowed unsafe FP math (such as use of NEON fp)
384
  bool UnsafeFPMath = false;
385
386
  /// UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS).
387
  bool UseSjLjEH = false;
388
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  /// Implicitly convert an instruction to a different one if its immediates
390
  /// cannot be encoded. For example, ADD r0, r1, #FFFFFFFF -> SUB r0, r1, #1.
391
  bool NegativeImmediates = true;
392
393
  /// stackAlignment - The minimum alignment known to hold of the stack frame on
394
  /// entry to the function and which must be maintained by every function.
395
  unsigned stackAlignment = 4;
396
397
  /// CPUString - String name of used CPU.
398
  std::string CPUString;
399
400
  unsigned MaxInterleaveFactor = 1;
401
402
  /// Clearance before partial register updates (in number of instructions)
403
  unsigned PartialUpdateClearance = 0;
404
405
  /// What kind of timing do load multiple/store multiple have (double issue,
406
  /// single issue etc).
407
  ARMLdStMultipleTiming LdStMultipleTiming = SingleIssue;
408
409
  /// The adjustment that we need to apply to get the operand latency from the
410
  /// operand cycle returned by the itinerary data for pre-ISel operands.
411
  int PreISelOperandLatencyAdjustment = 2;
412
413
  /// IsLittle - The target is Little Endian
414
  bool IsLittle;
415
416
  /// TargetTriple - What processor and OS we're targeting.
417
  Triple TargetTriple;
418
419
  /// SchedModel - Processor specific instruction costs.
420
  MCSchedModel SchedModel;
421
422
  /// Selected instruction itineraries (one entry per itinerary class.)
423
  InstrItineraryData InstrItins;
424
425
  /// Options passed via command line that could influence the target
426
  const TargetOptions &Options;
427
428
  const ARMBaseTargetMachine &TM;
429
430
public:
431
  /// This constructor initializes the data members to match that
432
  /// of the specified triple.
433
  ///
434
  ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
435
               const ARMBaseTargetMachine &TM, bool IsLittle);
436
437
  /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
438
  /// that still makes it profitable to inline the call.
439
453
  unsigned getMaxInlineSizeThreshold() const {
440
453
    return 64;
441
453
  }
442
443
  /// ParseSubtargetFeatures - Parses features string setting specified
444
  /// subtarget options.  Definition of function is auto generated by tblgen.
445
  void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
446
447
  /// initializeSubtargetDependencies - Initializes using a CPU and feature string
448
  /// so that we can use initializer lists for subtarget initialization.
449
  ARMSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
450
451
16.8k
  const ARMSelectionDAGInfo *getSelectionDAGInfo() const override {
452
16.8k
    return &TSInfo;
453
16.8k
  }
454
455
2.32M
  const ARMBaseInstrInfo *getInstrInfo() const override {
456
2.32M
    return InstrInfo.get();
457
2.32M
  }
458
459
1.16M
  const ARMTargetLowering *getTargetLowering() const override {
460
1.16M
    return &TLInfo;
461
1.16M
  }
462
463
4.91M
  const ARMFrameLowering *getFrameLowering() const override {
464
4.91M
    return FrameLowering.get();
465
4.91M
  }
466
467
4.52M
  const ARMBaseRegisterInfo *getRegisterInfo() const override {
468
4.52M
    return &InstrInfo->getRegisterInfo();
469
4.52M
  }
470
471
  const CallLowering *getCallLowering() const override;
472
  const InstructionSelector *getInstructionSelector() const override;
473
  const LegalizerInfo *getLegalizerInfo() const override;
474
  const RegisterBankInfo *getRegBankInfo() const override;
475
476
private:
477
  ARMSelectionDAGInfo TSInfo;
478
  // Either Thumb1FrameLowering or ARMFrameLowering.
479
  std::unique_ptr<ARMFrameLowering> FrameLowering;
480
  // Either Thumb1InstrInfo or Thumb2InstrInfo.
481
  std::unique_ptr<ARMBaseInstrInfo> InstrInfo;
482
  ARMTargetLowering   TLInfo;
483
484
  /// GlobalISel related APIs.
485
  std::unique_ptr<CallLowering> CallLoweringInfo;
486
  std::unique_ptr<InstructionSelector> InstSelector;
487
  std::unique_ptr<LegalizerInfo> Legalizer;
488
  std::unique_ptr<RegisterBankInfo> RegBankInfo;
489
490
  void initializeEnvironment();
491
  void initSubtargetFeatures(StringRef CPU, StringRef FS);
492
  ARMFrameLowering *initializeFrameLowering(StringRef CPU, StringRef FS);
493
494
public:
495
  void computeIssueWidth();
496
497
30.9k
  bool hasV4TOps()  const { return HasV4TOps;  }
498
93.3k
  bool hasV5TOps()  const { return HasV5TOps;  }
499
9.61k
  bool hasV5TEOps() const { return HasV5TEOps; }
500
397k
  bool hasV6Ops()   const { return HasV6Ops;   }
501
6.11k
  bool hasV6MOps()  const { return HasV6MOps;  }
502
6.60k
  bool hasV6KOps()  const { return HasV6KOps; }
503
117k
  bool hasV6T2Ops() const { return HasV6T2Ops; }
504
6.69k
  bool hasV7Ops()   const { return HasV7Ops;  }
505
22.6k
  bool hasV8Ops()   const { return HasV8Ops;  }
506
6.12k
  bool hasV8_1aOps() const { return HasV8_1aOps; }
507
0
  bool hasV8_2aOps() const { return HasV8_2aOps; }
508
0
  bool hasV8_3aOps() const { return HasV8_3aOps; }
509
124k
  bool hasV8MBaselineOps() const { return HasV8MBaselineOps; }
510
0
  bool hasV8MMainlineOps() const { return HasV8MMainlineOps; }
511
512
  /// @{
513
  /// These functions are obsolete, please consider adding subtarget features
514
  /// or properties instead of calling them.
515
0
  bool isCortexA5() const { return ARMProcFamily == CortexA5; }
516
412k
  bool isCortexA7() const { return ARMProcFamily == CortexA7; }
517
437k
  bool isCortexA8() const { return ARMProcFamily == CortexA8; }
518
419k
  bool isCortexA9() const { return ARMProcFamily == CortexA9; }
519
431k
  bool isCortexA15() const { return ARMProcFamily == CortexA15; }
520
280k
  bool isSwift()    const { return ARMProcFamily == Swift; }
521
34.3k
  bool isCortexM3() const { return ARMProcFamily == CortexM3; }
522
419k
  bool isLikeA9() const 
{ return isCortexA9() || 419k
isCortexA15()415k
||
isKrait()414k
; }
523
0
  bool isCortexR5() const { return ARMProcFamily == CortexR5; }
524
414k
  bool isKrait() const { return ARMProcFamily == Krait; }
525
  /// @}
526
527
3.22k
  bool hasARMOps() const { return !NoARM; }
528
529
165k
  bool hasVFP2() const { return HasVFPv2; }
530
45.3k
  bool hasVFP3() const { return HasVFPv3; }
531
15.7k
  bool hasVFP4() const { return HasVFPv4; }
532
22.4k
  bool hasFPARMv8() const { return HasFPARMv8; }
533
815k
  bool hasNEON() const { return HasNEON;  }
534
6.15k
  bool hasCrypto() const { return HasCrypto; }
535
0
  bool hasDotProd() const { return HasDotProd; }
536
6.11k
  bool hasCRC() const { return HasCRC; }
537
0
  bool hasRAS() const { return HasRAS; }
538
0
  bool hasVirtualization() const { return HasVirtualization; }
539
540
71.1k
  bool useNEONForSinglePrecisionFP() const {
541
38.4k
    return hasNEON() && UseNEONForSinglePrecisionFP;
542
71.1k
  }
543
544
9.74k
  bool hasDivideInThumbMode() const { return HasHardwareDivideInThumb; }
545
33.5k
  bool hasDivideInARMMode() const { return HasHardwareDivideInARM; }
546
17.7k
  bool hasDataBarrier() const { return HasDataBarrier; }
547
6.78k
  bool hasV7Clrex() const { return HasV7Clrex; }
548
6.30k
  bool hasAcquireRelease() const { return HasAcquireRelease; }
549
550
40.9k
  bool hasAnyDataBarrier() const {
551
13.4k
    return HasDataBarrier || 
(hasV6Ops() && 13.4k
!isThumb()4.02k
);
552
40.9k
  }
553
554
6.51k
  bool useMulOps() const { return UseMulOps; }
555
6.51k
  bool useFPVMLx() const { return !SlowFPVMLx; }
556
108
  bool hasVMLxForwarding() const { return HasVMLxForwarding; }
557
2
  bool isFPBrccSlow() const { return SlowFPBrcc; }
558
92.0k
  bool isFPOnlySP() const { return FPOnlySP; }
559
6.10k
  bool hasPerfMon() const { return HasPerfMon; }
560
0
  bool hasTrustZone() const { return HasTrustZone; }
561
0
  bool has8MSecExt() const { return Has8MSecExt; }
562
6.33k
  bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }
563
37.0k
  bool hasFPAO() const { return HasFPAO; }
564
150
  bool isProfitableToUnpredicate() const { return IsProfitableToUnpredicate; }
565
12.5k
  bool hasSlowVGETLNi32() const { return HasSlowVGETLNi32; }
566
12.2k
  bool hasSlowVDUP32() const { return HasSlowVDUP32; }
567
13.4k
  bool preferVMOVSR() const { return PreferVMOVSR; }
568
1.65k
  bool preferISHSTBarriers() const { return PreferISHST; }
569
15.8k
  bool expandMLx() const { return ExpandMLx; }
570
999
  bool hasVMLxHazards() const { return HasVMLxHazards; }
571
34.2k
  bool hasSlowOddRegister() const { return SlowOddRegister; }
572
19.9k
  bool hasSlowLoadDSubregister() const { return SlowLoadDSubregister; }
573
49.1k
  bool hasMuxedUnits() const { return HasMuxedUnits; }
574
34.8k
  bool dontWidenVMOVS() const { return DontWidenVMOVS; }
575
224k
  bool useNEONForFPMovs() const { return UseNEONForFPMovs; }
576
446k
  bool checkVLDnAccessAlignment() const { return CheckVLDnAlign; }
577
230
  bool nonpipelinedVFP() const { return NonpipelinedVFP; }
578
25.1k
  bool prefers32BitThumb() const { return Pref32BitThumb; }
579
15.2k
  bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; }
580
18.8k
  bool cheapPredicableCPSRDef() const { return CheapPredicableCPSRDef; }
581
2.75k
  bool avoidMOVsShifterOperand() const { return AvoidMOVsShifterOperand; }
582
109
  bool hasRetAddrStack() const { return HasRetAddrStack; }
583
10.8k
  bool hasBranchPredictor() const { return HasBranchPredictor; }
584
6.11k
  bool hasMPExtension() const { return HasMPExtension; }
585
27.5k
  bool hasDSP() const { return HasDSP; }
586
12.3k
  bool useNaClTrap() const { return UseNaClTrap; }
587
6.88k
  bool useSjLjEH() const { return UseSjLjEH; }
588
22.3k
  bool genLongCalls() const { return GenLongCalls; }
589
41.7k
  bool genExecuteOnly() const { return GenExecuteOnly; }
590
591
11.1k
  bool hasFP16() const { return HasFP16; }
592
25.0k
  bool hasD16() const { return HasD16; }
593
6.10k
  bool hasFullFP16() const { return HasFullFP16; }
594
595
1.68k
  bool hasFuseAES() const { return HasFuseAES; }
596
  /// \brief Return true if the CPU supports any kind of instruction fusion.
597
1.55k
  bool hasFusion() const { return hasFuseAES(); }
598
599
26.5k
  const Triple &getTargetTriple() const { return TargetTriple; }
600
601
1.66M
  bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
602
15.5k
  bool isTargetIOS() const { return TargetTriple.isiOS(); }
603
10.4k
  bool isTargetWatchOS() const { return TargetTriple.isWatchOS(); }
604
12.4k
  bool isTargetWatchABI() const { return TargetTriple.isWatchABI(); }
605
8.04k
  bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
606
10.6k
  bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
607
0
  bool isTargetNetBSD() const { return TargetTriple.isOSNetBSD(); }
608
617k
  bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
609
610
36.8k
  bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
611
11.4k
  bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
612
207k
  bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
613
614
  // ARM EABI is the bare-metal EABI described in ARM ABI documents and
615
  // can be accessed via -target arm-none-eabi. This is NOT GNUEABI.
616
  // FIXME: Add a flag for bare-metal for that target and set Triple::EABI
617
  // even for GNUEABI, so we can make a distinction here and still conform to
618
  // the EABI on GNU (and Android) mode. This requires change in Clang, too.
619
  // FIXME: The Darwin exception is temporary, while we move users to
620
  // "*-*-*-macho" triples as quickly as possible.
621
33.7k
  bool isTargetAEABI() const {
622
33.7k
    return (TargetTriple.getEnvironment() == Triple::EABI ||
623
22.5k
            TargetTriple.getEnvironment() == Triple::EABIHF) &&
624
33.7k
           
!isTargetDarwin()11.7k
&&
!isTargetWindows()9.70k
;
625
33.7k
  }
626
19.5k
  bool isTargetGNUAEABI() const {
627
19.5k
    return (TargetTriple.getEnvironment() == Triple::GNUEABI ||
628
15.0k
            TargetTriple.getEnvironment() == Triple::GNUEABIHF) &&
629
19.5k
           
!isTargetDarwin()5.40k
&&
!isTargetWindows()5.40k
;
630
19.5k
  }
631
14.1k
  bool isTargetMuslAEABI() const {
632
14.1k
    return (TargetTriple.getEnvironment() == Triple::MuslEABI ||
633
14.0k
            TargetTriple.getEnvironment() == Triple::MuslEABIHF) &&
634
14.1k
           
!isTargetDarwin()291
&&
!isTargetWindows()291
;
635
14.1k
  }
636
637
  // ARM Targets that support EHABI exception handling standard
638
  // Darwin uses SjLj. Other targets might need more checks.
639
375k
  bool isTargetEHABICompatible() const {
640
375k
    return (TargetTriple.getEnvironment() == Triple::EABI ||
641
325k
            TargetTriple.getEnvironment() == Triple::GNUEABI ||
642
309k
            TargetTriple.getEnvironment() == Triple::MuslEABI ||
643
308k
            TargetTriple.getEnvironment() == Triple::EABIHF ||
644
304k
            TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
645
300k
            TargetTriple.getEnvironment() == Triple::MuslEABIHF ||
646
300k
            isTargetAndroid()) &&
647
375k
           
!isTargetDarwin()77.2k
&&
!isTargetWindows()61.2k
;
648
375k
  }
649
650
0
  bool isTargetHardFloat() const {
651
0
    // FIXME: this is invalid for WindowsCE
652
0
    return TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
653
0
           TargetTriple.getEnvironment() == Triple::MuslEABIHF ||
654
0
           TargetTriple.getEnvironment() == Triple::EABIHF ||
655
0
           isTargetWindows() || isAAPCS16_ABI();
656
0
  }
657
658
307k
  bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
659
660
  bool isXRaySupported() const override;
661
662
  bool isAPCS_ABI() const;
663
  bool isAAPCS_ABI() const;
664
  bool isAAPCS16_ABI() const;
665
666
  bool isROPI() const;
667
  bool isRWPI() const;
668
669
87.9k
  bool useMachineScheduler() const { return UseMISched; }
670
15.6k
  bool disablePostRAScheduler() const { return DisablePostRAScheduler; }
671
80.2k
  bool useSoftFloat() const { return UseSoftFloat; }
672
1.59M
  bool isThumb() const { return InThumbMode; }
673
1.51M
  bool isThumb1Only() const 
{ return InThumbMode && 1.51M
!HasThumb21.11M
; }
674
899k
  bool isThumb2() const 
{ return InThumbMode && 899k
HasThumb2835k
; }
675
81.3k
  bool hasThumb2() const { return HasThumb2; }
676
32.2k
  bool isMClass() const { return ARMProcClass == MClass; }
677
0
  bool isRClass() const { return ARMProcClass == RClass; }
678
0
  bool isAClass() const { return ARMProcClass == AClass; }
679
12.2k
  bool isReadTPHard() const { return ReadTPHard; }
680
681
71.4k
  bool isR9Reserved() const {
682
71.4k
    return isTargetMachO() ? 
(ReserveR9 || 42.9k
!HasV6Ops42.9k
) :
ReserveR928.4k
;
683
71.4k
  }
684
685
996k
  bool useR7AsFramePointer() const {
686
418k
    return isTargetDarwin() || 
(!isTargetWindows() && 418k
isThumb()410k
);
687
996k
  }
688
689
  /// Returns true if the frame setup is split into two separate pushes (first
690
  /// r0-r7,lr then r8-r11), principally so that the frame pointer is adjacent
691
  /// to lr. This is always required on Thumb1-only targets, as the push and
692
  /// pop instructions can't access the high registers.
693
565k
  bool splitFramePushPop(const MachineFunction &MF) const {
694
565k
    return (useR7AsFramePointer() &&
695
391k
            MF.getTarget().Options.DisableFramePointerElim(MF)) ||
696
330k
           isThumb1Only();
697
565k
  }
698
699
  bool useStride4VFPs(const MachineFunction &MF) const;
700
701
  bool useMovt(const MachineFunction &MF) const;
702
703
22.2k
  bool supportsTailCall() const { return SupportsTailCall; }
704
705
2.56k
  bool allowsUnalignedMem() const { return !StrictAlign; }
706
707
140k
  bool restrictIT() const { return RestrictIT; }
708
709
0
  const std::string & getCPUString() const { return CPUString; }
710
711
18.9k
  bool isLittle() const { return IsLittle; }
712
713
  unsigned getMispredictionPenalty() const;
714
715
  /// This function returns true if the target has sincos() routine in its
716
  /// compiler runtime or math libraries.
717
  bool hasSinCos() const;
718
719
  /// Returns true if machine scheduler should be enabled.
720
  bool enableMachineScheduler() const override;
721
722
  /// True for some subtargets at > -O0.
723
  bool enablePostRAScheduler() const override;
724
725
  // enableAtomicExpand- True if we need to expand our atomics.
726
  bool enableAtomicExpand() const override;
727
728
  /// getInstrItins - Return the instruction itineraries based on subtarget
729
  /// selection.
730
127k
  const InstrItineraryData *getInstrItineraryData() const override {
731
127k
    return &InstrItins;
732
127k
  }
733
734
  /// getStackAlignment - Returns the minimum alignment known to hold of the
735
  /// stack frame on entry to the function and which must be maintained by every
736
  /// function for this subtarget.
737
6.10k
  unsigned getStackAlignment() const { return stackAlignment; }
738
739
1.09k
  unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
740
741
29.0k
  unsigned getPartialUpdateClearance() const { return PartialUpdateClearance; }
742
743
7.62k
  ARMLdStMultipleTiming getLdStMultipleTiming() const {
744
7.62k
    return LdStMultipleTiming;
745
7.62k
  }
746
747
45.8k
  int getPreISelOperandLatencyAdjustment() const {
748
45.8k
    return PreISelOperandLatencyAdjustment;
749
45.8k
  }
750
751
  /// True if the GV will be accessed via an indirect symbol.
752
  bool isGVIndirectSymbol(const GlobalValue *GV) const;
753
754
  /// Returns the constant pool modifier needed to access the GV.
755
  ARMCP::ARMCPModifier getCPModifier(const GlobalValue *GV) const;
756
757
  /// True if fast-isel is used.
758
  bool useFastISel() const;
759
760
  /// Returns the correct return opcode for the current feature set.
761
  /// Use BX if available to allow mixing thumb/arm code, but fall back
762
  /// to plain mov pc,lr on ARMv4.
763
1.15k
  unsigned getReturnOpcode() const {
764
1.15k
    if (isThumb())
765
326
      return ARM::tBX_RET;
766
828
    
if (828
hasV4TOps()828
)
767
789
      return ARM::BX_RET;
768
39
    return ARM::MOVPCLR;
769
1.15k
  }
770
};
771
772
} // end namespace llvm
773
774
#endif  // LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H