/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/llvm/lib/Target/Hexagon/RDFRegisters.h
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1 | | //===- RDFRegisters.h -------------------------------------------*- C++ -*-===// |
2 | | // |
3 | | // The LLVM Compiler Infrastructure |
4 | | // |
5 | | // This file is distributed under the University of Illinois Open Source |
6 | | // License. See LICENSE.TXT for details. |
7 | | // |
8 | | //===----------------------------------------------------------------------===// |
9 | | |
10 | | #ifndef LLVM_LIB_TARGET_HEXAGON_RDFREGISTERS_H |
11 | | #define LLVM_LIB_TARGET_HEXAGON_RDFREGISTERS_H |
12 | | |
13 | | #include "llvm/ADT/BitVector.h" |
14 | | #include "llvm/ADT/STLExtras.h" |
15 | | #include "llvm/MC/LaneBitmask.h" |
16 | | #include "llvm/Target/TargetRegisterInfo.h" |
17 | | #include <cassert> |
18 | | #include <cstdint> |
19 | | #include <map> |
20 | | #include <set> |
21 | | #include <vector> |
22 | | |
23 | | namespace llvm { |
24 | | |
25 | | class MachineFunction; |
26 | | class raw_ostream; |
27 | | |
28 | | namespace rdf { |
29 | | |
30 | | using RegisterId = uint32_t; |
31 | | |
32 | | // Template class for a map translating uint32_t into arbitrary types. |
33 | | // The map will act like an indexed set: upon insertion of a new object, |
34 | | // it will automatically assign a new index to it. Index of 0 is treated |
35 | | // as invalid and is never allocated. |
36 | | template <typename T, unsigned N = 32> |
37 | | struct IndexedSet { |
38 | 3.43k | IndexedSet() { Map.reserve(N); } llvm::rdf::IndexedSet<llvm::LaneBitmask, 32u>::IndexedSet() Line | Count | Source | 38 | 1.71k | IndexedSet() { Map.reserve(N); } |
llvm::rdf::IndexedSet<unsigned int const*, 32u>::IndexedSet() Line | Count | Source | 38 | 1.71k | IndexedSet() { Map.reserve(N); } |
|
39 | | |
40 | 59.6k | T get(uint32_t Idx) const { |
41 | 59.6k | // Index Idx corresponds to Map[Idx-1]. |
42 | 59.6k | assert(Idx != 0 && !Map.empty() && Idx-1 < Map.size()); |
43 | 59.6k | return Map[Idx-1]; |
44 | 59.6k | } llvm::rdf::IndexedSet<llvm::LaneBitmask, 32u>::get(unsigned int) const Line | Count | Source | 40 | 22.6k | T get(uint32_t Idx) const { | 41 | 22.6k | // Index Idx corresponds to Map[Idx-1]. | 42 | 22.6k | assert(Idx != 0 && !Map.empty() && Idx-1 < Map.size()); | 43 | 22.6k | return Map[Idx-1]; | 44 | 22.6k | } |
llvm::rdf::IndexedSet<unsigned int const*, 32u>::get(unsigned int) const Line | Count | Source | 40 | 36.9k | T get(uint32_t Idx) const { | 41 | 36.9k | // Index Idx corresponds to Map[Idx-1]. | 42 | 36.9k | assert(Idx != 0 && !Map.empty() && Idx-1 < Map.size()); | 43 | 36.9k | return Map[Idx-1]; | 44 | 36.9k | } |
|
45 | | |
46 | 5.01k | uint32_t insert(T Val) { |
47 | 5.01k | // Linear search. |
48 | 5.01k | auto F = llvm::find(Map, Val); |
49 | 5.01k | if (F != Map.end()) |
50 | 1.94k | return F - Map.begin() + 1; |
51 | 3.07k | Map.push_back(Val); |
52 | 3.07k | return Map.size(); // Return actual_index + 1. |
53 | 5.01k | } llvm::rdf::IndexedSet<llvm::LaneBitmask, 32u>::insert(llvm::LaneBitmask) Line | Count | Source | 46 | 2.84k | uint32_t insert(T Val) { | 47 | 2.84k | // Linear search. | 48 | 2.84k | auto F = llvm::find(Map, Val); | 49 | 2.84k | if (F != Map.end()) | 50 | 1.48k | return F - Map.begin() + 1; | 51 | 1.36k | Map.push_back(Val); | 52 | 1.36k | return Map.size(); // Return actual_index + 1. | 53 | 2.84k | } |
llvm::rdf::IndexedSet<unsigned int const*, 32u>::insert(unsigned int const*) Line | Count | Source | 46 | 2.16k | uint32_t insert(T Val) { | 47 | 2.16k | // Linear search. | 48 | 2.16k | auto F = llvm::find(Map, Val); | 49 | 2.16k | if (F != Map.end()) | 50 | 452 | return F - Map.begin() + 1; | 51 | 1.71k | Map.push_back(Val); | 52 | 1.71k | return Map.size(); // Return actual_index + 1. | 53 | 2.16k | } |
|
54 | | |
55 | 66.6k | uint32_t find(T Val) const { |
56 | 66.6k | auto F = llvm::find(Map, Val); |
57 | 66.6k | assert(F != Map.end()); |
58 | 66.6k | return F - Map.begin() + 1; |
59 | 66.6k | } Unexecuted instantiation: llvm::rdf::IndexedSet<llvm::LaneBitmask, 32u>::find(llvm::LaneBitmask) const llvm::rdf::IndexedSet<unsigned int const*, 32u>::find(unsigned int const*) const Line | Count | Source | 55 | 66.6k | uint32_t find(T Val) const { | 56 | 66.6k | auto F = llvm::find(Map, Val); | 57 | 66.6k | assert(F != Map.end()); | 58 | 66.6k | return F - Map.begin() + 1; | 59 | 66.6k | } |
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60 | | |
61 | 3.43k | uint32_t size() const { return Map.size(); } |
62 | | |
63 | | using const_iterator = typename std::vector<T>::const_iterator; |
64 | | |
65 | 30.8k | const_iterator begin() const { return Map.begin(); } |
66 | 30.8k | const_iterator end() const { return Map.end(); } |
67 | | |
68 | | private: |
69 | | std::vector<T> Map; |
70 | | }; |
71 | | |
72 | | struct RegisterRef { |
73 | | RegisterId Reg = 0; |
74 | | LaneBitmask Mask = LaneBitmask::getNone(); |
75 | | |
76 | 4.99k | RegisterRef() = default; |
77 | | explicit RegisterRef(RegisterId R, LaneBitmask M = LaneBitmask::getAll()) |
78 | 862k | : Reg(R), Mask(R != 0 ? M : LaneBitmask::getNone()) {} |
79 | | |
80 | 10.9k | operator bool() const { |
81 | 6.14k | return Reg != 0 && Mask.any(); |
82 | 10.9k | } |
83 | | |
84 | 232k | bool operator== (const RegisterRef &RR) const { |
85 | 75.3k | return Reg == RR.Reg && Mask == RR.Mask; |
86 | 232k | } |
87 | | |
88 | 148k | bool operator!= (const RegisterRef &RR) const { |
89 | 148k | return !operator==(RR); |
90 | 148k | } |
91 | | |
92 | 494k | bool operator< (const RegisterRef &RR) const { |
93 | 273k | return Reg < RR.Reg || (Reg == RR.Reg && 273k Mask < RR.Mask123k ); |
94 | 494k | } |
95 | | }; |
96 | | |
97 | | |
98 | | struct PhysicalRegisterInfo { |
99 | | PhysicalRegisterInfo(const TargetRegisterInfo &tri, |
100 | | const MachineFunction &mf); |
101 | | |
102 | 810k | static bool isRegMaskId(RegisterId R) { |
103 | 810k | return TargetRegisterInfo::isStackSlot(R); |
104 | 810k | } |
105 | | |
106 | 66.6k | RegisterId getRegMaskId(const uint32_t *RM) const { |
107 | 66.6k | return TargetRegisterInfo::index2StackSlot(RegMasks.find(RM)); |
108 | 66.6k | } |
109 | | |
110 | 35.2k | const uint32_t *getRegMaskBits(RegisterId R) const { |
111 | 35.2k | return RegMasks.get(TargetRegisterInfo::stackSlot2Index(R)); |
112 | 35.2k | } |
113 | | |
114 | | RegisterRef normalize(RegisterRef RR) const; |
115 | | |
116 | 65.1k | bool alias(RegisterRef RA, RegisterRef RB) const { |
117 | 65.1k | if (!isRegMaskId(RA.Reg)) |
118 | 61.6k | return !isRegMaskId(RB.Reg) ? 61.6k aliasRR(RA, RB)61.3k : aliasRM(RA, RB)328 ; |
119 | 3.54k | return !isRegMaskId(RB.Reg) ? 3.54k aliasRM(RB, RA)2.95k : aliasMM(RA, RB)585 ; |
120 | 65.1k | } |
121 | | |
122 | | std::set<RegisterId> getAliasSet(RegisterId Reg) const; |
123 | | |
124 | 15.0k | RegisterRef getRefForUnit(uint32_t U) const { |
125 | 15.0k | return RegisterRef(UnitInfos[U].Reg, UnitInfos[U].Mask); |
126 | 15.0k | } |
127 | | |
128 | 25.4k | const BitVector &getMaskUnits(RegisterId MaskId) const { |
129 | 25.4k | return MaskInfos[TargetRegisterInfo::stackSlot2Index(MaskId)].Units; |
130 | 25.4k | } |
131 | | |
132 | | RegisterRef mapTo(RegisterRef RR, unsigned R) const; |
133 | 922k | const TargetRegisterInfo &getTRI() const { return TRI; } |
134 | | |
135 | | private: |
136 | | struct RegInfo { |
137 | | const TargetRegisterClass *RegClass = nullptr; |
138 | | }; |
139 | | struct UnitInfo { |
140 | | RegisterId Reg = 0; |
141 | | LaneBitmask Mask; |
142 | | }; |
143 | | struct MaskInfo { |
144 | | BitVector Units; |
145 | | }; |
146 | | |
147 | | const TargetRegisterInfo &TRI; |
148 | | IndexedSet<const uint32_t*> RegMasks; |
149 | | std::vector<RegInfo> RegInfos; |
150 | | std::vector<UnitInfo> UnitInfos; |
151 | | std::vector<MaskInfo> MaskInfos; |
152 | | |
153 | | bool aliasRR(RegisterRef RA, RegisterRef RB) const; |
154 | | bool aliasRM(RegisterRef RR, RegisterRef RM) const; |
155 | | bool aliasMM(RegisterRef RM, RegisterRef RN) const; |
156 | | }; |
157 | | |
158 | | struct RegisterAggr { |
159 | | RegisterAggr(const PhysicalRegisterInfo &pri) |
160 | 257k | : Units(pri.getTRI().getNumRegUnits()), PRI(pri) {} |
161 | 58.5k | RegisterAggr(const RegisterAggr &RG) = default; |
162 | | |
163 | 704 | bool empty() const { return Units.none(); } |
164 | | bool hasAliasOf(RegisterRef RR) const; |
165 | | bool hasCoverOf(RegisterRef RR) const; |
166 | | |
167 | | static bool isCoverOf(RegisterRef RA, RegisterRef RB, |
168 | 154k | const PhysicalRegisterInfo &PRI) { |
169 | 154k | return RegisterAggr(PRI).insert(RA).hasCoverOf(RB); |
170 | 154k | } |
171 | | |
172 | | RegisterAggr &insert(RegisterRef RR); |
173 | | RegisterAggr &insert(const RegisterAggr &RG); |
174 | | RegisterAggr &intersect(RegisterRef RR); |
175 | | RegisterAggr &intersect(const RegisterAggr &RG); |
176 | | RegisterAggr &clear(RegisterRef RR); |
177 | | RegisterAggr &clear(const RegisterAggr &RG); |
178 | | |
179 | | RegisterRef intersectWith(RegisterRef RR) const; |
180 | | RegisterRef clearIn(RegisterRef RR) const; |
181 | | RegisterRef makeRegRef() const; |
182 | | |
183 | | void print(raw_ostream &OS) const; |
184 | | |
185 | | struct rr_iterator { |
186 | | using MapType = std::map<RegisterId, LaneBitmask>; |
187 | | |
188 | | private: |
189 | | MapType Masks; |
190 | | MapType::iterator Pos; |
191 | | unsigned Index; |
192 | | const RegisterAggr *Owner; |
193 | | |
194 | | public: |
195 | | rr_iterator(const RegisterAggr &RG, bool End); |
196 | | |
197 | 7.50k | RegisterRef operator*() const { |
198 | 7.50k | return RegisterRef(Pos->first, Pos->second); |
199 | 7.50k | } |
200 | | |
201 | 7.50k | rr_iterator &operator++() { |
202 | 7.50k | ++Pos; |
203 | 7.50k | ++Index; |
204 | 7.50k | return *this; |
205 | 7.50k | } |
206 | | |
207 | 10.5k | bool operator==(const rr_iterator &I) const { |
208 | 10.5k | assert(Owner == I.Owner); |
209 | 10.5k | return Index == I.Index; |
210 | 10.5k | } |
211 | | |
212 | 10.5k | bool operator!=(const rr_iterator &I) const { |
213 | 10.5k | return !(*this == I); |
214 | 10.5k | } |
215 | | }; |
216 | | |
217 | 3.02k | rr_iterator rr_begin() const { |
218 | 3.02k | return rr_iterator(*this, false); |
219 | 3.02k | } |
220 | 3.02k | rr_iterator rr_end() const { |
221 | 3.02k | return rr_iterator(*this, true); |
222 | 3.02k | } |
223 | | |
224 | | private: |
225 | | BitVector Units; |
226 | | const PhysicalRegisterInfo &PRI; |
227 | | }; |
228 | | |
229 | | // Optionally print the lane mask, if it is not ~0. |
230 | | struct PrintLaneMaskOpt { |
231 | 0 | PrintLaneMaskOpt(LaneBitmask M) : Mask(M) {} |
232 | | LaneBitmask Mask; |
233 | | }; |
234 | | raw_ostream &operator<< (raw_ostream &OS, const PrintLaneMaskOpt &P); |
235 | | |
236 | | } // end namespace rdf |
237 | | |
238 | | } // end namespace llvm |
239 | | |
240 | | #endif // LLVM_LIB_TARGET_HEXAGON_RDFREGISTERS_H |