/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/llvm/lib/Target/Mips/MCTargetDesc/MipsOptionRecord.cpp
Line | Count | Source (jump to first uncovered line) |
1 | | //===- MipsOptionRecord.cpp - Abstraction for storing information ---------===// |
2 | | // |
3 | | // The LLVM Compiler Infrastructure |
4 | | // |
5 | | // This file is distributed under the University of Illinois Open Source |
6 | | // License. See LICENSE.TXT for details. |
7 | | // |
8 | | //===----------------------------------------------------------------------===// |
9 | | |
10 | | #include "MipsOptionRecord.h" |
11 | | #include "MipsABIInfo.h" |
12 | | #include "MipsELFStreamer.h" |
13 | | #include "MipsTargetStreamer.h" |
14 | | #include "llvm/BinaryFormat/ELF.h" |
15 | | #include "llvm/MC/MCAssembler.h" |
16 | | #include "llvm/MC/MCContext.h" |
17 | | #include "llvm/MC/MCRegisterInfo.h" |
18 | | #include "llvm/MC/MCSectionELF.h" |
19 | | #include <cassert> |
20 | | |
21 | | using namespace llvm; |
22 | | |
23 | 461 | void MipsRegInfoRecord::EmitMipsOptionRecord() { |
24 | 461 | MCAssembler &MCA = Streamer->getAssembler(); |
25 | 461 | MipsTargetStreamer *MTS = |
26 | 461 | static_cast<MipsTargetStreamer *>(Streamer->getTargetStreamer()); |
27 | 461 | |
28 | 461 | Streamer->PushSection(); |
29 | 461 | |
30 | 461 | // We need to distinguish between N64 and the rest because at the moment |
31 | 461 | // we don't emit .Mips.options for other ELFs other than N64. |
32 | 461 | // Since .reginfo has the same information as .Mips.options (ODK_REGINFO), |
33 | 461 | // we can use the same abstraction (MipsRegInfoRecord class) to handle both. |
34 | 461 | if (MTS->getABI().IsN64()461 ) { |
35 | 151 | // The EntrySize value of 1 seems strange since the records are neither |
36 | 151 | // 1-byte long nor fixed length but it matches the value GAS emits. |
37 | 151 | MCSectionELF *Sec = |
38 | 151 | Context.getELFSection(".MIPS.options", ELF::SHT_MIPS_OPTIONS, |
39 | 151 | ELF::SHF_ALLOC | ELF::SHF_MIPS_NOSTRIP, 1, ""); |
40 | 151 | MCA.registerSection(*Sec); |
41 | 151 | Sec->setAlignment(8); |
42 | 151 | Streamer->SwitchSection(Sec); |
43 | 151 | |
44 | 151 | Streamer->EmitIntValue(ELF::ODK_REGINFO, 1); // kind |
45 | 151 | Streamer->EmitIntValue(40, 1); // size |
46 | 151 | Streamer->EmitIntValue(0, 2); // section |
47 | 151 | Streamer->EmitIntValue(0, 4); // info |
48 | 151 | Streamer->EmitIntValue(ri_gprmask, 4); |
49 | 151 | Streamer->EmitIntValue(0, 4); // pad |
50 | 151 | Streamer->EmitIntValue(ri_cprmask[0], 4); |
51 | 151 | Streamer->EmitIntValue(ri_cprmask[1], 4); |
52 | 151 | Streamer->EmitIntValue(ri_cprmask[2], 4); |
53 | 151 | Streamer->EmitIntValue(ri_cprmask[3], 4); |
54 | 151 | Streamer->EmitIntValue(ri_gp_value, 8); |
55 | 461 | } else { |
56 | 310 | MCSectionELF *Sec = Context.getELFSection(".reginfo", ELF::SHT_MIPS_REGINFO, |
57 | 310 | ELF::SHF_ALLOC, 24, ""); |
58 | 310 | MCA.registerSection(*Sec); |
59 | 310 | Sec->setAlignment(MTS->getABI().IsN32() ? 844 : 4266 ); |
60 | 310 | Streamer->SwitchSection(Sec); |
61 | 310 | |
62 | 310 | Streamer->EmitIntValue(ri_gprmask, 4); |
63 | 310 | Streamer->EmitIntValue(ri_cprmask[0], 4); |
64 | 310 | Streamer->EmitIntValue(ri_cprmask[1], 4); |
65 | 310 | Streamer->EmitIntValue(ri_cprmask[2], 4); |
66 | 310 | Streamer->EmitIntValue(ri_cprmask[3], 4); |
67 | 310 | assert((ri_gp_value & 0xffffffff) == ri_gp_value); |
68 | 310 | Streamer->EmitIntValue(ri_gp_value, 4); |
69 | 310 | } |
70 | 461 | |
71 | 461 | Streamer->PopSection(); |
72 | 461 | } |
73 | | |
74 | | void MipsRegInfoRecord::SetPhysRegUsed(unsigned Reg, |
75 | 4.61k | const MCRegisterInfo *MCRegInfo) { |
76 | 4.61k | unsigned Value = 0; |
77 | 4.61k | |
78 | 10.0k | for (MCSubRegIterator SubRegIt(Reg, MCRegInfo, true); SubRegIt.isValid(); |
79 | 5.41k | ++SubRegIt5.41k ) { |
80 | 5.41k | unsigned CurrentSubReg = *SubRegIt; |
81 | 5.41k | |
82 | 5.41k | unsigned EncVal = MCRegInfo->getEncodingValue(CurrentSubReg); |
83 | 5.41k | Value |= 1 << EncVal; |
84 | 5.41k | |
85 | 5.41k | if (GPR32RegClass->contains(CurrentSubReg) || |
86 | 887 | GPR64RegClass->contains(CurrentSubReg)) |
87 | 5.18k | ri_gprmask |= Value; |
88 | 232 | else if (232 COP0RegClass->contains(CurrentSubReg)232 ) |
89 | 2 | ri_cprmask[0] |= Value; |
90 | 232 | // MIPS COP1 is the FPU. |
91 | 230 | else if (230 FGR32RegClass->contains(CurrentSubReg) || |
92 | 120 | FGR64RegClass->contains(CurrentSubReg) || |
93 | 78 | AFGR64RegClass->contains(CurrentSubReg) || |
94 | 60 | MSA128BRegClass->contains(CurrentSubReg)) |
95 | 188 | ri_cprmask[1] |= Value; |
96 | 42 | else if (42 COP2RegClass->contains(CurrentSubReg)42 ) |
97 | 0 | ri_cprmask[2] |= Value; |
98 | 42 | else if (42 COP3RegClass->contains(CurrentSubReg)42 ) |
99 | 0 | ri_cprmask[3] |= Value; |
100 | 5.41k | } |
101 | 4.61k | } |