/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/llvm/lib/Target/Mips/MipsMachineFunction.cpp
Line | Count | Source (jump to first uncovered line) |
1 | | //===-- MipsMachineFunctionInfo.cpp - Private data used for Mips ----------===// |
2 | | // |
3 | | // The LLVM Compiler Infrastructure |
4 | | // |
5 | | // This file is distributed under the University of Illinois Open Source |
6 | | // License. See LICENSE.TXT for details. |
7 | | // |
8 | | //===----------------------------------------------------------------------===// |
9 | | |
10 | | #include "MipsMachineFunction.h" |
11 | | #include "MCTargetDesc/MipsABIInfo.h" |
12 | | #include "MipsSubtarget.h" |
13 | | #include "MipsTargetMachine.h" |
14 | | #include "llvm/CodeGen/MachineFrameInfo.h" |
15 | | #include "llvm/CodeGen/MachineRegisterInfo.h" |
16 | | #include "llvm/CodeGen/PseudoSourceValue.h" |
17 | | #include "llvm/Support/CommandLine.h" |
18 | | #include "llvm/Target/TargetRegisterInfo.h" |
19 | | |
20 | | using namespace llvm; |
21 | | |
22 | | static cl::opt<bool> |
23 | | FixGlobalBaseReg("mips-fix-global-base-reg", cl::Hidden, cl::init(true), |
24 | | cl::desc("Always use $gp as the global base register.")); |
25 | | |
26 | 12.3k | MipsFunctionInfo::~MipsFunctionInfo() = default; |
27 | | |
28 | 14.9k | bool MipsFunctionInfo::globalBaseRegSet() const { |
29 | 14.9k | return GlobalBaseReg; |
30 | 14.9k | } |
31 | | |
32 | 12.1k | unsigned MipsFunctionInfo::getGlobalBaseReg() { |
33 | 12.1k | // Return if it has already been initialized. |
34 | 12.1k | if (GlobalBaseReg) |
35 | 8.85k | return GlobalBaseReg; |
36 | 3.24k | |
37 | 3.24k | MipsSubtarget const &STI = |
38 | 3.24k | static_cast<const MipsSubtarget &>(MF.getSubtarget()); |
39 | 3.24k | |
40 | 3.24k | const TargetRegisterClass *RC = |
41 | 3.24k | STI.inMips16Mode() |
42 | 197 | ? &Mips::CPU16RegsRegClass |
43 | 3.04k | : STI.inMicroMipsMode() |
44 | 160 | ? STI.hasMips64() |
45 | 32 | ? &Mips::GPRMM16_64RegClass |
46 | 128 | : &Mips::GPRMM16RegClass |
47 | 2.88k | : static_cast<const MipsTargetMachine &>(MF.getTarget()) |
48 | 2.88k | .getABI() |
49 | 2.88k | .IsN64() |
50 | 1.01k | ? &Mips::GPR64RegClass |
51 | 1.87k | : &Mips::GPR32RegClass; |
52 | 12.1k | return GlobalBaseReg = MF.getRegInfo().createVirtualRegister(RC); |
53 | 12.1k | } |
54 | | |
55 | 14 | void MipsFunctionInfo::createEhDataRegsFI() { |
56 | 14 | const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); |
57 | 70 | for (int I = 0; I < 470 ; ++I56 ) { |
58 | 56 | const TargetRegisterClass &RC = |
59 | 56 | static_cast<const MipsTargetMachine &>(MF.getTarget()).getABI().IsN64() |
60 | 32 | ? Mips::GPR64RegClass |
61 | 24 | : Mips::GPR32RegClass; |
62 | 56 | |
63 | 56 | EhDataRegFI[I] = MF.getFrameInfo().CreateStackObject(TRI.getSpillSize(RC), |
64 | 56 | TRI.getSpillAlignment(RC), false); |
65 | 56 | } |
66 | 14 | } |
67 | | |
68 | 11 | void MipsFunctionInfo::createISRRegFI() { |
69 | 11 | // ISRs require spill slots for Status & ErrorPC Coprocessor 0 registers. |
70 | 11 | // The current implementation only supports Mips32r2+ not Mips64rX. Status |
71 | 11 | // is always 32 bits, ErrorPC is 32 or 64 bits dependent on architecture, |
72 | 11 | // however Mips32r2+ is the supported architecture. |
73 | 11 | const TargetRegisterClass &RC = Mips::GPR32RegClass; |
74 | 11 | const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); |
75 | 11 | |
76 | 33 | for (int I = 0; I < 233 ; ++I22 ) |
77 | 22 | ISRDataRegFI[I] = MF.getFrameInfo().CreateStackObject( |
78 | 22 | TRI.getSpillSize(RC), TRI.getSpillAlignment(RC), false); |
79 | 11 | } |
80 | | |
81 | 12.8k | bool MipsFunctionInfo::isEhDataRegFI(int FI) const { |
82 | 162 | return CallsEhReturn && (FI == EhDataRegFI[0] || 162 FI == EhDataRegFI[1]134 |
83 | 162 | || FI == EhDataRegFI[2]106 || FI == EhDataRegFI[3]78 ); |
84 | 12.8k | } |
85 | | |
86 | 12.8k | bool MipsFunctionInfo::isISRRegFI(int FI) const { |
87 | 78 | return IsISR && (FI == ISRDataRegFI[0] || 78 FI == ISRDataRegFI[1]60 ); |
88 | 12.8k | } |
89 | 636 | MachinePointerInfo MipsFunctionInfo::callPtrInfo(const char *ES) { |
90 | 636 | return MachinePointerInfo(MF.getPSVManager().getExternalSymbolCallEntry(ES)); |
91 | 636 | } |
92 | | |
93 | 1.08k | MachinePointerInfo MipsFunctionInfo::callPtrInfo(const GlobalValue *GV) { |
94 | 1.08k | return MachinePointerInfo(MF.getPSVManager().getGlobalValueCallEntry(GV)); |
95 | 1.08k | } |
96 | | |
97 | 25 | int MipsFunctionInfo::getMoveF64ViaSpillFI(const TargetRegisterClass *RC) { |
98 | 25 | const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); |
99 | 25 | if (MoveF64ViaSpillFI == -125 ) { |
100 | 19 | MoveF64ViaSpillFI = MF.getFrameInfo().CreateStackObject( |
101 | 19 | TRI.getSpillSize(*RC), TRI.getSpillAlignment(*RC), false); |
102 | 19 | } |
103 | 25 | return MoveF64ViaSpillFI; |
104 | 25 | } |
105 | | |
106 | 0 | void MipsFunctionInfo::anchor() {} |