Coverage Report

Created: 2017-10-03 07:32

/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
Line
Count
Source (jump to first uncovered line)
1
//===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===//
2
//
3
//                     The LLVM Compiler Infrastructure
4
//
5
// This file is distributed under the University of Illinois Open Source
6
// License. See LICENSE.TXT for details.
7
//
8
//===----------------------------------------------------------------------===//
9
//
10
// This file contains the PowerPC implementation of the TargetRegisterInfo
11
// class.
12
//
13
//===----------------------------------------------------------------------===//
14
15
#include "PPCRegisterInfo.h"
16
#include "PPC.h"
17
#include "PPCFrameLowering.h"
18
#include "PPCInstrBuilder.h"
19
#include "PPCMachineFunctionInfo.h"
20
#include "PPCSubtarget.h"
21
#include "PPCTargetMachine.h"
22
#include "llvm/ADT/BitVector.h"
23
#include "llvm/ADT/STLExtras.h"
24
#include "llvm/ADT/Statistic.h"
25
#include "llvm/CodeGen/MachineFrameInfo.h"
26
#include "llvm/CodeGen/MachineFunction.h"
27
#include "llvm/CodeGen/MachineInstrBuilder.h"
28
#include "llvm/CodeGen/MachineModuleInfo.h"
29
#include "llvm/CodeGen/MachineRegisterInfo.h"
30
#include "llvm/CodeGen/RegisterScavenging.h"
31
#include "llvm/IR/CallingConv.h"
32
#include "llvm/IR/Constants.h"
33
#include "llvm/IR/Function.h"
34
#include "llvm/IR/Type.h"
35
#include "llvm/Support/CommandLine.h"
36
#include "llvm/Support/Debug.h"
37
#include "llvm/Support/ErrorHandling.h"
38
#include "llvm/Support/MathExtras.h"
39
#include "llvm/Support/raw_ostream.h"
40
#include "llvm/Target/TargetFrameLowering.h"
41
#include "llvm/Target/TargetInstrInfo.h"
42
#include "llvm/Target/TargetMachine.h"
43
#include "llvm/Target/TargetOptions.h"
44
#include <cstdlib>
45
46
using namespace llvm;
47
48
#define DEBUG_TYPE "reginfo"
49
50
#define GET_REGINFO_TARGET_DESC
51
#include "PPCGenRegisterInfo.inc"
52
53
STATISTIC(InflateGPRC, "Number of gprc inputs for getLargestLegalClass");
54
STATISTIC(InflateGP8RC, "Number of g8rc inputs for getLargestLegalClass");
55
56
static cl::opt<bool>
57
EnableBasePointer("ppc-use-base-pointer", cl::Hidden, cl::init(true),
58
         cl::desc("Enable use of a base pointer for complex stack frames"));
59
60
static cl::opt<bool>
61
AlwaysBasePointer("ppc-always-use-base-pointer", cl::Hidden, cl::init(false),
62
         cl::desc("Force the use of a base pointer in every function"));
63
64
static cl::opt<bool>
65
EnableGPRToVecSpills("ppc-enable-gpr-to-vsr-spills", cl::Hidden, cl::init(false),
66
         cl::desc("Enable spills from gpr to vsr rather than stack"));
67
68
PPCRegisterInfo::PPCRegisterInfo(const PPCTargetMachine &TM)
69
  : PPCGenRegisterInfo(TM.isPPC64() ? PPC::LR8 : PPC::LR,
70
                       TM.isPPC64() ? 0 : 1,
71
                       TM.isPPC64() ? 0 : 1),
72
1.40k
    TM(TM) {
73
1.40k
  ImmToIdxMap[PPC::LD]   = PPC::LDX;    ImmToIdxMap[PPC::STD]  = PPC::STDX;
74
1.40k
  ImmToIdxMap[PPC::LBZ]  = PPC::LBZX;   ImmToIdxMap[PPC::STB]  = PPC::STBX;
75
1.40k
  ImmToIdxMap[PPC::LHZ]  = PPC::LHZX;   ImmToIdxMap[PPC::LHA]  = PPC::LHAX;
76
1.40k
  ImmToIdxMap[PPC::LWZ]  = PPC::LWZX;   ImmToIdxMap[PPC::LWA]  = PPC::LWAX;
77
1.40k
  ImmToIdxMap[PPC::LFS]  = PPC::LFSX;   ImmToIdxMap[PPC::LFD]  = PPC::LFDX;
78
1.40k
  ImmToIdxMap[PPC::STH]  = PPC::STHX;   ImmToIdxMap[PPC::STW]  = PPC::STWX;
79
1.40k
  ImmToIdxMap[PPC::STFS] = PPC::STFSX;  ImmToIdxMap[PPC::STFD] = PPC::STFDX;
80
1.40k
  ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
81
1.40k
  ImmToIdxMap[PPC::LWA_32] = PPC::LWAX_32;
82
1.40k
83
1.40k
  // 64-bit
84
1.40k
  ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8;
85
1.40k
  ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8;
86
1.40k
  ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8;
87
1.40k
  ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX;
88
1.40k
  ImmToIdxMap[PPC::ADDI8] = PPC::ADD8;
89
1.40k
90
1.40k
  // VSX
91
1.40k
  ImmToIdxMap[PPC::DFLOADf32] = PPC::LXSSPX;
92
1.40k
  ImmToIdxMap[PPC::DFLOADf64] = PPC::LXSDX;
93
1.40k
  ImmToIdxMap[PPC::SPILLTOVSR_LD] = PPC::SPILLTOVSR_LDX;
94
1.40k
  ImmToIdxMap[PPC::SPILLTOVSR_ST] = PPC::SPILLTOVSR_STX;
95
1.40k
  ImmToIdxMap[PPC::DFSTOREf32] = PPC::STXSSPX;
96
1.40k
  ImmToIdxMap[PPC::DFSTOREf64] = PPC::STXSDX;
97
1.40k
  ImmToIdxMap[PPC::LXV] = PPC::LXVX;
98
1.40k
  ImmToIdxMap[PPC::LXSD] = PPC::LXSDX;
99
1.40k
  ImmToIdxMap[PPC::LXSSP] = PPC::LXSSPX;
100
1.40k
  ImmToIdxMap[PPC::STXV] = PPC::STXVX;
101
1.40k
  ImmToIdxMap[PPC::STXSD] = PPC::STXSDX;
102
1.40k
  ImmToIdxMap[PPC::STXSSP] = PPC::STXSSPX;
103
1.40k
}
104
105
/// getPointerRegClass - Return the register class to use to hold pointers.
106
/// This is used for addressing modes.
107
const TargetRegisterClass *
108
PPCRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
109
403k
                                                                       const {
110
403k
  // Note that PPCInstrInfo::FoldImmediate also directly uses this Kind value
111
403k
  // when it checks for ZERO folding.
112
403k
  if (
Kind == 1403k
) {
113
304k
    if (TM.isPPC64())
114
233k
      return &PPC::G8RC_NOX0RegClass;
115
70.5k
    return &PPC::GPRC_NOR0RegClass;
116
70.5k
  }
117
99.3k
118
99.3k
  
if (99.3k
TM.isPPC64()99.3k
)
119
88.9k
    return &PPC::G8RCRegClass;
120
10.4k
  return &PPC::GPRCRegClass;
121
10.4k
}
122
123
const MCPhysReg*
124
160k
PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
125
160k
  const PPCSubtarget &Subtarget = MF->getSubtarget<PPCSubtarget>();
126
160k
  if (
MF->getFunction()->getCallingConv() == CallingConv::AnyReg160k
) {
127
0
    if (Subtarget.hasVSX())
128
0
      return CSR_64_AllRegs_VSX_SaveList;
129
0
    
if (0
Subtarget.hasAltivec()0
)
130
0
      return CSR_64_AllRegs_Altivec_SaveList;
131
0
    return CSR_64_AllRegs_SaveList;
132
0
  }
133
160k
134
160k
  
if (160k
Subtarget.isDarwinABI()160k
)
135
6.53k
    return TM.isPPC64()
136
1.10k
               ? 
(Subtarget.hasAltivec() ? 1.10k
CSR_Darwin64_Altivec_SaveList127
137
1.10k
                                         : CSR_Darwin64_SaveList)
138
5.42k
               : 
(Subtarget.hasAltivec() ? 5.42k
CSR_Darwin32_Altivec_SaveList1.18k
139
6.53k
                                         : CSR_Darwin32_SaveList);
140
153k
141
153k
  
if (153k
TM.isPPC64() && 153k
MF->getInfo<PPCFunctionInfo>()->isSplitCSR()139k
)
142
86
    return CSR_SRV464_TLS_PE_SaveList;
143
153k
144
153k
  // On PPC64, we might need to save r2 (but only if it is not reserved).
145
153k
  bool SaveR2 = MF->getRegInfo().isAllocatable(PPC::X2);
146
153k
147
153k
  return TM.isPPC64()
148
139k
             ? (Subtarget.hasAltivec()
149
115k
                    ? 
(SaveR2 ? 115k
CSR_SVR464_R2_Altivec_SaveList79.9k
150
115k
                              : CSR_SVR464_Altivec_SaveList)
151
139k
                    : 
(SaveR2 ? 23.8k
CSR_SVR464_R2_SaveList13.1k
:
CSR_SVR464_SaveList10.7k
))
152
14.1k
             : 
(Subtarget.hasAltivec() ? 14.1k
CSR_SVR432_Altivec_SaveList3.06k
153
14.1k
                                       : CSR_SVR432_SaveList);
154
160k
}
155
156
const MCPhysReg *
157
6.95k
PPCRegisterInfo::getCalleeSavedRegsViaCopy(const MachineFunction *MF) const {
158
6.95k
  assert(MF && "Invalid MachineFunction pointer.");
159
6.95k
  const PPCSubtarget &Subtarget = MF->getSubtarget<PPCSubtarget>();
160
6.95k
  if (Subtarget.isDarwinABI())
161
261
    return nullptr;
162
6.69k
  
if (6.69k
!TM.isPPC64()6.69k
)
163
716
    return nullptr;
164
5.98k
  
if (5.98k
MF->getFunction()->getCallingConv() != CallingConv::CXX_FAST_TLS5.98k
)
165
5.97k
    return nullptr;
166
6
  
if (6
!MF->getInfo<PPCFunctionInfo>()->isSplitCSR()6
)
167
0
    return nullptr;
168
6
169
6
  // On PPC64, we might need to save r2 (but only if it is not reserved).
170
6
  bool SaveR2 = !getReservedRegs(*MF).test(PPC::X2);
171
6
  if (Subtarget.hasAltivec())
172
6
    return SaveR2
173
4
      ? CSR_SVR464_R2_Altivec_ViaCopy_SaveList
174
2
      : CSR_SVR464_Altivec_ViaCopy_SaveList;
175
6
  else
176
0
    return SaveR2
177
0
      ? CSR_SVR464_R2_ViaCopy_SaveList
178
0
      : CSR_SVR464_ViaCopy_SaveList;
179
0
}
180
181
const uint32_t *
182
PPCRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
183
1.63k
                                      CallingConv::ID CC) const {
184
1.63k
  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
185
1.63k
  if (
CC == CallingConv::AnyReg1.63k
) {
186
10
    if (Subtarget.hasVSX())
187
0
      return CSR_64_AllRegs_VSX_RegMask;
188
10
    
if (10
Subtarget.hasAltivec()10
)
189
0
      return CSR_64_AllRegs_Altivec_RegMask;
190
10
    return CSR_64_AllRegs_RegMask;
191
10
  }
192
1.62k
193
1.62k
  
if (1.62k
Subtarget.isDarwinABI()1.62k
)
194
119
    
return TM.isPPC64() ? 119
(Subtarget.hasAltivec() ? 20
CSR_Darwin64_Altivec_RegMask2
195
20
                                                  : CSR_Darwin64_RegMask)
196
99
                        : 
(Subtarget.hasAltivec() ? 99
CSR_Darwin32_Altivec_RegMask30
197
119
                                                  : CSR_Darwin32_RegMask);
198
1.50k
199
1.50k
  
return TM.isPPC64() ? 1.50k
(Subtarget.hasAltivec() ? 1.26k
CSR_SVR464_Altivec_RegMask927
200
1.26k
                                                : CSR_SVR464_RegMask)
201
232
                      : 
(Subtarget.hasAltivec() ? 232
CSR_SVR432_Altivec_RegMask17
202
232
                                                : CSR_SVR432_RegMask);
203
1.63k
}
204
205
const uint32_t*
206
6
PPCRegisterInfo::getNoPreservedMask() const {
207
6
  return CSR_NoRegs_RegMask;
208
6
}
209
210
39
void PPCRegisterInfo::adjustStackMapLiveOutMask(uint32_t *Mask) const {
211
39
  for (unsigned PseudoReg : {PPC::ZERO, PPC::ZERO8, PPC::RM})
212
117
    Mask[PseudoReg / 32] &= ~(1u << (PseudoReg % 32));
213
39
}
214
215
25.5k
BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
216
25.5k
  BitVector Reserved(getNumRegs());
217
25.5k
  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
218
25.5k
  const PPCFrameLowering *TFI = getFrameLowering(MF);
219
25.5k
220
25.5k
  // The ZERO register is not really a register, but the representation of r0
221
25.5k
  // when used in instructions that treat r0 as the constant 0.
222
25.5k
  markSuperRegs(Reserved, PPC::ZERO);
223
25.5k
224
25.5k
  // The FP register is also not really a register, but is the representation
225
25.5k
  // of the frame pointer register used by ISD::FRAMEADDR.
226
25.5k
  markSuperRegs(Reserved, PPC::FP);
227
25.5k
228
25.5k
  // The BP register is also not really a register, but is the representation
229
25.5k
  // of the base pointer register used by setjmp.
230
25.5k
  markSuperRegs(Reserved, PPC::BP);
231
25.5k
232
25.5k
  // The counter registers must be reserved so that counter-based loops can
233
25.5k
  // be correctly formed (and the mtctr instructions are not DCE'd).
234
25.5k
  markSuperRegs(Reserved, PPC::CTR);
235
25.5k
  markSuperRegs(Reserved, PPC::CTR8);
236
25.5k
237
25.5k
  markSuperRegs(Reserved, PPC::R1);
238
25.5k
  markSuperRegs(Reserved, PPC::LR);
239
25.5k
  markSuperRegs(Reserved, PPC::LR8);
240
25.5k
  markSuperRegs(Reserved, PPC::RM);
241
25.5k
242
25.5k
  if (
!Subtarget.isDarwinABI() || 25.5k
!Subtarget.hasAltivec()796
)
243
25.4k
    markSuperRegs(Reserved, PPC::VRSAVE);
244
25.5k
245
25.5k
  // The SVR4 ABI reserves r2 and r13
246
25.5k
  if (
Subtarget.isSVR4ABI()25.5k
) {
247
24.7k
    // We only reserve r2 if we need to use the TOC pointer. If we have no
248
24.7k
    // explicit uses of the TOC pointer (meaning we're a leaf function with
249
24.7k
    // no constant-pool loads, etc.) and we have no potential uses inside an
250
24.7k
    // inline asm block, then we can treat r2 has an ordinary callee-saved
251
24.7k
    // register.
252
24.7k
    const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
253
24.7k
    if (
!TM.isPPC64() || 24.7k
FuncInfo->usesTOCBasePtr()22.4k
||
MF.hasInlineAsm()16.0k
)
254
9.17k
      markSuperRegs(Reserved, PPC::R2);  // System-reserved register
255
24.7k
    markSuperRegs(Reserved, PPC::R13); // Small Data Area pointer register
256
24.7k
  }
257
25.5k
258
25.5k
  // On PPC64, r13 is the thread pointer. Never allocate this register.
259
25.5k
  if (TM.isPPC64())
260
22.6k
    markSuperRegs(Reserved, PPC::R13);
261
25.5k
262
25.5k
  if (TFI->needsFP(MF))
263
673
    markSuperRegs(Reserved, PPC::R31);
264
25.5k
265
25.5k
  bool IsPositionIndependent = TM.isPositionIndependent();
266
25.5k
  if (
hasBasePointer(MF)25.5k
) {
267
183
    if (
Subtarget.isSVR4ABI() && 183
!TM.isPPC64()183
&&
IsPositionIndependent75
)
268
29
      markSuperRegs(Reserved, PPC::R29);
269
183
    else
270
154
      markSuperRegs(Reserved, PPC::R30);
271
183
  }
272
25.5k
273
25.5k
  if (
Subtarget.isSVR4ABI() && 25.5k
!TM.isPPC64()24.7k
&&
IsPositionIndependent2.31k
)
274
89
    markSuperRegs(Reserved, PPC::R30);
275
25.5k
276
25.5k
  // Reserve Altivec registers when Altivec is unavailable.
277
25.5k
  if (!Subtarget.hasAltivec())
278
5.33k
    for (TargetRegisterClass::iterator I = PPC::VRRCRegClass.begin(),
279
175k
         IE = PPC::VRRCRegClass.end(); 
I != IE175k
;
++I170k
)
280
170k
      markSuperRegs(Reserved, *I);
281
25.5k
282
25.5k
  assert(checkAllSuperRegsMarked(Reserved));
283
25.5k
  return Reserved;
284
25.5k
}
285
286
bool PPCRegisterInfo::isCallerPreservedPhysReg(unsigned PhysReg,
287
381
                                               const MachineFunction &MF) const {
288
381
  assert(TargetRegisterInfo::isPhysicalRegister(PhysReg));
289
381
  if (
TM.isELFv2ABI() && 381
PhysReg == PPC::X2141
) {
290
5
    // X2 is guaranteed to be preserved within a function if it is reserved.
291
5
    // The reason it's reserved is that it's the TOC pointer (and the function
292
5
    // uses the TOC). In functions where it isn't reserved (i.e. leaf functions
293
5
    // with no TOC access), we can't claim that it is preserved.
294
5
    return (getReservedRegs(MF).test(PPC::X2));
295
0
  } else {
296
376
    return false;
297
376
  }
298
0
}
299
300
unsigned PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
301
77.5k
                                              MachineFunction &MF) const {
302
77.5k
  const PPCFrameLowering *TFI = getFrameLowering(MF);
303
77.5k
  const unsigned DefaultSafety = 1;
304
77.5k
305
77.5k
  switch (RC->getID()) {
306
39.9k
  default:
307
39.9k
    return 0;
308
9.39k
  case PPC::G8RC_NOX0RegClassID:
309
9.39k
  case PPC::GPRC_NOR0RegClassID:
310
9.39k
  case PPC::G8RCRegClassID:
311
9.39k
  case PPC::GPRCRegClassID: {
312
9.39k
    unsigned FP = TFI->hasFP(MF) ? 
10
:
09.39k
;
313
9.39k
    return 32 - FP - DefaultSafety;
314
9.39k
  }
315
18.7k
  case PPC::F8RCRegClassID:
316
18.7k
  case PPC::F4RCRegClassID:
317
18.7k
  case PPC::QFRCRegClassID:
318
18.7k
  case PPC::QSRCRegClassID:
319
18.7k
  case PPC::QBRCRegClassID:
320
18.7k
  case PPC::VRRCRegClassID:
321
18.7k
  case PPC::VFRCRegClassID:
322
18.7k
  case PPC::VSLRCRegClassID:
323
18.7k
    return 32 - DefaultSafety;
324
7.04k
  case PPC::VSRCRegClassID:
325
7.04k
  case PPC::VSFRCRegClassID:
326
7.04k
  case PPC::VSSRCRegClassID:
327
7.04k
    return 64 - DefaultSafety;
328
2.34k
  case PPC::CRRCRegClassID:
329
2.34k
    return 8 - DefaultSafety;
330
0
  }
331
0
}
332
333
const TargetRegisterClass *
334
PPCRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
335
46.0k
                                           const MachineFunction &MF) const {
336
46.0k
  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
337
46.0k
  if (
Subtarget.hasVSX()46.0k
) {
338
34.7k
    // With VSX, we can inflate various sub-register classes to the full VSX
339
34.7k
    // register set.
340
34.7k
341
34.7k
    // For Power9 we allow the user to enable GPR to vector spills.
342
34.7k
    // FIXME: Currently limited to spilling GP8RC. A follow on patch will add
343
34.7k
    // support to spill GPRC.
344
34.7k
    if (
TM.isELFv2ABI()34.7k
) {
345
13.2k
      if (
Subtarget.hasP9Vector() && 13.2k
EnableGPRToVecSpills3.06k
&&
346
13.2k
          
RC == &PPC::G8RCRegClass64
) {
347
37
        InflateGP8RC++;
348
37
        return &PPC::SPILLTOVSRRCRegClass;
349
37
      }
350
13.1k
      
if (13.1k
RC == &PPC::GPRCRegClass && 13.1k
EnableGPRToVecSpills890
)
351
4
        InflateGPRC++;
352
13.2k
    }
353
34.7k
    
if (34.7k
RC == &PPC::F8RCRegClass34.7k
)
354
113
      return &PPC::VSFRCRegClass;
355
34.5k
    else 
if (34.5k
RC == &PPC::VRRCRegClass34.5k
)
356
1.39k
      return &PPC::VSRCRegClass;
357
33.2k
    else 
if (33.2k
RC == &PPC::F4RCRegClass && 33.2k
Subtarget.hasP8Vector()562
)
358
377
      return &PPC::VSSRCRegClass;
359
44.1k
  }
360
44.1k
361
44.1k
  return TargetRegisterInfo::getLargestLegalSuperClass(RC, MF);
362
44.1k
}
363
364
//===----------------------------------------------------------------------===//
365
// Stack Frame Processing methods
366
//===----------------------------------------------------------------------===//
367
368
/// lowerDynamicAlloc - Generate the code for allocating an object in the
369
/// current frame.  The sequence of code will be in the general form
370
///
371
///   addi   R0, SP, \#frameSize ; get the address of the previous frame
372
///   stwxu  R0, SP, Rnegsize   ; add and update the SP with the negated size
373
///   addi   Rnew, SP, \#maxCalFrameSize ; get the top of the allocation
374
///
375
22
void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const {
376
22
  // Get the instruction.
377
22
  MachineInstr &MI = *II;
378
22
  // Get the instruction's basic block.
379
22
  MachineBasicBlock &MBB = *MI.getParent();
380
22
  // Get the basic block's function.
381
22
  MachineFunction &MF = *MBB.getParent();
382
22
  // Get the frame info.
383
22
  MachineFrameInfo &MFI = MF.getFrameInfo();
384
22
  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
385
22
  // Get the instruction info.
386
22
  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
387
22
  // Determine whether 64-bit pointers are used.
388
22
  bool LP64 = TM.isPPC64();
389
22
  DebugLoc dl = MI.getDebugLoc();
390
22
391
22
  // Get the maximum call stack size.
392
22
  unsigned maxCallFrameSize = MFI.getMaxCallFrameSize();
393
22
  // Get the total frame size.
394
22
  unsigned FrameSize = MFI.getStackSize();
395
22
396
22
  // Get stack alignments.
397
22
  const PPCFrameLowering *TFI = getFrameLowering(MF);
398
22
  unsigned TargetAlign = TFI->getStackAlignment();
399
22
  unsigned MaxAlign = MFI.getMaxAlignment();
400
22
  assert((maxCallFrameSize & (MaxAlign-1)) == 0 &&
401
22
         "Maximum call-frame size not sufficiently aligned");
402
22
403
22
  // Determine the previous frame's address.  If FrameSize can't be
404
22
  // represented as 16 bits or we need special alignment, then we load the
405
22
  // previous frame's address from 0(SP).  Why not do an addis of the hi?
406
22
  // Because R0 is our only safe tmp register and addi/addis treat R0 as zero.
407
22
  // Constructing the constant and adding would take 3 instructions.
408
22
  // Fortunately, a frame greater than 32K is rare.
409
22
  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
410
22
  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
411
22
  unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? 
G8RC13
:
GPRC9
);
412
22
413
22
  if (
MaxAlign < TargetAlign && 22
isInt<16>(FrameSize)18
) {
414
17
    if (LP64)
415
11
      BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), Reg)
416
11
        .addReg(PPC::X31)
417
11
        .addImm(FrameSize);
418
17
    else
419
6
      BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg)
420
6
        .addReg(PPC::R31)
421
6
        .addImm(FrameSize);
422
22
  } else 
if (5
LP645
) {
423
2
    BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg)
424
2
      .addImm(0)
425
2
      .addReg(PPC::X1);
426
5
  } else {
427
3
    BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg)
428
3
      .addImm(0)
429
3
      .addReg(PPC::R1);
430
3
  }
431
22
432
22
  bool KillNegSizeReg = MI.getOperand(1).isKill();
433
22
  unsigned NegSizeReg = MI.getOperand(1).getReg();
434
22
435
22
  // Grow the stack and update the stack pointer link, then determine the
436
22
  // address of new allocated space.
437
22
  if (
LP6422
) {
438
13
    if (
MaxAlign > TargetAlign13
) {
439
2
      unsigned UnalNegSizeReg = NegSizeReg;
440
2
      NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC);
441
2
442
2
      // Unfortunately, there is no andi, only andi., and we can't insert that
443
2
      // here because we might clobber cr0 while it is live.
444
2
      BuildMI(MBB, II, dl, TII.get(PPC::LI8), NegSizeReg)
445
2
        .addImm(~(MaxAlign-1));
446
2
447
2
      unsigned NegSizeReg1 = NegSizeReg;
448
2
      NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC);
449
2
      BuildMI(MBB, II, dl, TII.get(PPC::AND8), NegSizeReg)
450
2
        .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg))
451
2
        .addReg(NegSizeReg1, RegState::Kill);
452
2
      KillNegSizeReg = true;
453
2
    }
454
13
455
13
    BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1)
456
13
      .addReg(Reg, RegState::Kill)
457
13
      .addReg(PPC::X1)
458
13
      .addReg(NegSizeReg, getKillRegState(KillNegSizeReg));
459
13
    BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
460
13
      .addReg(PPC::X1)
461
13
      .addImm(maxCallFrameSize);
462
22
  } else {
463
9
    if (
MaxAlign > TargetAlign9
) {
464
2
      unsigned UnalNegSizeReg = NegSizeReg;
465
2
      NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC);
466
2
467
2
      // Unfortunately, there is no andi, only andi., and we can't insert that
468
2
      // here because we might clobber cr0 while it is live.
469
2
      BuildMI(MBB, II, dl, TII.get(PPC::LI), NegSizeReg)
470
2
        .addImm(~(MaxAlign-1));
471
2
472
2
      unsigned NegSizeReg1 = NegSizeReg;
473
2
      NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC);
474
2
      BuildMI(MBB, II, dl, TII.get(PPC::AND), NegSizeReg)
475
2
        .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg))
476
2
        .addReg(NegSizeReg1, RegState::Kill);
477
2
      KillNegSizeReg = true;
478
2
    }
479
9
480
9
    BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1)
481
9
      .addReg(Reg, RegState::Kill)
482
9
      .addReg(PPC::R1)
483
9
      .addReg(NegSizeReg, getKillRegState(KillNegSizeReg));
484
9
    BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
485
9
      .addReg(PPC::R1)
486
9
      .addImm(maxCallFrameSize);
487
9
  }
488
22
489
22
  // Discard the DYNALLOC instruction.
490
22
  MBB.erase(II);
491
22
}
492
493
void PPCRegisterInfo::lowerDynamicAreaOffset(
494
1
    MachineBasicBlock::iterator II) const {
495
1
  // Get the instruction.
496
1
  MachineInstr &MI = *II;
497
1
  // Get the instruction's basic block.
498
1
  MachineBasicBlock &MBB = *MI.getParent();
499
1
  // Get the basic block's function.
500
1
  MachineFunction &MF = *MBB.getParent();
501
1
  // Get the frame info.
502
1
  MachineFrameInfo &MFI = MF.getFrameInfo();
503
1
  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
504
1
  // Get the instruction info.
505
1
  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
506
1
507
1
  unsigned maxCallFrameSize = MFI.getMaxCallFrameSize();
508
1
  bool is64Bit = TM.isPPC64();
509
1
  DebugLoc dl = MI.getDebugLoc();
510
1
  BuildMI(MBB, II, dl, TII.get(is64Bit ? 
PPC::LI81
:
PPC::LI0
),
511
1
          MI.getOperand(0).getReg())
512
1
      .addImm(maxCallFrameSize);
513
1
  MBB.erase(II);
514
1
}
515
516
/// lowerCRSpilling - Generate the code for spilling a CR register. Instead of
517
/// reserving a whole register (R0), we scrounge for one here. This generates
518
/// code like this:
519
///
520
///   mfcr rA                  ; Move the conditional register into GPR rA.
521
///   rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot.
522
///   stw rA, FI               ; Store rA to the frame.
523
///
524
void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II,
525
39
                                      unsigned FrameIndex) const {
526
39
  // Get the instruction.
527
39
  MachineInstr &MI = *II;       // ; SPILL_CR <SrcReg>, <offset>
528
39
  // Get the instruction's basic block.
529
39
  MachineBasicBlock &MBB = *MI.getParent();
530
39
  MachineFunction &MF = *MBB.getParent();
531
39
  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
532
39
  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
533
39
  DebugLoc dl = MI.getDebugLoc();
534
39
535
39
  bool LP64 = TM.isPPC64();
536
39
  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
537
39
  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
538
39
539
39
  unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? 
G8RC17
:
GPRC22
);
540
39
  unsigned SrcReg = MI.getOperand(0).getReg();
541
39
542
39
  // We need to store the CR in the low 4-bits of the saved value. First, issue
543
39
  // an MFOCRF to save all of the CRBits and, if needed, kill the SrcReg.
544
39
  BuildMI(MBB, II, dl, TII.get(LP64 ? 
PPC::MFOCRF817
:
PPC::MFOCRF22
), Reg)
545
39
      .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
546
39
547
39
  // If the saved register wasn't CR0, shift the bits left so that they are in
548
39
  // CR0's slot.
549
39
  if (
SrcReg != PPC::CR039
) {
550
16
    unsigned Reg1 = Reg;
551
16
    Reg = MF.getRegInfo().createVirtualRegister(LP64 ? 
G8RC5
:
GPRC11
);
552
16
553
16
    // rlwinm rA, rA, ShiftBits, 0, 31.
554
16
    BuildMI(MBB, II, dl, TII.get(LP64 ? 
PPC::RLWINM85
:
PPC::RLWINM11
), Reg)
555
16
      .addReg(Reg1, RegState::Kill)
556
16
      .addImm(getEncodingValue(SrcReg) * 4)
557
16
      .addImm(0)
558
16
      .addImm(31);
559
16
  }
560
39
561
39
  addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? 
PPC::STW817
:
PPC::STW22
))
562
39
                    .addReg(Reg, RegState::Kill),
563
39
                    FrameIndex);
564
39
565
39
  // Discard the pseudo instruction.
566
39
  MBB.erase(II);
567
39
}
568
569
void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II,
570
47
                                      unsigned FrameIndex) const {
571
47
  // Get the instruction.
572
47
  MachineInstr &MI = *II;       // ; <DestReg> = RESTORE_CR <offset>
573
47
  // Get the instruction's basic block.
574
47
  MachineBasicBlock &MBB = *MI.getParent();
575
47
  MachineFunction &MF = *MBB.getParent();
576
47
  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
577
47
  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
578
47
  DebugLoc dl = MI.getDebugLoc();
579
47
580
47
  bool LP64 = TM.isPPC64();
581
47
  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
582
47
  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
583
47
584
47
  unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? 
G8RC21
:
GPRC26
);
585
47
  unsigned DestReg = MI.getOperand(0).getReg();
586
47
  assert(MI.definesRegister(DestReg) &&
587
47
    "RESTORE_CR does not define its destination");
588
47
589
47
  addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? 
PPC::LWZ821
:
PPC::LWZ26
),
590
47
                              Reg), FrameIndex);
591
47
592
47
  // If the reloaded register isn't CR0, shift the bits right so that they are
593
47
  // in the right CR's slot.
594
47
  if (
DestReg != PPC::CR047
) {
595
39
    unsigned Reg1 = Reg;
596
39
    Reg = MF.getRegInfo().createVirtualRegister(LP64 ? 
G8RC16
:
GPRC23
);
597
39
598
39
    unsigned ShiftBits = getEncodingValue(DestReg)*4;
599
39
    // rlwinm r11, r11, 32-ShiftBits, 0, 31.
600
39
    BuildMI(MBB, II, dl, TII.get(LP64 ? 
PPC::RLWINM816
:
PPC::RLWINM23
), Reg)
601
39
             .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0)
602
39
             .addImm(31);
603
39
  }
604
47
605
47
  BuildMI(MBB, II, dl, TII.get(LP64 ? 
PPC::MTOCRF821
:
PPC::MTOCRF26
), DestReg)
606
47
             .addReg(Reg, RegState::Kill);
607
47
608
47
  // Discard the pseudo instruction.
609
47
  MBB.erase(II);
610
47
}
611
612
void PPCRegisterInfo::lowerCRBitSpilling(MachineBasicBlock::iterator II,
613
8
                                         unsigned FrameIndex) const {
614
8
  // Get the instruction.
615
8
  MachineInstr &MI = *II;       // ; SPILL_CRBIT <SrcReg>, <offset>
616
8
  // Get the instruction's basic block.
617
8
  MachineBasicBlock &MBB = *MI.getParent();
618
8
  MachineFunction &MF = *MBB.getParent();
619
8
  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
620
8
  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
621
8
  DebugLoc dl = MI.getDebugLoc();
622
8
623
8
  bool LP64 = TM.isPPC64();
624
8
  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
625
8
  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
626
8
627
8
  unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? 
G8RC4
:
GPRC4
);
628
8
  unsigned SrcReg = MI.getOperand(0).getReg();
629
8
630
8
  BuildMI(MBB, II, dl, TII.get(TargetOpcode::KILL),
631
8
          getCRFromCRBit(SrcReg))
632
8
          .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
633
8
634
8
  BuildMI(MBB, II, dl, TII.get(LP64 ? 
PPC::MFOCRF84
:
PPC::MFOCRF4
), Reg)
635
8
      .addReg(getCRFromCRBit(SrcReg));
636
8
637
8
  // If the saved register wasn't CR0LT, shift the bits left so that the bit to
638
8
  // store is the first one. Mask all but that bit.
639
8
  unsigned Reg1 = Reg;
640
8
  Reg = MF.getRegInfo().createVirtualRegister(LP64 ? 
G8RC4
:
GPRC4
);
641
8
642
8
  // rlwinm rA, rA, ShiftBits, 0, 0.
643
8
  BuildMI(MBB, II, dl, TII.get(LP64 ? 
PPC::RLWINM84
:
PPC::RLWINM4
), Reg)
644
8
    .addReg(Reg1, RegState::Kill)
645
8
    .addImm(getEncodingValue(SrcReg))
646
8
    .addImm(0).addImm(0);
647
8
648
8
  addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? 
PPC::STW84
:
PPC::STW4
))
649
8
                    .addReg(Reg, RegState::Kill),
650
8
                    FrameIndex);
651
8
652
8
  // Discard the pseudo instruction.
653
8
  MBB.erase(II);
654
8
}
655
656
void PPCRegisterInfo::lowerCRBitRestore(MachineBasicBlock::iterator II,
657
8
                                      unsigned FrameIndex) const {
658
8
  // Get the instruction.
659
8
  MachineInstr &MI = *II;       // ; <DestReg> = RESTORE_CRBIT <offset>
660
8
  // Get the instruction's basic block.
661
8
  MachineBasicBlock &MBB = *MI.getParent();
662
8
  MachineFunction &MF = *MBB.getParent();
663
8
  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
664
8
  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
665
8
  DebugLoc dl = MI.getDebugLoc();
666
8
667
8
  bool LP64 = TM.isPPC64();
668
8
  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
669
8
  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
670
8
671
8
  unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? 
G8RC4
:
GPRC4
);
672
8
  unsigned DestReg = MI.getOperand(0).getReg();
673
8
  assert(MI.definesRegister(DestReg) &&
674
8
    "RESTORE_CRBIT does not define its destination");
675
8
676
8
  addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? 
PPC::LWZ84
:
PPC::LWZ4
),
677
8
                              Reg), FrameIndex);
678
8
679
8
  BuildMI(MBB, II, dl, TII.get(TargetOpcode::IMPLICIT_DEF), DestReg);
680
8
681
8
  unsigned RegO = MF.getRegInfo().createVirtualRegister(LP64 ? 
G8RC4
:
GPRC4
);
682
8
  BuildMI(MBB, II, dl, TII.get(LP64 ? 
PPC::MFOCRF84
:
PPC::MFOCRF4
), RegO)
683
8
          .addReg(getCRFromCRBit(DestReg));
684
8
685
8
  unsigned ShiftBits = getEncodingValue(DestReg);
686
8
  // rlwimi r11, r10, 32-ShiftBits, ..., ...
687
8
  BuildMI(MBB, II, dl, TII.get(LP64 ? 
PPC::RLWIMI84
:
PPC::RLWIMI4
), RegO)
688
8
      .addReg(RegO, RegState::Kill)
689
8
      .addReg(Reg, RegState::Kill)
690
8
      .addImm(ShiftBits ? 
32 - ShiftBits8
:
00
)
691
8
      .addImm(ShiftBits)
692
8
      .addImm(ShiftBits);
693
8
694
8
  BuildMI(MBB, II, dl, TII.get(LP64 ? 
PPC::MTOCRF84
:
PPC::MTOCRF4
),
695
8
          getCRFromCRBit(DestReg))
696
8
      .addReg(RegO, RegState::Kill)
697
8
      // Make sure we have a use dependency all the way through this
698
8
      // sequence of instructions. We can't have the other bits in the CR
699
8
      // modified in between the mfocrf and the mtocrf.
700
8
      .addReg(getCRFromCRBit(DestReg), RegState::Implicit);
701
8
702
8
  // Discard the pseudo instruction.
703
8
  MBB.erase(II);
704
8
}
705
706
void PPCRegisterInfo::lowerVRSAVESpilling(MachineBasicBlock::iterator II,
707
0
                                          unsigned FrameIndex) const {
708
0
  // Get the instruction.
709
0
  MachineInstr &MI = *II;       // ; SPILL_VRSAVE <SrcReg>, <offset>
710
0
  // Get the instruction's basic block.
711
0
  MachineBasicBlock &MBB = *MI.getParent();
712
0
  MachineFunction &MF = *MBB.getParent();
713
0
  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
714
0
  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
715
0
  DebugLoc dl = MI.getDebugLoc();
716
0
717
0
  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
718
0
  unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC);
719
0
  unsigned SrcReg = MI.getOperand(0).getReg();
720
0
721
0
  BuildMI(MBB, II, dl, TII.get(PPC::MFVRSAVEv), Reg)
722
0
      .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
723
0
724
0
  addFrameReference(
725
0
      BuildMI(MBB, II, dl, TII.get(PPC::STW)).addReg(Reg, RegState::Kill),
726
0
      FrameIndex);
727
0
728
0
  // Discard the pseudo instruction.
729
0
  MBB.erase(II);
730
0
}
731
732
void PPCRegisterInfo::lowerVRSAVERestore(MachineBasicBlock::iterator II,
733
0
                                         unsigned FrameIndex) const {
734
0
  // Get the instruction.
735
0
  MachineInstr &MI = *II;       // ; <DestReg> = RESTORE_VRSAVE <offset>
736
0
  // Get the instruction's basic block.
737
0
  MachineBasicBlock &MBB = *MI.getParent();
738
0
  MachineFunction &MF = *MBB.getParent();
739
0
  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
740
0
  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
741
0
  DebugLoc dl = MI.getDebugLoc();
742
0
743
0
  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
744
0
  unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC);
745
0
  unsigned DestReg = MI.getOperand(0).getReg();
746
0
  assert(MI.definesRegister(DestReg) &&
747
0
    "RESTORE_VRSAVE does not define its destination");
748
0
749
0
  addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::LWZ),
750
0
                              Reg), FrameIndex);
751
0
752
0
  BuildMI(MBB, II, dl, TII.get(PPC::MTVRSAVEv), DestReg)
753
0
             .addReg(Reg, RegState::Kill);
754
0
755
0
  // Discard the pseudo instruction.
756
0
  MBB.erase(II);
757
0
}
758
759
bool PPCRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
760
1.83k
                                           unsigned Reg, int &FrameIdx) const {
761
1.83k
  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
762
1.83k
  // For the nonvolatile condition registers (CR2, CR3, CR4) in an SVR4
763
1.83k
  // ABI, return true to prevent allocating an additional frame slot.
764
1.83k
  // For 64-bit, the CR save area is at SP+8; the value of FrameIdx = 0
765
1.83k
  // is arbitrary and will be subsequently ignored.  For 32-bit, we have
766
1.83k
  // previously created the stack slot if needed, so return its FrameIdx.
767
1.83k
  if (
Subtarget.isSVR4ABI() && 1.83k
PPC::CR2 <= Reg1.75k
&&
Reg <= PPC::CR41.75k
) {
768
70
    if (TM.isPPC64())
769
59
      FrameIdx = 0;
770
11
    else {
771
11
      const PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
772
11
      FrameIdx = FI->getCRSpillFrameIndex();
773
11
    }
774
70
    return true;
775
70
  }
776
1.76k
  return false;
777
1.76k
}
778
779
// If the offset must be a multiple of some value, return what that value is.
780
9.63k
static unsigned offsetMinAlign(const MachineInstr &MI) {
781
9.63k
  unsigned OpC = MI.getOpcode();
782
9.63k
783
9.63k
  switch (OpC) {
784
6.76k
  default:
785
6.76k
    return 1;
786
2.86k
  case PPC::LWA:
787
2.86k
  case PPC::LWA_32:
788
2.86k
  case PPC::LD:
789
2.86k
  case PPC::LDU:
790
2.86k
  case PPC::STD:
791
2.86k
  case PPC::STDU:
792
2.86k
  case PPC::DFLOADf32:
793
2.86k
  case PPC::DFLOADf64:
794
2.86k
  case PPC::DFSTOREf32:
795
2.86k
  case PPC::DFSTOREf64:
796
2.86k
  case PPC::LXSD:
797
2.86k
  case PPC::LXSSP:
798
2.86k
  case PPC::STXSD:
799
2.86k
  case PPC::STXSSP:
800
2.86k
    return 4;
801
1
  case PPC::LXV:
802
1
  case PPC::STXV:
803
1
    return 16;
804
0
  }
805
0
}
806
807
// Return the OffsetOperandNo given the FIOperandNum (and the instruction).
808
static unsigned getOffsetONFromFION(const MachineInstr &MI,
809
10.3k
                                    unsigned FIOperandNum) {
810
10.3k
  // Take into account whether it's an add or mem instruction
811
10.3k
  unsigned OffsetOperandNo = (FIOperandNum == 2) ? 
19.36k
:
21.03k
;
812
10.3k
  if (MI.isInlineAsm())
813
0
    OffsetOperandNo = FIOperandNum - 1;
814
10.3k
  else 
if (10.3k
MI.getOpcode() == TargetOpcode::STACKMAP ||
815
10.3k
           MI.getOpcode() == TargetOpcode::PATCHPOINT)
816
16
    OffsetOperandNo = FIOperandNum + 1;
817
10.3k
818
10.3k
  return OffsetOperandNo;
819
10.3k
}
820
821
void
822
PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
823
                                     int SPAdj, unsigned FIOperandNum,
824
8.46k
                                     RegScavenger *RS) const {
825
8.46k
  assert(SPAdj == 0 && "Unexpected");
826
8.46k
827
8.46k
  // Get the instruction.
828
8.46k
  MachineInstr &MI = *II;
829
8.46k
  // Get the instruction's basic block.
830
8.46k
  MachineBasicBlock &MBB = *MI.getParent();
831
8.46k
  // Get the basic block's function.
832
8.46k
  MachineFunction &MF = *MBB.getParent();
833
8.46k
  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
834
8.46k
  // Get the instruction info.
835
8.46k
  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
836
8.46k
  // Get the frame info.
837
8.46k
  MachineFrameInfo &MFI = MF.getFrameInfo();
838
8.46k
  DebugLoc dl = MI.getDebugLoc();
839
8.46k
840
8.46k
  unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum);
841
8.46k
842
8.46k
  // Get the frame index.
843
8.46k
  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
844
8.46k
845
8.46k
  // Get the frame pointer save index.  Users of this index are primarily
846
8.46k
  // DYNALLOC instructions.
847
8.46k
  PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
848
8.46k
  int FPSI = FI->getFramePointerSaveIndex();
849
8.46k
  // Get the instruction opcode.
850
8.46k
  unsigned OpC = MI.getOpcode();
851
8.46k
852
8.46k
  if (
(OpC == PPC::DYNAREAOFFSET || 8.46k
OpC == PPC::DYNAREAOFFSET88.46k
)) {
853
1
    lowerDynamicAreaOffset(II);
854
1
    return;
855
1
  }
856
8.46k
857
8.46k
  // Special case for dynamic alloca.
858
8.46k
  
if (8.46k
FPSI && 8.46k
FrameIndex == FPSI1.05k
&&
859
8.46k
      
(OpC == PPC::DYNALLOC || 22
OpC == PPC::DYNALLOC813
)) {
860
22
    lowerDynamicAlloc(II);
861
22
    return;
862
22
  }
863
8.44k
864
8.44k
  // Special case for pseudo-ops SPILL_CR and RESTORE_CR, etc.
865
8.44k
  
if (8.44k
OpC == PPC::SPILL_CR8.44k
) {
866
39
    lowerCRSpilling(II, FrameIndex);
867
39
    return;
868
8.40k
  } else 
if (8.40k
OpC == PPC::RESTORE_CR8.40k
) {
869
47
    lowerCRRestore(II, FrameIndex);
870
47
    return;
871
8.35k
  } else 
if (8.35k
OpC == PPC::SPILL_CRBIT8.35k
) {
872
8
    lowerCRBitSpilling(II, FrameIndex);
873
8
    return;
874
8.34k
  } else 
if (8.34k
OpC == PPC::RESTORE_CRBIT8.34k
) {
875
8
    lowerCRBitRestore(II, FrameIndex);
876
8
    return;
877
8.33k
  } else 
if (8.33k
OpC == PPC::SPILL_VRSAVE8.33k
) {
878
0
    lowerVRSAVESpilling(II, FrameIndex);
879
0
    return;
880
8.33k
  } else 
if (8.33k
OpC == PPC::RESTORE_VRSAVE8.33k
) {
881
0
    lowerVRSAVERestore(II, FrameIndex);
882
0
    return;
883
0
  }
884
8.33k
885
8.33k
  // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
886
8.33k
  MI.getOperand(FIOperandNum).ChangeToRegister(
887
8.33k
    FrameIndex < 0 ? 
getBaseRegister(MF)3.89k
:
getFrameRegister(MF)4.44k
, false);
888
8.33k
889
8.33k
  // If the instruction is not present in ImmToIdxMap, then it has no immediate
890
8.33k
  // form (and must be r+r).
891
8.33k
  bool noImmForm = !MI.isInlineAsm() && OpC != TargetOpcode::STACKMAP &&
892
8.33k
                   
OpC != TargetOpcode::PATCHPOINT8.33k
&&
!ImmToIdxMap.count(OpC)8.32k
;
893
8.33k
894
8.33k
  // Now add the frame object offset to the offset from r1.
895
8.33k
  int Offset = MFI.getObjectOffset(FrameIndex);
896
8.33k
  Offset += MI.getOperand(OffsetOperandNo).getImm();
897
8.33k
898
8.33k
  // If we're not using a Frame Pointer that has been set to the value of the
899
8.33k
  // SP before having the stack size subtracted from it, then add the stack size
900
8.33k
  // to Offset to get the correct offset.
901
8.33k
  // Naked functions have stack size 0, although getStackSize may not reflect
902
8.33k
  // that because we didn't call all the pieces that compute it for naked
903
8.33k
  // functions.
904
8.33k
  if (
!MF.getFunction()->hasFnAttribute(Attribute::Naked)8.33k
) {
905
8.33k
    if (
!(hasBasePointer(MF) && 8.33k
FrameIndex < 0273
))
906
8.13k
      Offset += MFI.getStackSize();
907
8.33k
  }
908
8.33k
909
8.33k
  // If we can, encode the offset directly into the instruction.  If this is a
910
8.33k
  // normal PPC "ri" instruction, any 16-bit value can be safely encoded.  If
911
8.33k
  // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits
912
8.33k
  // clear can be encoded.  This is extremely uncommon, because normally you
913
8.33k
  // only "std" to a stack slot that is at least 4-byte aligned, but it can
914
8.33k
  // happen in invalid code.
915
8.33k
  assert(OpC != PPC::DBG_VALUE &&
916
8.33k
         "This should be handled in a target-independent way");
917
8.33k
  if (
!noImmForm && 8.33k
((isInt<16>(Offset) &&
918
7.89k
                      ((Offset % offsetMinAlign(MI)) == 0)) ||
919
71
                     OpC == TargetOpcode::STACKMAP ||
920
8.33k
                     
OpC == TargetOpcode::PATCHPOINT71
)) {
921
7.89k
    MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
922
7.89k
    return;
923
7.89k
  }
924
446
925
446
  // The offset doesn't fit into a single register, scavenge one to build the
926
446
  // offset in.
927
446
928
446
  bool is64Bit = TM.isPPC64();
929
446
  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
930
446
  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
931
446
  const TargetRegisterClass *RC = is64Bit ? 
G8RC437
:
GPRC9
;
932
446
  unsigned SRegHi = MF.getRegInfo().createVirtualRegister(RC),
933
446
           SReg = MF.getRegInfo().createVirtualRegister(RC);
934
446
935
446
  // Insert a set of rA with the full offset value before the ld, st, or add
936
446
  BuildMI(MBB, II, dl, TII.get(is64Bit ? 
PPC::LIS8437
:
PPC::LIS9
), SRegHi)
937
446
    .addImm(Offset >> 16);
938
446
  BuildMI(MBB, II, dl, TII.get(is64Bit ? 
PPC::ORI8437
:
PPC::ORI9
), SReg)
939
446
    .addReg(SRegHi, RegState::Kill)
940
446
    .addImm(Offset);
941
446
942
446
  // Convert into indexed form of the instruction:
943
446
  //
944
446
  //   sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
945
446
  //   addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
946
446
  unsigned OperandBase;
947
446
948
446
  if (noImmForm)
949
375
    OperandBase = 1;
950
71
  else 
if (71
OpC != TargetOpcode::INLINEASM71
) {
951
71
    assert(ImmToIdxMap.count(OpC) &&
952
71
           "No indexed form of load or store available!");
953
71
    unsigned NewOpcode = ImmToIdxMap.find(OpC)->second;
954
71
    MI.setDesc(TII.get(NewOpcode));
955
71
    OperandBase = 1;
956
71
  } else {
957
0
    OperandBase = OffsetOperandNo;
958
0
  }
959
8.46k
960
8.46k
  unsigned StackReg = MI.getOperand(FIOperandNum).getReg();
961
8.46k
  MI.getOperand(OperandBase).ChangeToRegister(StackReg, false);
962
8.46k
  MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true);
963
8.46k
}
964
965
24.9k
unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
966
24.9k
  const PPCFrameLowering *TFI = getFrameLowering(MF);
967
24.9k
968
24.9k
  if (!TM.isPPC64())
969
5.13k
    
return TFI->hasFP(MF) ? 5.13k
PPC::R31128
:
PPC::R15.00k
;
970
24.9k
  else
971
19.7k
    
return TFI->hasFP(MF) ? 19.7k
PPC::X31857
:
PPC::X118.9k
;
972
0
}
973
974
20.6k
unsigned PPCRegisterInfo::getBaseRegister(const MachineFunction &MF) const {
975
20.6k
  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
976
20.6k
  if (!hasBasePointer(MF))
977
20.3k
    return getFrameRegister(MF);
978
343
979
343
  
if (343
TM.isPPC64()343
)
980
258
    return PPC::X30;
981
85
982
85
  
if (85
Subtarget.isSVR4ABI() && 85
TM.isPositionIndependent()85
)
983
38
    return PPC::R29;
984
47
985
47
  return PPC::R30;
986
47
}
987
988
113k
bool PPCRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
989
113k
  if (!EnableBasePointer)
990
0
    return false;
991
113k
  
if (113k
AlwaysBasePointer113k
)
992
48
    return true;
993
113k
994
113k
  // If we need to realign the stack, then the stack pointer can no longer
995
113k
  // serve as an offset into the caller's stack space. As a result, we need a
996
113k
  // base pointer.
997
113k
  return needsStackRealignment(MF);
998
113k
}
999
1000
/// Returns true if the instruction's frame index
1001
/// reference would be better served by a base register other than FP
1002
/// or SP. Used by LocalStackFrameAllocation to determine which frame index
1003
/// references it should create new base registers for.
1004
bool PPCRegisterInfo::
1005
3.71k
needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
1006
3.71k
  assert(Offset < 0 && "Local offset must be negative");
1007
3.71k
1008
3.71k
  // It's the load/store FI references that cause issues, as it can be difficult
1009
3.71k
  // to materialize the offset if it won't fit in the literal field. Estimate
1010
3.71k
  // based on the size of the local frame and some conservative assumptions
1011
3.71k
  // about the rest of the stack frame (note, this is pre-regalloc, so
1012
3.71k
  // we don't know everything for certain yet) whether this offset is likely
1013
3.71k
  // to be out of range of the immediate. Return true if so.
1014
3.71k
1015
3.71k
  // We only generate virtual base registers for loads and stores that have
1016
3.71k
  // an r+i form. Return false for everything else.
1017
3.71k
  unsigned OpC = MI->getOpcode();
1018
3.71k
  if (!ImmToIdxMap.count(OpC))
1019
8
    return false;
1020
3.71k
1021
3.71k
  // Don't generate a new virtual base register just to add zero to it.
1022
3.71k
  
if (3.71k
(OpC == PPC::ADDI || 3.71k
OpC == PPC::ADDI83.61k
) &&
1023
784
      MI->getOperand(2).getImm() == 0)
1024
740
    return false;
1025
2.97k
1026
2.97k
  MachineBasicBlock &MBB = *MI->getParent();
1027
2.97k
  MachineFunction &MF = *MBB.getParent();
1028
2.97k
  const PPCFrameLowering *TFI = getFrameLowering(MF);
1029
2.97k
  unsigned StackEst = TFI->determineFrameLayout(MF, false, true);
1030
2.97k
1031
2.97k
  // If we likely don't need a stack frame, then we probably don't need a
1032
2.97k
  // virtual base register either.
1033
2.97k
  if (!StackEst)
1034
1.23k
    return false;
1035
1.74k
1036
1.74k
  // Estimate an offset from the stack pointer.
1037
1.74k
  // The incoming offset is relating to the SP at the start of the function,
1038
1.74k
  // but when we access the local it'll be relative to the SP after local
1039
1.74k
  // allocation, so adjust our SP-relative offset by that allocation size.
1040
1.74k
  Offset += StackEst;
1041
1.74k
1042
1.74k
  // The frame pointer will point to the end of the stack, so estimate the
1043
1.74k
  // offset as the difference between the object offset and the FP location.
1044
1.74k
  return !isFrameOffsetLegal(MI, getBaseRegister(MF), Offset);
1045
1.74k
}
1046
1047
/// Insert defining instruction(s) for BaseReg to
1048
/// be a pointer to FrameIdx at the beginning of the basic block.
1049
void PPCRegisterInfo::
1050
materializeFrameBaseRegister(MachineBasicBlock *MBB,
1051
                             unsigned BaseReg, int FrameIdx,
1052
2
                             int64_t Offset) const {
1053
2
  unsigned ADDriOpc = TM.isPPC64() ? 
PPC::ADDI82
:
PPC::ADDI0
;
1054
2
1055
2
  MachineBasicBlock::iterator Ins = MBB->begin();
1056
2
  DebugLoc DL;                  // Defaults to "unknown"
1057
2
  if (Ins != MBB->end())
1058
2
    DL = Ins->getDebugLoc();
1059
2
1060
2
  const MachineFunction &MF = *MBB->getParent();
1061
2
  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1062
2
  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1063
2
  const MCInstrDesc &MCID = TII.get(ADDriOpc);
1064
2
  MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1065
2
  MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
1066
2
1067
2
  BuildMI(*MBB, Ins, DL, MCID, BaseReg)
1068
2
    .addFrameIndex(FrameIdx).addImm(Offset);
1069
2
}
1070
1071
void PPCRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
1072
96
                                        int64_t Offset) const {
1073
96
  unsigned FIOperandNum = 0;
1074
288
  while (
!MI.getOperand(FIOperandNum).isFI()288
) {
1075
192
    ++FIOperandNum;
1076
192
    assert(FIOperandNum < MI.getNumOperands() &&
1077
192
           "Instr doesn't have FrameIndex operand!");
1078
192
  }
1079
96
1080
96
  MI.getOperand(FIOperandNum).ChangeToRegister(BaseReg, false);
1081
96
  unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum);
1082
96
  Offset += MI.getOperand(OffsetOperandNo).getImm();
1083
96
  MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
1084
96
1085
96
  MachineBasicBlock &MBB = *MI.getParent();
1086
96
  MachineFunction &MF = *MBB.getParent();
1087
96
  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1088
96
  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1089
96
  const MCInstrDesc &MCID = MI.getDesc();
1090
96
  MachineRegisterInfo &MRI = MF.getRegInfo();
1091
96
  MRI.constrainRegClass(BaseReg,
1092
96
                        TII.getRegClass(MCID, FIOperandNum, this, MF));
1093
96
}
1094
1095
bool PPCRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
1096
                                         unsigned BaseReg,
1097
1.83k
                                         int64_t Offset) const {
1098
1.83k
  unsigned FIOperandNum = 0;
1099
5.47k
  while (
!MI->getOperand(FIOperandNum).isFI()5.47k
) {
1100
3.63k
    ++FIOperandNum;
1101
3.63k
    assert(FIOperandNum < MI->getNumOperands() &&
1102
3.63k
           "Instr doesn't have FrameIndex operand!");
1103
3.63k
  }
1104
1.83k
1105
1.83k
  unsigned OffsetOperandNo = getOffsetONFromFION(*MI, FIOperandNum);
1106
1.83k
  Offset += MI->getOperand(OffsetOperandNo).getImm();
1107
1.83k
1108
1.83k
  return MI->getOpcode() == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm
1109
1.83k
         MI->getOpcode() == TargetOpcode::STACKMAP ||
1110
1.83k
         MI->getOpcode() == TargetOpcode::PATCHPOINT ||
1111
1.83k
         
(isInt<16>(Offset) && 1.83k
(Offset % offsetMinAlign(*MI)) == 01.73k
);
1112
1.83k
}