/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
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1 | | //===-- X86MCTargetDesc.cpp - X86 Target Descriptions ---------------------===// |
2 | | // |
3 | | // The LLVM Compiler Infrastructure |
4 | | // |
5 | | // This file is distributed under the University of Illinois Open Source |
6 | | // License. See LICENSE.TXT for details. |
7 | | // |
8 | | //===----------------------------------------------------------------------===// |
9 | | // |
10 | | // This file provides X86 specific target descriptions. |
11 | | // |
12 | | //===----------------------------------------------------------------------===// |
13 | | |
14 | | #include "X86MCTargetDesc.h" |
15 | | #include "InstPrinter/X86ATTInstPrinter.h" |
16 | | #include "InstPrinter/X86IntelInstPrinter.h" |
17 | | #include "X86MCAsmInfo.h" |
18 | | #include "llvm/ADT/Triple.h" |
19 | | #include "llvm/MC/MCInstrAnalysis.h" |
20 | | #include "llvm/MC/MCInstrInfo.h" |
21 | | #include "llvm/MC/MCRegisterInfo.h" |
22 | | #include "llvm/MC/MCStreamer.h" |
23 | | #include "llvm/MC/MCSubtargetInfo.h" |
24 | | #include "llvm/MC/MachineLocation.h" |
25 | | #include "llvm/Support/ErrorHandling.h" |
26 | | #include "llvm/Support/Host.h" |
27 | | #include "llvm/Support/TargetRegistry.h" |
28 | | |
29 | | #if _MSC_VER |
30 | | #include <intrin.h> |
31 | | #endif |
32 | | |
33 | | using namespace llvm; |
34 | | |
35 | | #define GET_REGINFO_MC_DESC |
36 | | #include "X86GenRegisterInfo.inc" |
37 | | |
38 | | #define GET_INSTRINFO_MC_DESC |
39 | | #include "X86GenInstrInfo.inc" |
40 | | |
41 | | #define GET_SUBTARGETINFO_MC_DESC |
42 | | #include "X86GenSubtargetInfo.inc" |
43 | | |
44 | 17.9k | std::string X86_MC::ParseX86Triple(const Triple &TT) { |
45 | 17.9k | std::string FS; |
46 | 17.9k | if (TT.getArch() == Triple::x86_64) |
47 | 13.3k | FS = "+64bit-mode,-32bit-mode,-16bit-mode"; |
48 | 4.56k | else if (4.56k TT.getEnvironment() != Triple::CODE164.56k ) |
49 | 4.55k | FS = "-64bit-mode,+32bit-mode,-16bit-mode"; |
50 | 4.56k | else |
51 | 11 | FS = "-64bit-mode,-32bit-mode,+16bit-mode"; |
52 | 17.9k | |
53 | 17.9k | return FS; |
54 | 17.9k | } |
55 | | |
56 | 55.6k | unsigned X86_MC::getDwarfRegFlavour(const Triple &TT, bool isEH) { |
57 | 55.6k | if (TT.getArch() == Triple::x86_64) |
58 | 41.4k | return DWARFFlavour::X86_64; |
59 | 14.1k | |
60 | 14.1k | if (14.1k TT.isOSDarwin()14.1k ) |
61 | 5.35k | return isEH ? 5.35k DWARFFlavour::X86_32_DarwinEH2.67k : DWARFFlavour::X86_32_Generic2.67k ; |
62 | 8.79k | if (8.79k TT.isOSCygMing()8.79k ) |
63 | 8.79k | // Unsupported by now, just quick fallback |
64 | 268 | return DWARFFlavour::X86_32_Generic; |
65 | 8.52k | return DWARFFlavour::X86_32_Generic; |
66 | 8.52k | } |
67 | | |
68 | 27.8k | void X86_MC::initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI) { |
69 | 27.8k | // FIXME: TableGen these. |
70 | 6.84M | for (unsigned Reg = X86::NoRegister + 1; Reg < X86::NUM_TARGET_REGS6.84M ; ++Reg6.81M ) { |
71 | 6.81M | unsigned SEH = MRI->getEncodingValue(Reg); |
72 | 6.81M | MRI->mapLLVMRegToSEHReg(Reg, SEH); |
73 | 6.81M | } |
74 | 27.8k | |
75 | 27.8k | // These CodeView registers are numbered sequentially starting at value 1. |
76 | 27.8k | static const MCPhysReg LowCVRegs[] = { |
77 | 27.8k | X86::AL, X86::CL, X86::DL, X86::BL, X86::AH, X86::CH, |
78 | 27.8k | X86::DH, X86::BH, X86::AX, X86::CX, X86::DX, X86::BX, |
79 | 27.8k | X86::SP, X86::BP, X86::SI, X86::DI, X86::EAX, X86::ECX, |
80 | 27.8k | X86::EDX, X86::EBX, X86::ESP, X86::EBP, X86::ESI, X86::EDI, |
81 | 27.8k | }; |
82 | 27.8k | unsigned CVLowRegStart = 1; |
83 | 695k | for (unsigned I = 0; I < array_lengthof(LowCVRegs)695k ; ++I667k ) |
84 | 667k | MRI->mapLLVMRegToCVReg(LowCVRegs[I], I + CVLowRegStart); |
85 | 27.8k | |
86 | 27.8k | MRI->mapLLVMRegToCVReg(X86::EFLAGS, 34); |
87 | 27.8k | |
88 | 27.8k | // The x87 registers start at 128 and are numbered sequentially. |
89 | 27.8k | unsigned FP0Start = 128; |
90 | 250k | for (unsigned I = 0; I < 8250k ; ++I222k ) |
91 | 222k | MRI->mapLLVMRegToCVReg(X86::FP0 + I, FP0Start + I); |
92 | 27.8k | |
93 | 27.8k | // The low 8 XMM registers start at 154 and are numbered sequentially. |
94 | 27.8k | unsigned CVXMM0Start = 154; |
95 | 250k | for (unsigned I = 0; I < 8250k ; ++I222k ) |
96 | 222k | MRI->mapLLVMRegToCVReg(X86::XMM0 + I, CVXMM0Start + I); |
97 | 27.8k | |
98 | 27.8k | // The high 8 XMM registers start at 252 and are numbered sequentially. |
99 | 27.8k | unsigned CVXMM8Start = 252; |
100 | 250k | for (unsigned I = 0; I < 8250k ; ++I222k ) |
101 | 222k | MRI->mapLLVMRegToCVReg(X86::XMM8 + I, CVXMM8Start + I); |
102 | 27.8k | |
103 | 27.8k | // FIXME: XMM16 and above from AVX512 not yet documented. |
104 | 27.8k | |
105 | 27.8k | // AMD64 registers start at 324 and count up. |
106 | 27.8k | unsigned CVX64RegStart = 324; |
107 | 27.8k | static const MCPhysReg CVX64Regs[] = { |
108 | 27.8k | X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::RAX, X86::RBX, |
109 | 27.8k | X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBP, X86::RSP, |
110 | 27.8k | X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, |
111 | 27.8k | X86::R14, X86::R15, X86::R8B, X86::R9B, X86::R10B, X86::R11B, |
112 | 27.8k | X86::R12B, X86::R13B, X86::R14B, X86::R15B, X86::R8W, X86::R9W, |
113 | 27.8k | X86::R10W, X86::R11W, X86::R12W, X86::R13W, X86::R14W, X86::R15W, |
114 | 27.8k | X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R12D, X86::R13D, |
115 | 27.8k | X86::R14D, X86::R15D, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, |
116 | 27.8k | X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, |
117 | 27.8k | X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, |
118 | 27.8k | }; |
119 | 1.69M | for (unsigned I = 0; I < array_lengthof(CVX64Regs)1.69M ; ++I1.66M ) |
120 | 1.66M | MRI->mapLLVMRegToCVReg(CVX64Regs[I], CVX64RegStart + I); |
121 | 27.8k | } |
122 | | |
123 | | MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(const Triple &TT, |
124 | 17.9k | StringRef CPU, StringRef FS) { |
125 | 17.9k | std::string ArchFS = X86_MC::ParseX86Triple(TT); |
126 | 17.9k | if (!FS.empty()17.9k ) { |
127 | 8.75k | if (!ArchFS.empty()) |
128 | 8.75k | ArchFS = (Twine(ArchFS) + "," + FS).str(); |
129 | 8.75k | else |
130 | 0 | ArchFS = FS; |
131 | 8.75k | } |
132 | 17.9k | |
133 | 17.9k | std::string CPUName = CPU; |
134 | 17.9k | if (CPUName.empty()) |
135 | 13.8k | CPUName = "generic"; |
136 | 17.9k | |
137 | 17.9k | return createX86MCSubtargetInfoImpl(TT, CPUName, ArchFS); |
138 | 17.9k | } |
139 | | |
140 | 21.0k | static MCInstrInfo *createX86MCInstrInfo() { |
141 | 21.0k | MCInstrInfo *X = new MCInstrInfo(); |
142 | 21.0k | InitX86MCInstrInfo(X); |
143 | 21.0k | return X; |
144 | 21.0k | } |
145 | | |
146 | 18.1k | static MCRegisterInfo *createX86MCRegisterInfo(const Triple &TT) { |
147 | 18.1k | unsigned RA = (TT.getArch() == Triple::x86_64) |
148 | 13.6k | ? X86::RIP // Should have dwarf #16. |
149 | 4.54k | : X86::EIP; // Should have dwarf #8. |
150 | 18.1k | |
151 | 18.1k | MCRegisterInfo *X = new MCRegisterInfo(); |
152 | 18.1k | InitX86MCRegisterInfo(X, RA, X86_MC::getDwarfRegFlavour(TT, false), |
153 | 18.1k | X86_MC::getDwarfRegFlavour(TT, true), RA); |
154 | 18.1k | X86_MC::initLLVMToSEHAndCVRegMapping(X); |
155 | 18.1k | return X; |
156 | 18.1k | } |
157 | | |
158 | | static MCAsmInfo *createX86MCAsmInfo(const MCRegisterInfo &MRI, |
159 | 17.7k | const Triple &TheTriple) { |
160 | 17.7k | bool is64Bit = TheTriple.getArch() == Triple::x86_64; |
161 | 17.7k | |
162 | 17.7k | MCAsmInfo *MAI; |
163 | 17.7k | if (TheTriple.isOSBinFormatMachO()17.7k ) { |
164 | 7.82k | if (is64Bit) |
165 | 6.14k | MAI = new X86_64MCAsmInfoDarwin(TheTriple); |
166 | 7.82k | else |
167 | 1.67k | MAI = new X86MCAsmInfoDarwin(TheTriple); |
168 | 17.7k | } else if (9.91k TheTriple.isOSBinFormatELF()9.91k ) { |
169 | 8.66k | // Force the use of an ELF container. |
170 | 8.66k | MAI = new X86ELFMCAsmInfo(TheTriple); |
171 | 9.91k | } else if (1.25k TheTriple.isWindowsMSVCEnvironment() || |
172 | 1.25k | TheTriple.isWindowsCoreCLREnvironment()178 ) { |
173 | 1.08k | MAI = new X86MCAsmInfoMicrosoft(TheTriple); |
174 | 1.25k | } else if (173 TheTriple.isOSCygMing() || |
175 | 173 | TheTriple.isWindowsItaniumEnvironment()34 ) { |
176 | 173 | MAI = new X86MCAsmInfoGNUCOFF(TheTriple); |
177 | 173 | } else { |
178 | 0 | // The default is ELF. |
179 | 0 | MAI = new X86ELFMCAsmInfo(TheTriple); |
180 | 0 | } |
181 | 17.7k | |
182 | 17.7k | // Initialize initial frame state. |
183 | 17.7k | // Calculate amount of bytes used for return address storing |
184 | 17.7k | int stackGrowth = is64Bit ? -813.2k : -44.50k ; |
185 | 17.7k | |
186 | 17.7k | // Initial state of the frame pointer is esp+stackGrowth. |
187 | 17.7k | unsigned StackPtr = is64Bit ? X86::RSP13.2k : X86::ESP4.50k ; |
188 | 17.7k | MCCFIInstruction Inst = MCCFIInstruction::createDefCfa( |
189 | 17.7k | nullptr, MRI.getDwarfRegNum(StackPtr, true), -stackGrowth); |
190 | 17.7k | MAI->addInitialFrameState(Inst); |
191 | 17.7k | |
192 | 17.7k | // Add return address to move list |
193 | 17.7k | unsigned InstPtr = is64Bit ? X86::RIP13.2k : X86::EIP4.50k ; |
194 | 17.7k | MCCFIInstruction Inst2 = MCCFIInstruction::createOffset( |
195 | 17.7k | nullptr, MRI.getDwarfRegNum(InstPtr, true), stackGrowth); |
196 | 17.7k | MAI->addInitialFrameState(Inst2); |
197 | 17.7k | |
198 | 17.7k | return MAI; |
199 | 17.7k | } |
200 | | |
201 | | static MCInstPrinter *createX86MCInstPrinter(const Triple &T, |
202 | | unsigned SyntaxVariant, |
203 | | const MCAsmInfo &MAI, |
204 | | const MCInstrInfo &MII, |
205 | 6.27k | const MCRegisterInfo &MRI) { |
206 | 6.27k | if (SyntaxVariant == 0) |
207 | 6.03k | return new X86ATTInstPrinter(MAI, MII, MRI); |
208 | 248 | if (248 SyntaxVariant == 1248 ) |
209 | 247 | return new X86IntelInstPrinter(MAI, MII, MRI); |
210 | 1 | return nullptr; |
211 | 1 | } |
212 | | |
213 | | static MCRelocationInfo *createX86MCRelocationInfo(const Triple &TheTriple, |
214 | 30 | MCContext &Ctx) { |
215 | 30 | // Default to the stock relocation info. |
216 | 30 | return llvm::createMCRelocationInfo(TheTriple, Ctx); |
217 | 30 | } |
218 | | |
219 | 225 | static MCInstrAnalysis *createX86MCInstrAnalysis(const MCInstrInfo *Info) { |
220 | 225 | return new MCInstrAnalysis(Info); |
221 | 225 | } |
222 | | |
223 | | // Force static initialization. |
224 | 70.3k | extern "C" void LLVMInitializeX86TargetMC() { |
225 | 140k | for (Target *T : {&getTheX86_32Target(), &getTheX86_64Target()}) { |
226 | 140k | // Register the MC asm info. |
227 | 140k | RegisterMCAsmInfoFn X(*T, createX86MCAsmInfo); |
228 | 140k | |
229 | 140k | // Register the MC instruction info. |
230 | 140k | TargetRegistry::RegisterMCInstrInfo(*T, createX86MCInstrInfo); |
231 | 140k | |
232 | 140k | // Register the MC register info. |
233 | 140k | TargetRegistry::RegisterMCRegInfo(*T, createX86MCRegisterInfo); |
234 | 140k | |
235 | 140k | // Register the MC subtarget info. |
236 | 140k | TargetRegistry::RegisterMCSubtargetInfo(*T, |
237 | 140k | X86_MC::createX86MCSubtargetInfo); |
238 | 140k | |
239 | 140k | // Register the MC instruction analyzer. |
240 | 140k | TargetRegistry::RegisterMCInstrAnalysis(*T, createX86MCInstrAnalysis); |
241 | 140k | |
242 | 140k | // Register the code emitter. |
243 | 140k | TargetRegistry::RegisterMCCodeEmitter(*T, createX86MCCodeEmitter); |
244 | 140k | |
245 | 140k | // Register the object streamer. |
246 | 140k | TargetRegistry::RegisterCOFFStreamer(*T, createX86WinCOFFStreamer); |
247 | 140k | |
248 | 140k | // Register the MCInstPrinter. |
249 | 140k | TargetRegistry::RegisterMCInstPrinter(*T, createX86MCInstPrinter); |
250 | 140k | |
251 | 140k | // Register the MC relocation info. |
252 | 140k | TargetRegistry::RegisterMCRelocationInfo(*T, createX86MCRelocationInfo); |
253 | 140k | } |
254 | 70.3k | |
255 | 70.3k | // Register the asm backend. |
256 | 70.3k | TargetRegistry::RegisterMCAsmBackend(getTheX86_32Target(), |
257 | 70.3k | createX86_32AsmBackend); |
258 | 70.3k | TargetRegistry::RegisterMCAsmBackend(getTheX86_64Target(), |
259 | 70.3k | createX86_64AsmBackend); |
260 | 70.3k | } |
261 | | |
262 | | unsigned llvm::getX86SubSuperRegisterOrZero(unsigned Reg, unsigned Size, |
263 | 10.6k | bool High) { |
264 | 10.6k | switch (Size) { |
265 | 1 | default: return 0; |
266 | 2.63k | case 8: |
267 | 2.63k | if (High2.63k ) { |
268 | 2.60k | switch (Reg) { |
269 | 66 | default: return getX86SubSuperRegisterOrZero(Reg, 64); |
270 | 12 | case X86::SIL: 12 case X86::SI: 12 case X86::ESI: 12 case X86::RSI: |
271 | 12 | return X86::SI; |
272 | 2 | case X86::DIL: 2 case X86::DI: 2 case X86::EDI: 2 case X86::RDI: |
273 | 2 | return X86::DI; |
274 | 1 | case X86::BPL: 1 case X86::BP: 1 case X86::EBP: 1 case X86::RBP: |
275 | 1 | return X86::BP; |
276 | 0 | case X86::SPL: 0 case X86::SP: 0 case X86::ESP: 0 case X86::RSP: |
277 | 0 | return X86::SP; |
278 | 651 | case X86::AH: 651 case X86::AL: 651 case X86::AX: 651 case X86::EAX: 651 case X86::RAX: |
279 | 651 | return X86::AH; |
280 | 447 | case X86::DH: 447 case X86::DL: 447 case X86::DX: 447 case X86::EDX: 447 case X86::RDX: |
281 | 447 | return X86::DH; |
282 | 1.21k | case X86::CH: 1.21k case X86::CL: 1.21k case X86::CX: 1.21k case X86::ECX: 1.21k case X86::RCX: |
283 | 1.21k | return X86::CH; |
284 | 204 | case X86::BH: 204 case X86::BL: 204 case X86::BX: 204 case X86::EBX: 204 case X86::RBX: |
285 | 204 | return X86::BH; |
286 | 2.63k | } |
287 | 29 | } else { |
288 | 29 | switch (Reg) { |
289 | 0 | default: return 0; |
290 | 21 | case X86::AH: 21 case X86::AL: 21 case X86::AX: 21 case X86::EAX: 21 case X86::RAX: |
291 | 21 | return X86::AL; |
292 | 1 | case X86::DH: 1 case X86::DL: 1 case X86::DX: 1 case X86::EDX: 1 case X86::RDX: |
293 | 1 | return X86::DL; |
294 | 2 | case X86::CH: 2 case X86::CL: 2 case X86::CX: 2 case X86::ECX: 2 case X86::RCX: |
295 | 2 | return X86::CL; |
296 | 1 | case X86::BH: 1 case X86::BL: 1 case X86::BX: 1 case X86::EBX: 1 case X86::RBX: |
297 | 1 | return X86::BL; |
298 | 1 | case X86::SIL: 1 case X86::SI: 1 case X86::ESI: 1 case X86::RSI: |
299 | 1 | return X86::SIL; |
300 | 1 | case X86::DIL: 1 case X86::DI: 1 case X86::EDI: 1 case X86::RDI: |
301 | 1 | return X86::DIL; |
302 | 1 | case X86::BPL: 1 case X86::BP: 1 case X86::EBP: 1 case X86::RBP: |
303 | 1 | return X86::BPL; |
304 | 0 | case X86::SPL: 0 case X86::SP: 0 case X86::ESP: 0 case X86::RSP: |
305 | 0 | return X86::SPL; |
306 | 0 | case X86::R8B: 0 case X86::R8W: 0 case X86::R8D: 0 case X86::R8: |
307 | 0 | return X86::R8B; |
308 | 0 | case X86::R9B: 0 case X86::R9W: 0 case X86::R9D: 0 case X86::R9: |
309 | 0 | return X86::R9B; |
310 | 0 | case X86::R10B: 0 case X86::R10W: 0 case X86::R10D: 0 case X86::R10: |
311 | 0 | return X86::R10B; |
312 | 0 | case X86::R11B: 0 case X86::R11W: 0 case X86::R11D: 0 case X86::R11: |
313 | 0 | return X86::R11B; |
314 | 1 | case X86::R12B: 1 case X86::R12W: 1 case X86::R12D: 1 case X86::R12: |
315 | 1 | return X86::R12B; |
316 | 0 | case X86::R13B: 0 case X86::R13W: 0 case X86::R13D: 0 case X86::R13: |
317 | 0 | return X86::R13B; |
318 | 0 | case X86::R14B: 0 case X86::R14W: 0 case X86::R14D: 0 case X86::R14: |
319 | 0 | return X86::R14B; |
320 | 0 | case X86::R15B: 0 case X86::R15W: 0 case X86::R15D: 0 case X86::R15: |
321 | 0 | return X86::R15B; |
322 | 0 | } |
323 | 0 | } |
324 | 10 | case 16: |
325 | 10 | switch (Reg) { |
326 | 0 | default: return 0; |
327 | 6 | case X86::AH: 6 case X86::AL: 6 case X86::AX: 6 case X86::EAX: 6 case X86::RAX: |
328 | 6 | return X86::AX; |
329 | 1 | case X86::DH: 1 case X86::DL: 1 case X86::DX: 1 case X86::EDX: 1 case X86::RDX: |
330 | 1 | return X86::DX; |
331 | 0 | case X86::CH: 0 case X86::CL: 0 case X86::CX: 0 case X86::ECX: 0 case X86::RCX: |
332 | 0 | return X86::CX; |
333 | 0 | case X86::BH: 0 case X86::BL: 0 case X86::BX: 0 case X86::EBX: 0 case X86::RBX: |
334 | 0 | return X86::BX; |
335 | 0 | case X86::SIL: 0 case X86::SI: 0 case X86::ESI: 0 case X86::RSI: |
336 | 0 | return X86::SI; |
337 | 1 | case X86::DIL: 1 case X86::DI: 1 case X86::EDI: 1 case X86::RDI: |
338 | 1 | return X86::DI; |
339 | 0 | case X86::BPL: 0 case X86::BP: 0 case X86::EBP: 0 case X86::RBP: |
340 | 0 | return X86::BP; |
341 | 0 | case X86::SPL: 0 case X86::SP: 0 case X86::ESP: 0 case X86::RSP: |
342 | 0 | return X86::SP; |
343 | 0 | case X86::R8B: 0 case X86::R8W: 0 case X86::R8D: 0 case X86::R8: |
344 | 0 | return X86::R8W; |
345 | 1 | case X86::R9B: 1 case X86::R9W: 1 case X86::R9D: 1 case X86::R9: |
346 | 1 | return X86::R9W; |
347 | 0 | case X86::R10B: 0 case X86::R10W: 0 case X86::R10D: 0 case X86::R10: |
348 | 0 | return X86::R10W; |
349 | 0 | case X86::R11B: 0 case X86::R11W: 0 case X86::R11D: 0 case X86::R11: |
350 | 0 | return X86::R11W; |
351 | 0 | case X86::R12B: 0 case X86::R12W: 0 case X86::R12D: 0 case X86::R12: |
352 | 0 | return X86::R12W; |
353 | 0 | case X86::R13B: 0 case X86::R13W: 0 case X86::R13D: 0 case X86::R13: |
354 | 0 | return X86::R13W; |
355 | 0 | case X86::R14B: 0 case X86::R14W: 0 case X86::R14D: 0 case X86::R14: |
356 | 0 | return X86::R14W; |
357 | 1 | case X86::R15B: 1 case X86::R15W: 1 case X86::R15D: 1 case X86::R15: |
358 | 1 | return X86::R15W; |
359 | 0 | } |
360 | 6.44k | case 32: |
361 | 6.44k | switch (Reg) { |
362 | 0 | default: return 0; |
363 | 2.50k | case X86::AH: 2.50k case X86::AL: 2.50k case X86::AX: 2.50k case X86::EAX: 2.50k case X86::RAX: |
364 | 2.50k | return X86::EAX; |
365 | 872 | case X86::DH: 872 case X86::DL: 872 case X86::DX: 872 case X86::EDX: 872 case X86::RDX: |
366 | 872 | return X86::EDX; |
367 | 1.78k | case X86::CH: 1.78k case X86::CL: 1.78k case X86::CX: 1.78k case X86::ECX: 1.78k case X86::RCX: |
368 | 1.78k | return X86::ECX; |
369 | 460 | case X86::BH: 460 case X86::BL: 460 case X86::BX: 460 case X86::EBX: 460 case X86::RBX: |
370 | 460 | return X86::EBX; |
371 | 215 | case X86::SIL: 215 case X86::SI: 215 case X86::ESI: 215 case X86::RSI: |
372 | 215 | return X86::ESI; |
373 | 207 | case X86::DIL: 207 case X86::DI: 207 case X86::EDI: 207 case X86::RDI: |
374 | 207 | return X86::EDI; |
375 | 48 | case X86::BPL: 48 case X86::BP: 48 case X86::EBP: 48 case X86::RBP: |
376 | 48 | return X86::EBP; |
377 | 10 | case X86::SPL: 10 case X86::SP: 10 case X86::ESP: 10 case X86::RSP: |
378 | 10 | return X86::ESP; |
379 | 64 | case X86::R8B: 64 case X86::R8W: 64 case X86::R8D: 64 case X86::R8: |
380 | 64 | return X86::R8D; |
381 | 44 | case X86::R9B: 44 case X86::R9W: 44 case X86::R9D: 44 case X86::R9: |
382 | 44 | return X86::R9D; |
383 | 39 | case X86::R10B: 39 case X86::R10W: 39 case X86::R10D: 39 case X86::R10: |
384 | 39 | return X86::R10D; |
385 | 41 | case X86::R11B: 41 case X86::R11W: 41 case X86::R11D: 41 case X86::R11: |
386 | 41 | return X86::R11D; |
387 | 35 | case X86::R12B: 35 case X86::R12W: 35 case X86::R12D: 35 case X86::R12: |
388 | 35 | return X86::R12D; |
389 | 7 | case X86::R13B: 7 case X86::R13W: 7 case X86::R13D: 7 case X86::R13: |
390 | 7 | return X86::R13D; |
391 | 56 | case X86::R14B: 56 case X86::R14W: 56 case X86::R14D: 56 case X86::R14: |
392 | 56 | return X86::R14D; |
393 | 55 | case X86::R15B: 55 case X86::R15W: 55 case X86::R15D: 55 case X86::R15: |
394 | 55 | return X86::R15D; |
395 | 0 | } |
396 | 1.52k | case 64: |
397 | 1.52k | switch (Reg) { |
398 | 0 | default: return 0; |
399 | 240 | case X86::AH: 240 case X86::AL: 240 case X86::AX: 240 case X86::EAX: 240 case X86::RAX: |
400 | 240 | return X86::RAX; |
401 | 92 | case X86::DH: 92 case X86::DL: 92 case X86::DX: 92 case X86::EDX: 92 case X86::RDX: |
402 | 92 | return X86::RDX; |
403 | 109 | case X86::CH: 109 case X86::CL: 109 case X86::CX: 109 case X86::ECX: 109 case X86::RCX: |
404 | 109 | return X86::RCX; |
405 | 81 | case X86::BH: 81 case X86::BL: 81 case X86::BX: 81 case X86::EBX: 81 case X86::RBX: |
406 | 81 | return X86::RBX; |
407 | 156 | case X86::SIL: 156 case X86::SI: 156 case X86::ESI: 156 case X86::RSI: |
408 | 156 | return X86::RSI; |
409 | 210 | case X86::DIL: 210 case X86::DI: 210 case X86::EDI: 210 case X86::RDI: |
410 | 210 | return X86::RDI; |
411 | 130 | case X86::BPL: 130 case X86::BP: 130 case X86::EBP: 130 case X86::RBP: |
412 | 130 | return X86::RBP; |
413 | 420 | case X86::SPL: 420 case X86::SP: 420 case X86::ESP: 420 case X86::RSP: |
414 | 420 | return X86::RSP; |
415 | 22 | case X86::R8B: 22 case X86::R8W: 22 case X86::R8D: 22 case X86::R8: |
416 | 22 | return X86::R8; |
417 | 10 | case X86::R9B: 10 case X86::R9W: 10 case X86::R9D: 10 case X86::R9: |
418 | 10 | return X86::R9; |
419 | 10 | case X86::R10B: 10 case X86::R10W: 10 case X86::R10D: 10 case X86::R10: |
420 | 10 | return X86::R10; |
421 | 2 | case X86::R11B: 2 case X86::R11W: 2 case X86::R11D: 2 case X86::R11: |
422 | 2 | return X86::R11; |
423 | 8 | case X86::R12B: 8 case X86::R12W: 8 case X86::R12D: 8 case X86::R12: |
424 | 8 | return X86::R12; |
425 | 4 | case X86::R13B: 4 case X86::R13W: 4 case X86::R13D: 4 case X86::R13: |
426 | 4 | return X86::R13; |
427 | 10 | case X86::R14B: 10 case X86::R14W: 10 case X86::R14D: 10 case X86::R14: |
428 | 10 | return X86::R14; |
429 | 17 | case X86::R15B: 17 case X86::R15W: 17 case X86::R15D: 17 case X86::R15: |
430 | 17 | return X86::R15; |
431 | 0 | } |
432 | 10.6k | } |
433 | 10.6k | } |
434 | | |
435 | 10.0k | unsigned llvm::getX86SubSuperRegister(unsigned Reg, unsigned Size, bool High) { |
436 | 10.0k | unsigned Res = getX86SubSuperRegisterOrZero(Reg, Size, High); |
437 | 10.0k | assert(Res != 0 && "Unexpected register or VT"); |
438 | 10.0k | return Res; |
439 | 10.0k | } |
440 | | |
441 | | |