/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/llvm/lib/Target/X86/X86GenRegisterBankInfo.def
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1 | | //===- X86GenRegisterBankInfo.def ----------------------------*- C++ -*-==// |
2 | | // |
3 | | // The LLVM Compiler Infrastructure |
4 | | // |
5 | | // This file is distributed under the University of Illinois Open Source |
6 | | // License. See LICENSE.TXT for details. |
7 | | // |
8 | | //===----------------------------------------------------------------------===// |
9 | | /// \file |
10 | | /// This file defines all the static objects used by X86RegisterBankInfo. |
11 | | /// \todo This should be generated by TableGen. |
12 | | //===----------------------------------------------------------------------===// |
13 | | |
14 | | #ifdef GET_TARGET_REGBANK_INFO_IMPL |
15 | | RegisterBankInfo::PartialMapping X86GenRegisterBankInfo::PartMappings[]{ |
16 | | /* StartIdx, Length, RegBank */ |
17 | | // GPR value |
18 | | {0, 8, X86::GPRRegBank}, // :0 |
19 | | {0, 16, X86::GPRRegBank}, // :1 |
20 | | {0, 32, X86::GPRRegBank}, // :2 |
21 | | {0, 64, X86::GPRRegBank}, // :3 |
22 | | // FR32/64 , xmm registers |
23 | | {0, 32, X86::VECRRegBank}, // :4 |
24 | | {0, 64, X86::VECRRegBank}, // :5 |
25 | | // VR128/256/512 |
26 | | {0, 128, X86::VECRRegBank}, // :6 |
27 | | {0, 256, X86::VECRRegBank}, // :7 |
28 | | {0, 512, X86::VECRRegBank}, // :8 |
29 | | }; |
30 | | #endif // GET_TARGET_REGBANK_INFO_IMPL |
31 | | |
32 | | #ifdef GET_TARGET_REGBANK_INFO_CLASS |
33 | | enum PartialMappingIdx { |
34 | | PMI_None = -1, |
35 | | PMI_GPR8, |
36 | | PMI_GPR16, |
37 | | PMI_GPR32, |
38 | | PMI_GPR64, |
39 | | PMI_FP32, |
40 | | PMI_FP64, |
41 | | PMI_VEC128, |
42 | | PMI_VEC256, |
43 | | PMI_VEC512 |
44 | | }; |
45 | | #endif // GET_TARGET_REGBANK_INFO_CLASS |
46 | | |
47 | | #ifdef GET_TARGET_REGBANK_INFO_IMPL |
48 | | #define INSTR_3OP(INFO) INFO, INFO, INFO, |
49 | | #define BREAKDOWN(INDEX, NUM) \ |
50 | | { &X86GenRegisterBankInfo::PartMappings[INDEX], NUM } |
51 | | // ValueMappings. |
52 | | RegisterBankInfo::ValueMapping X86GenRegisterBankInfo::ValMappings[]{ |
53 | | /* BreakDown, NumBreakDowns */ |
54 | | // 3-operands instructions (all binary operations should end up with one of |
55 | | // those mapping). |
56 | | INSTR_3OP(BREAKDOWN(PMI_GPR8, 1)) // 0: GPR_8 |
57 | | INSTR_3OP(BREAKDOWN(PMI_GPR16, 1)) // 3: GPR_16 |
58 | | INSTR_3OP(BREAKDOWN(PMI_GPR32, 1)) // 6: GPR_32 |
59 | | INSTR_3OP(BREAKDOWN(PMI_GPR64, 1)) // 9: GPR_64 |
60 | | INSTR_3OP(BREAKDOWN(PMI_FP32, 1)) // 12: Fp32 |
61 | | INSTR_3OP(BREAKDOWN(PMI_FP64, 1)) // 15: Fp64 |
62 | | INSTR_3OP(BREAKDOWN(PMI_VEC128, 1)) // 18: Vec128 |
63 | | INSTR_3OP(BREAKDOWN(PMI_VEC256, 1)) // 21: Vec256 |
64 | | INSTR_3OP(BREAKDOWN(PMI_VEC512, 1)) // 24: Vec512 |
65 | | }; |
66 | | #undef INSTR_3OP |
67 | | #undef BREAKDOWN |
68 | | #endif // GET_TARGET_REGBANK_INFO_IMPL |
69 | | |
70 | | #ifdef GET_TARGET_REGBANK_INFO_CLASS |
71 | | enum ValueMappingIdx { |
72 | | VMI_None = -1, |
73 | | VMI_3OpsGpr8Idx = PMI_GPR8 * 3, |
74 | | VMI_3OpsGpr16Idx = PMI_GPR16 * 3, |
75 | | VMI_3OpsGpr32Idx = PMI_GPR32 * 3, |
76 | | VMI_3OpsGpr64Idx = PMI_GPR64 * 3, |
77 | | VMI_3OpsFp32Idx = PMI_FP32 * 3, |
78 | | VMI_3OpsFp64Idx = PMI_FP64 * 3, |
79 | | VMI_3OpsVec128Idx = PMI_VEC128 * 3, |
80 | | VMI_3OpsVec256Idx = PMI_VEC256 * 3, |
81 | | VMI_3OpsVec512Idx = PMI_VEC512 * 3, |
82 | | }; |
83 | | #undef GET_TARGET_REGBANK_INFO_CLASS |
84 | | #endif // GET_TARGET_REGBANK_INFO_CLASS |
85 | | |
86 | | #ifdef GET_TARGET_REGBANK_INFO_IMPL |
87 | | #undef GET_TARGET_REGBANK_INFO_IMPL |
88 | | const RegisterBankInfo::ValueMapping * |
89 | | X86GenRegisterBankInfo::getValueMapping(PartialMappingIdx Idx, |
90 | 1.98k | unsigned NumOperands) { |
91 | 1.98k | |
92 | 1.98k | // We can use VMI_3Ops Mapping for all the cases. |
93 | 1.98k | if (NumOperands <= 3 && 1.98k (Idx >= PMI_GPR8 && 1.98k Idx <= PMI_VEC5121.98k )) |
94 | 1.98k | return &ValMappings[(unsigned)Idx * 3]; |
95 | 1.98k | |
96 | 0 | llvm_unreachable0 ("Unsupported PartialMappingIdx."); |
97 | | } |
98 | | |
99 | | #endif // GET_TARGET_REGBANK_INFO_IMPL |
100 | | |