1. [DebugInfo] Fix pessimizing move. NFC. (details)
  2. SpeculativeExecution: Fix for logic change introduced in D81730. (details)
  3. [RISCV] Avoid Splitting MBB in RISCVExpandPseudo (details)
Commit d36b8414bdde1f361c40e6f6d53788c43ffe53c1 by benny.kra
[DebugInfo] Fix pessimizing move. NFC.

DWARFDebugPubTable.cpp:80:31: warning: moving a temporary object prevents copy elision [-Wpessimizing-move]
The file was modifiedllvm/lib/DebugInfo/DWARF/DWARFDebugPubTable.cpp (diff)
Commit 167767a775f3db5cd94053d4da6a4f419b6211cd by dfukalov
SpeculativeExecution: Fix for logic change introduced in D81730.

The test case started to hoist bitcasts to upper BB after D81730.
Reverted unintentional logic change. Some instructions may have zero cost but
will not be hoisted by different limitation so should be counted for threshold.

Reviewers: aprantl, arsenm, nhaehnle

Reviewed By: aprantl

Subscribers: wdng, hiraditya, llvm-commits

Tags: #llvm

Differential Revision:
The file was modifiedllvm/lib/Transforms/Scalar/SpeculativeExecution.cpp (diff)
The file was modifiedllvm/test/Transforms/SpeculativeExecution/PR46267.ll (diff)
Commit 97106f9d80f6ba1bf5eafbd5a6f88d72913ec5a1 by selliott
[RISCV] Avoid Splitting MBB in RISCVExpandPseudo

Since the `RISCVExpandPseudo` pass has been split from
`RISCVExpandAtomicPseudo` pass, it would be nice to run the former as
early as possible (The latter has to be run as late as possible to
ensure correctness). Running earlier means we can reschedule these pairs
as we see fit.

Running earlier in the machine pass pipeline is good, but would mean
teaching many more passes about `hasLabelMustBeEmitted`. Splitting the
basic blocks also pessimises possible optimisations because some
optimisations are MBB-local, and others are disabled if the block has
its address taken (which is notionally what `hasLabelMustBeEmitted`

This patch uses a new approach of setting the pre-instruction symbol on
the AUIPC instruction to a temporary symbol and referencing that. This
avoids splitting the basic block, but allows us to reference exactly the
instruction that we need to. Notionally, this approach seems more
correct because we do actually want to address a specific instruction.

This then allows the pass to be moved much earlier in the pass pipeline,
before both scheduling and register allocation. However, to do so we
must leave the MIR in SSA form (by not redefining registers), and so use
a virtual register for the intermediate value. By using this virtual
register, this pass now has to come before register allocation.

Reviewed By: luismarques, asb

Differential Revision:
The file was modifiedllvm/test/CodeGen/RISCV/pic-models.ll (diff)
The file was modifiedllvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (diff)
The file was modifiedllvm/lib/Target/RISCV/RISCVMCInstLower.cpp (diff)
The file was modifiedllvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp (diff)
The file was modifiedllvm/include/llvm/CodeGen/MachineBasicBlock.h (diff)
The file was modifiedllvm/test/CodeGen/RISCV/mir-target-flags.ll (diff)
The file was modifiedllvm/test/CodeGen/RISCV/tls-models.ll (diff)
The file was modifiedllvm/lib/Target/RISCV/RISCVTargetMachine.cpp (diff)
The file was modifiedllvm/test/CodeGen/RISCV/codemodel-lowering.ll (diff)