Started 2 mo 18 days ago
Took 1 hr 9 min

Success Build #3489 (Nov 4, 2019 11:24:55 AM)

Changes
  1. [lldb] [Process/NetBSD] Add register info for missing register sets (detail / githubweb)
  2. [DAGCombine][MSP430] use shift amount threshold in DAGCombine (2/2) (detail / githubweb)
  3. [SimplifyCFG] Use a (trivially) dominanting widenable branch to remove (detail / githubweb)
  4. [X86] Add support for -mvzeroupper and -mno-vzeroupper to match gcc (detail / githubweb)

Started by an SCM change (13 times)

This run spent:

  • 46 min waiting;
  • 1 hr 9 min build duration;
  • 1 hr 56 min total from scheduled to completion.
Revision: b2b6a54f847f33f821f41e3e82bf3b86e08817a0
  • refs/remotes/origin/master
Revision: 8ea093f54b1b5c4588b08b606c84b80bec84cf2b
  • refs/remotes/origin/master
Test Result (no failures)