Started 27 days ago
Took 10 hr on green-dragon-06

Success Build #7790 (Apr 20, 2021 7:45:22 AM)

Changes

Git (git http://labmaster3.local/git/llvm-project.git)

  1. [mlir][llvm] Add UnnamedAddr attribute to GlobalOp (detail)
  2. [lldb] Fix one leak in reproducer (detail)
  3. [AArch64][SVE] Combine add and index_vector (detail)
  4. [GreedyRA ORE] Add Cost of spill locations into remark (detail)
  5. [Docs] Mention LLVM_EXPERIMENTAL_TARGETS_TO_BUILD variable in CMake.rst (detail)
  6. Revert "[GreedyRA ORE] Add Cost of spill locations into remark" (detail)
  7. [RISCV][test] Add a new test of addition (detail)
  8. [Test] Add loop load PRE test with GC pointers (detail)
  9. [mlir][linalg] update drop unit dims to support linalg index operations. (detail)
  10. [RISCV] Handle PseudoVRELOAD and PseudoVSPILL in getInstSizeInBytes. (detail)
  11. [mlir][linalg] update fusion on tensors to support linalg index operations. (detail)
  12. [llvm-rc] Simplify Opts.td to avoid repetition. NFC. (detail)
  13. [llvm-rc] Fix handling of the /X option to match its documentation and rc.exe (detail)
  14. [Test] Add -lcssa run to force LI in GVN (detail)
  15. [X86][AMX] Add description of x86_amx to LangRef. (detail)
  16. [MLIR][LinAlg] Detensoring CF cost-model: look forward. (detail)
  17. [NFC] Restructure code to make it possible to insert other GCs (detail)
  18. [CSKY 4/n] Add basic CSKYAsmParser and CSKYInstPrinter (detail)
  19. [CSKY 5/n] Add support for all CSKY basic integer instructions except for branch series (detail)
  20. [CSKY 6/n] Add support branch and symbol series instruction (detail)
  21. [SelectionDAG] Relax constraints on STEP_VECTOR step operand (detail)
  22. [PowerPC] Support f128 under VSX (detail)
  23. Explicitly pass type to cast load constant folding result (detail)
  24. [X86][AMX] Verify illegal types or instructions for x86_amx. (detail)
  25. [AMDGPU] GCNDPPCombine: don't shrink V_ADD_CO_U32 if carry out is used (detail)
  26. [DAGCombiner] Support fold zero scalar vector. (detail)
  27. [PowerPC] Use mtvsrdd to put callee-saved GPR into VSR (detail)
  28. [LV] Let selectVectorizationFactor reason directly on VectorizationFactor. (detail)
  29. [RISCV] Fix missing emergency slots for scalable stack offsets (detail)
  30. Re-land [GreedyRA ORE] Add Cost of spill locations into remark (detail)
  31. [Support] BinaryStreamReader.h - remove unnecessary <string> include. NFCI. (detail)
  32. [mlir] Add patterns to lower Math operations to LLVM based libm calls. (detail)
  33. [mlir] Progressively lower vector to SCF (detail)
  34. [ARM] Regenerate a couple of tests. NFC (detail)
  35. [libcxx][test] Split off debug mode tests (detail)
  36. [AArch64][SVE][InstCombine] Replace last{a,b} intrinsics with extracts... (detail)
  37. [AArch64] Constant fold sve_convert_from_svbool(zero) to zero (detail)
  38. [RISCV] Refactor an optimization of addition with immediate (detail)
  39. [CodeGen] CodeGenPassBuilder.h - remove unnecessary <string> include. NFCI. (detail)
  40. [Support] APInt.h - remove <algorithm> include. NFCI. (detail)
  41. [MemoryBuiltins] Added support for memalign (detail)
  42. [AMDGPU] Re-arrange ds_read/ds_write ISel pattern for better readability. (detail)
  43. [C++, test] Fix typo in NSS* vars (detail)
  44. clang-format: [JS] do not merge imports and exports. (detail)
  45. [lit, test] Fix test cancellation feature detection (detail)
  46. [mlir] test gather/scatter index vector of type index. (detail)
  47. Fix Wdocumentation warning by consistently using '///' comment blocks. NFCI. (detail)
  48. [DAG] SelectionDAG.cpp - breakup if-else chains where each block returns. NFCI. (detail)
  49. [mlir][linalg] lower index operations during linalg to vector lowering. (detail)
  50. [AMDGPU] Use simpler alternatives to !foldl. NFC. (detail)
  51. [ValueTypes] Fix sizes of v256i32 and v256f32 (8182 -> 8192) (detail)
  52. [llvm-objdump] Add an llvm-otool tool (detail)
  53. [PowerPC] Canonicalize shuffles on big endian targets as well (detail)
  54. [MCA][LSUnit] Fix a potential use after free in the logic that updates memory groups. (detail)
  55. [libc++][ci] Re-split the CI pipeline to try and reduce load on more builders (detail)

Started by upstream project clang-stage2-cmake-RgSan_relay build number 3453
originally caused by:

This run spent:

  • 1 hr 9 min waiting;
  • 10 hr build duration;
  • 11 hr total from scheduled to completion.
Revision: 2704d0a70172f5b57dd2bebcc173d4c9cec082d3
  • detached
Revision: 1e62f7a9ca6dedbeaa5f2b046701d0b13d40df9d
  • refs/remotes/origin/main
LLVM/Clang Warnings: 0 warnings.
  • No warnings since build 7,779.
  • Still 381 days before reaching the previous zero warnings highscore.
Test Result (no failures)