FailedChanges

Summary

  1. [AMDGPU] Don’t marke the .note section as ALLOC (details)
  2. [Utils][x86] add an option to reduce scrubbing of shuffles with memops (details)
  3. AMDGPU: Fix v2i64<->v4f32 bitcast (details)
  4. [NFC][RDA] Break-up initialization code (details)
  5. [PowerPC][NFC] We do not save/restore vrsave for any remaining subtargets. (details)
  6. [x86] regenerate test checks with less shuffle scrubbing; NFC (details)
  7. Add #include <condition_variable> to fix build after 85fb997659b5 (details)
  8. [DAGCombine] visitEXTRACT_VECTOR_ELT - add SimplifyDemandedBits multi use support (details)
  9. [clang][analyzer] Modify include AllocationState.h in PutenvWithAutoChecker.cpp (details)
  10. [X86] Add DAG combines to form CVTPH2PS/CVTPS2PH from vXf16->vXf32/vXf64 fp_extends and vXf32->vXf16 fp_round. (details)
  11. [AArch64][SVE] Add intrinsics for SVE2 bitwise ternary operations (details)
  12. [x86] add vector tests for splatted memory ops; NFC (details)
  13. [AArch64] Move isOverflowIntrOpRes help function to the ISD namespace in SelectionDAG.h. NFC (details)
  14. [X86] Rewrite LowerBRCOND to remove dead code and handle ISD::SETCC and overflow ops directly. (details)
  15. [libc++] Fix unintended ADL inside ref(reference_wrapper<T>) and cref(reference_wrapper<T>) (details)
  16. [libc++] Fix unqualified call to 'ref' inside shared_ptr(unique_ptr<U, D>) (details)
  17. [clang-tidy] rename_check.py: maintain alphabetical order in Renamed checks section (details)
  18. [X86] Fix a -Wparentheses warning. NFC (details)
Commit 977cd661cf019039dec7ffdd15bf0ac500828c87 by sebastian.neubauer
[AMDGPU] Don’t marke the .note section as ALLOC

Marking a section as ALLOC tells the ELF loader to load the section into memory.
As we do not want to load the notes into VRAM, the flag should not be there.

Differential Revision: https://reviews.llvm.org/D74600
The file was modifiedllvm/test/CodeGen/AMDGPU/hsa.ll
The file was modifiedllvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
Commit 15e20dcb8f9decf1928871d562a3724e8cc1e343 by spatel
[Utils][x86] add an option to reduce scrubbing of shuffles with memops

I was drafting a patch that would increase broadcast load usage,
but our shuffle scrubbing makes it impossible to see if the memory
operand offset was getting created correctly. I'm proposing to make
that an option (defaulted to 'off' for now to reduce regression
test churn).

The updated files provide examples of tests where we can now verify
that the pointer offset for a loaded memory operand is correct. We
still have stack and constant scrubbing that can obscure the operand
even if we don't scrub the entire instruction.

Differential Revision: https://reviews.llvm.org/D74775
The file was modifiedllvm/test/CodeGen/X86/extractelement-load.ll
The file was modifiedllvm/test/CodeGen/X86/avx-splat.ll
The file was modifiedllvm/utils/UpdateTestChecks/asm.py
The file was modifiedllvm/utils/update_llc_test_checks.py
Commit 083717cf49968ebb973d73b448709d45e3fc0e99 by arsenm2
AMDGPU: Fix v2i64<->v4f32 bitcast

I'm not sure how to test the v2i64->v4f32 case since I can't think of
any v2i64 cases that won't legalize to v4i32.
The file was modifiedllvm/lib/Target/AMDGPU/SIInstructions.td
The file was modifiedllvm/test/CodeGen/AMDGPU/amdgcn.bitcast.ll
Commit 659500c0c9657fc6e8d2d184b507f4e4da99297e by sam.parker
[NFC][RDA] Break-up initialization code

Separate out the initialization code from the loop traversal so
that the analysis can be reset and re-run by a user.
The file was modifiedllvm/lib/CodeGen/ReachingDefAnalysis.cpp
The file was modifiedllvm/include/llvm/CodeGen/ReachingDefAnalysis.h
Commit 45f008704df2680660ee82a7c3543d3ac9499a99 by sd.fertile
[PowerPC][NFC] We do not save/restore vrsave for any remaining subtargets.

Extend lit test to show that we don't save or restore vrsave register
when expanding @llvm.eh.unwind.init().
The file was modifiedllvm/test/CodeGen/PowerPC/unwind-dw2.ll
Commit 216a6e05249544db4c1c3f30944aba3da7463eef by spatel
[x86] regenerate test checks with less shuffle scrubbing; NFC

For shuffles with memory operands, we generally don't want to
hide the asm because we want to verify that the address offsets
are as expected.
The file was modifiedllvm/test/CodeGen/X86/masked_gather.ll
The file was modifiedllvm/test/CodeGen/X86/avx512-shuffles/partial_permute.ll
Commit 1f984c83a41bb68b8af4998a7f68876d52bff872 by hans
Add #include <condition_variable> to fix build after 85fb997659b5

See https://reviews.llvm.org/D74300#1884614
The file was modifiedllvm/lib/ExecutionEngine/Orc/Core.cpp
Commit fc2b4a02b1a82c40ac1459cd15b9911ebfc78acc by llvm-dev
[DAGCombine] visitEXTRACT_VECTOR_ELT - add SimplifyDemandedBits multi use support

Similar to what we already do with SimplifyDemandedVectorElts, call SimplifyDemandedBits across all the extracted elements of the source vector, treating it as single use.

There's a minor regression in store-weird-sizes.ll which will be addressed in an upcoming SimplifyDemandedBits patch.
The file was modifiedllvm/test/CodeGen/AMDGPU/extractelt-to-trunc.ll
The file was modifiedllvm/test/CodeGen/X86/psadbw.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/idot8s.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/idot4u.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/idot4s.ll
The file was modifiedllvm/test/CodeGen/AArch64/vecreduce-and-legalization.ll
The file was modifiedllvm/test/CodeGen/X86/vector-reduce-mul.ll
Commit cb54c13c217b3e5fcda5c97bab229c1f9c3934b7 by usx
[clang][analyzer] Modify include AllocationState.h in PutenvWithAutoChecker.cpp

Summary:
PutenvWithAutoChecker.cpp used to include "AllocationState.h" that is present in project root.
This makes build systems like blaze unhappy. Made it include the header relative to source file.

Reviewers: kadircet

Subscribers: xazax.hun, baloghadamsoftware, szepet, a.sidorin, mikhail.ramalho, Szelethus, donat.nagy, dkrupp, Charusso, martong, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D74906
The file was modifiedclang/lib/StaticAnalyzer/Checkers/cert/PutenvWithAutoChecker.cpp
Commit 12cc105f806f5a7e7c14350c5ba54654e263c972 by craig.topper
[X86] Add DAG combines to form CVTPH2PS/CVTPS2PH from vXf16->vXf32/vXf64 fp_extends and vXf32->vXf16 fp_round.

Only handle power of 2 element count for simplicity. Not sure what to do with vXf64->vXf16 fp_round to avoid double rounding

Differential Revision: https://reviews.llvm.org/D74886
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/half.ll
The file was modifiedllvm/test/CodeGen/X86/vector-half-conversions.ll
Commit ce70e2899879e092b153a4078b993833b6696713 by danilo.carvalho.grael
[AArch64][SVE] Add intrinsics for SVE2 bitwise ternary operations

Summary:
Add intrinsics for the following operations:
- eor3, bcax
- bsl, bsl1n, bsl2n, nbsl

Reviewers: kmclaughlin, c-rhodes, sdesmalen, efriedma, rengolin

Reviewed By: efriedma

Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D74785
The file was modifiedllvm/include/llvm/IR/IntrinsicsAArch64.td
The file was modifiedllvm/lib/Target/AArch64/SVEInstrFormats.td
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
The file was addedllvm/test/CodeGen/AArch64/sve2-bitwise-ternary.ll
Commit 914a97a4e6184234ea231321c3073e021e0c60c7 by spatel
[x86] add vector tests for splatted memory ops; NFC

These correspond to patterns seen in PR42024:
https://bugs.llvm.org/show_bug.cgi?id=42024
The file was modifiedllvm/test/CodeGen/X86/x86-interleaved-access.ll
Commit 9bbf271fc9d5b84f9e657805dfff0fb8a1607af4 by craig.topper
[AArch64] Move isOverflowIntrOpRes help function to the ISD namespace in SelectionDAG.h. NFC

Enables sharing with an upcoming X86 change.
The file was modifiedllvm/include/llvm/CodeGen/SelectionDAGNodes.h
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Commit 3543ac9ab52df77af55a2ebdeeddfb76aba15d29 by craig.topper
[X86] Rewrite LowerBRCOND to remove dead code and handle ISD::SETCC and overflow ops directly.

There's a lot of old leftover code in LowerBRCOND. Especially
the detecting or AND or OR of X86ISD::SETCC nodes. Those were
needed before LegalizeDAG was changed to visit nodes before
their operands.

It also relied on reversing the output of LowerSETCC to find the
flags producing node to use for the X86ISD::BRCOND node.

Rather than using LowerSETCC this patch uses emitFlagsForSetcc to
handle the integer ISD::SETCC case. This gives the flag producer
and the comparison code to use directly. I've removed the addTest
flag and just produce a X86ISD::BRCOND and return immediately.

Floating point ISD::SETCC case is just an X86ISD::FCMP with special
care for OEQ and UNE derived from the previous code. I've left
f128 out so it will emit a test. And LowerSETCC will be called
later to produce a libcall and X86ISD::SETCC. We have combines
that can merge the test and X86ISD::SETCC.

We need to handle two cases for overflow ops. Either they are used
directly or they have a seteq 0 or setne 1 to invert the overflow.
The old code did not handle the setne 1 case, but I think some
other combines were making up for it.

If we fail to find a condition, we'll wrap an AND with 1 on the
original condition and tell emitFlagsForSetcc to emit a compare
with 0. This will pickup the LowerAndToBT and or the EmitTest case.
I kept the isTruncWithZeroHighBitsInput call, but we might be able
to fold that in to emitFlagsForSetcc.

Differential Revision: https://reviews.llvm.org/D74750
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit e442f38395f71b680bc1174568e461b5ff1f7ebf by Louis Dionne
[libc++] Fix unintended ADL inside ref(reference_wrapper<T>) and cref(reference_wrapper<T>)

This patch qualifies calls to ref and cref inside ref(reference_wrapper<T>)
and cref(reference_wrapper<T>), respectively. These previously unqualified
calls could break in the presence of user functions called ref/cref inside
associated namespaces: https://gcc.godbolt.org/z/8VfprT

Fixes PR44398.

Differential Revision: https://reviews.llvm.org/D74287
The file was modifiedlibcxx/test/std/utilities/function.objects/refwrap/refwrap.helpers/cref_2.pass.cpp
The file was modifiedlibcxx/test/std/utilities/function.objects/refwrap/refwrap.helpers/ref_2.pass.cpp
The file was modifiedlibcxx/include/__functional_base
Commit 092a57f5082146b6770f89839666b7545a0d27f0 by Louis Dionne
[libc++] Fix unqualified call to 'ref' inside shared_ptr(unique_ptr<U, D>)

This prevents unintended ADL: https://gcc.godbolt.org/z/EHw3Gy
This issue was mentioned as an addendum in PR44398.

Differential Revision: https://reviews.llvm.org/D74289
The file was modifiedlibcxx/include/memory
The file was modifiedlibcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.const/unique_ptr.pass.cpp
Commit db8911aad726d050fb36f17f2978bd35f69165cc by n.james93
[clang-tidy] rename_check.py: maintain alphabetical order in Renamed checks section

Summary:
Also use //check// in add_new_check.py for terminology consistency.

PS

My GitHub ID is [[ https://github.com/EugeneZelenko | EugeneZelenko ]], if it's necessary for attribution.

Reviewers: alexfh, hokein, aaron.ballman, njames93, MyDeveloperDay

Reviewed By: njames93

Subscribers: Andi, xazax.hun, cfe-commits

Tags: #clang-tools-extra, #clang

Differential Revision: https://reviews.llvm.org/D73580
The file was modifiedclang-tools-extra/clang-tidy/rename_check.py
The file was modifiedclang-tools-extra/docs/ReleaseNotes.rst
The file was modifiedclang-tools-extra/clang-tidy/add_new_check.py
Commit 0ed7a61543840ddfe4dcc71307dd77b032dcca6c by craig.topper
[X86] Fix a -Wparentheses warning. NFC
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp