1. [DWARFYAML][debug_abbrev] Emit 0 byte for terminating abbreviations. (details)
  2. [Outliner] Set nounwind for outlined functions (details)
  3. [InstCombine] Don't let an alignment assume prevent new/delete removals. (details)
  4. [Alignment][NFC] Use Align for BPFAbstractMemberAccess::RecordAlignment (details)
  5. [ms] [llvm-ml] Use default RIP-relative addressing for x64 MASM. (details)
  6. [CVP] Use different number in test (NFC) (details)
  7. [NFC] Clean up uses of MachineModuleInfoWrapperPass (details)
  8. Change the INLINEASM_BR MachineInstr to be a non-terminating instruction. (details)
  9. [BPF] Fix a BTF gen bug related to a pointer struct member (details)
  10. [Coroutines] Fix code coverage for coroutine (details)
  11. [AArch64] Remove unnecessary CostKindCheck (NFC). (details)
  12. sanitizer_common_interceptors: Fix lint errors (details)
  13. Revert "Improve the detection of iOS/tvOS/watchOS simulator binaries in" (details)
  14. [CodeGen] Fix warnings in DAGCombiner::visitSCALAR_TO_VECTOR (details)
Commit 38907b696c0e31d2269ec4b8966bf603c36b579c by Xing
[DWARFYAML][debug_abbrev] Emit 0 byte for terminating abbreviations.

The abbreviations for a given compilation unit end with an entry
consisting of a 0 byte for the abbreviation code.

Reviewed By: jhenderson

Differential Revision:
The file was modifiedllvm/lib/ObjectYAML/DWARFEmitter.cpp
The file was modifiedllvm/test/ObjectYAML/MachO/DWARF2-AddrSize8-FormValues.yaml
The file was modifiedllvm/test/tools/yaml2obj/ELF/DWARF/debug-abbrev.yaml
The file was modifiedllvm/test/tools/yaml2obj/ELF/DWARF/debug-info.yaml
Commit ca4c1ad854ab9baf510e489d81625cace991beb1 by
[Outliner] Set nounwind for outlined functions

This prevents the outlined functions from pulling in a lot of unnecessary code
in our downstream libraries/linker. Which stops outlining making codesize
worse in c++ code with no-exceptions.

Differential Revision:
The file was modifiedllvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-v8-3.ll
The file was modifiedllvm/test/CodeGen/AArch64/machine-outliner.ll
The file was addedllvm/test/CodeGen/AArch64/machine-outliner-throw2.ll
The file was modifiedllvm/lib/CodeGen/MachineOutliner.cpp
The file was modifiedllvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-cfi.ll
The file was addedllvm/test/CodeGen/AArch64/machine-outliner-throw.ll
The file was modifiedllvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-same-scope-same-key-b.ll
Commit 6bd1db08e7ccd61996d3867d22ff8eb1979f8621 by yamauchi
[InstCombine] Don't let an alignment assume prevent new/delete removals.

Remove allocations with alignment assume.

Differential Revision:
The file was modifiedllvm/lib/Transforms/InstCombine/InstructionCombining.cpp
The file was modifiedllvm/test/Transforms/InstCombine/malloc-free-delete.ll
The file was modifiedllvm/test/Transforms/PhaseOrdering/inlining-alignment-assumptions.ll
Commit 0f9d623b63e87b4ba30c30fd884ecc333eb32b4a by gchatelet
[Alignment][NFC] Use Align for BPFAbstractMemberAccess::RecordAlignment

This patch is part of a series to introduce an Alignment type.
See this thread for context:
See this patch for the introduction of the type:

Differential Revision:
The file was modifiedllvm/lib/Target/BPF/BPFAbstractMemberAccess.cpp
Commit 353a169cb814334e47bc2e98f03931e62023665a by epastor
[ms] [llvm-ml] Use default RIP-relative addressing for x64 MASM.

When parsing 64-bit MASM, treat memory operands with unspecified base register as RIP-based.

Documented in several places, including "Unfortunately, MASM does not allow this form of opcode, but other assemblers like FASM and YASM do. Instead, MASM embeds RIP-relative addressing implicitly."

Reviewed By: thakis

Differential Revision:
The file was addedllvm/test/tools/llvm-ml/rip-relative-addressing.test
The file was modifiedllvm/lib/MC/MCParser/MasmParser.cpp
The file was modifiedllvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
The file was modifiedllvm/lib/Target/X86/AsmParser/X86Operand.h
The file was modifiedllvm/include/llvm/MC/MCParser/MCAsmParser.h
Commit 0f6afd946d25a2e83288339934f8fa384e38eea3 by nikita.ppv
[CVP] Use different number in test (NFC)

To make it clear that this is not intended to be specific to
mask / bit tests.
The file was modifiedllvm/test/Transforms/CorrelatedValuePropagation/icmp.ll
Commit 78c69a00a4cff786e0ef13c895d0db309d6b3f42 by Yuanfang Chen
[NFC] Clean up uses of MachineModuleInfoWrapperPass
The file was modifiedllvm/lib/CodeGen/BranchFolding.cpp
The file was modifiedllvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64SLSHardening.cpp
The file was modifiedllvm/lib/Target/X86/X86IndirectThunks.cpp
The file was modifiedllvm/lib/Target/X86/X86InsertPrefetch.cpp
The file was modifiedllvm/lib/CodeGen/BranchFolding.h
The file was modifiedllvm/lib/CodeGen/UnreachableBlockElim.cpp
The file was modifiedllvm/lib/CodeGen/GCRootLowering.cpp
The file was modifiedllvm/lib/CodeGen/BBSectionsPrepare.cpp
The file was modifiedllvm/lib/CodeGen/IfConversion.cpp
The file was modifiedllvm/lib/CodeGen/MachineBlockPlacement.cpp
Commit 4b0aa5724feaa89a9538dcab97e018110b0e4bc3 by jyknight
Change the INLINEASM_BR MachineInstr to be a non-terminating instruction.

Before this instruction supported output values, it fit fairly
naturally as a terminator. However, being a terminator while also
supporting outputs causes some trouble, as the physreg->vreg COPY
operations cannot be in the same block.

Modeling it as a non-terminator allows it to be handled the same way
as invoke is handled already.

Most of the changes here were created by auditing all the existing
users of MachineBasicBlock::isEHPad() and
MachineBasicBlock::hasEHPadSuccessor(), and adding calls to
isInlineAsmBrIndirectTarget or mayHaveInlineAsmBr, as appropriate.

Reviewed By: nickdesaulniers, void

Differential Revision:
The file was modifiedllvm/include/llvm/CodeGen/MachineBasicBlock.h
The file was modifiedllvm/include/llvm/Target/
The file was modifiedllvm/test/CodeGen/AArch64/callbr-asm-obj-file.ll
The file was modifiedllvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
The file was modifiedllvm/test/CodeGen/X86/callbr-asm-branch-folding.ll
The file was modifiedllvm/test/CodeGen/X86/callbr-asm-outputs-pred-succ.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
The file was modifiedllvm/lib/Target/Hexagon/BitTracker.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
The file was modifiedllvm/test/CodeGen/X86/callbr-asm-blockplacement.ll
The file was modifiedllvm/test/CodeGen/X86/callbr-asm-outputs.ll
The file was modifiedllvm/lib/CodeGen/MachineBasicBlock.cpp
The file was modifiedllvm/test/CodeGen/AArch64/callbr-asm-label.ll
The file was modifiedllvm/test/CodeGen/ARM/ifcvt-size.mir
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
The file was modifiedllvm/lib/CodeGen/TailDuplicator.cpp
The file was addedllvm/test/CodeGen/X86/callbr-asm-instr-scheduling.ll
The file was modifiedllvm/lib/CodeGen/MachineSink.cpp
The file was modifiedllvm/lib/CodeGen/ShrinkWrap.cpp
The file was modifiedllvm/test/CodeGen/X86/callbr-asm-label-addr.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.cpp
The file was modifiedllvm/test/CodeGen/X86/callbr-asm.ll
The file was modifiedllvm/test/CodeGen/ARM/ifcvt-diamond-unanalyzable-common.mir
The file was modifiedllvm/lib/CodeGen/TargetInstrInfo.cpp
The file was modifiedllvm/lib/CodeGen/SplitKit.h
The file was modifiedllvm/test/Verifier/callbr.ll
The file was modifiedllvm/lib/CodeGen/BranchFolding.cpp
The file was modifiedllvm/lib/CodeGen/MachineVerifier.cpp
The file was modifiedllvm/lib/CodeGen/PHIEliminationUtils.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
The file was modifiedllvm/lib/CodeGen/RegisterCoalescer.cpp
The file was modifiedllvm/include/llvm/CodeGen/ISDOpcodes.h
The file was modifiedllvm/lib/Target/PowerPC/PPCBranchCoalescing.cpp
The file was addedllvm/test/CodeGen/X86/shrinkwrap-callbr.ll
The file was modifiedllvm/lib/CodeGen/SplitKit.cpp
Commit 3eacfdc72f1aa3ac53eb300116f194d560053ec7 by yhs
[BPF] Fix a BTF gen bug related to a pointer struct member

Currently, BTF generation stops at pointer struct members
if the pointee type is a struct. This is to avoid bloating
generated BTF size. The following is the process to
correctly record types for these pointee struct types.
  - During type traversal stage, when a struct member, which
    is a pointer to another struct, is encountered,
    the pointee struct type, keyed with its name, is
    remembered in a Fixup map.
  - Later, when all type traversal is done, the Fixup map
    is scanned, based on struct name matching, to either
    resolve as pointing to a real already generated type
    or as a forward declaration.

Andrii discovered a bug if the struct member pointee struct
is anonymous. In this case, a struct with empty name is
recorded in Fixup map, and later it happens another anonymous
struct with empty name is defined in BTF. So wrong type
resolution happens.

To fix the problem, if the struct member pointee struct
is anonymous, pointee struct type will be generated in
stead of being put in Fixup map.

Differential Revision:
The file was modifiedllvm/lib/Target/BPF/BTFDebug.cpp
The file was addedllvm/test/CodeGen/BPF/BTF/struct-anon-2.ll
Commit 565e37c7702d181804c12d36b6010c513c9b3417 by xun
[Coroutines] Fix code coverage for coroutine

Previously, source-based coverage analysis does not work properly for coroutine.
This patch adds processing of coroutine body and co_return in the coverage analysis, so that we can handle them properly.
For coroutine body, we should only look at the actual function body and ignore the compiler-generated things; for co_return, we need to terminate the region similar to return statement.
Added a test, and confirms that it now works properly. (without this patch, the statement after the if statement will be treated wrongly)

Reviewers: lewissbaker, modocache, junparser

Reviewed By: modocache

Subscribers: cfe-commits

Tags: #clang

Differential Revision:
The file was modifiedclang/lib/CodeGen/CoverageMappingGen.cpp
The file was addedclang/test/CoverageMapping/coroutine.cpp
Commit c30da98d478e547428a723354b4fd1e45a7f7003 by flo
[AArch64] Remove unnecessary CostKindCheck (NFC).

Simplification suggested post-commit.
The file was modifiedllvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
Commit cc4d523bb600cbf129242dee3167e3acf1d37a6a by guiand
sanitizer_common_interceptors: Fix lint errors
The file was modifiedcompiler-rt/lib/sanitizer_common/
Commit 98c3a38a1967ece4e70891aa188c51e29ca0f8d3 by Jonas Devlieghere
Revert "Improve the detection of iOS/tvOS/watchOS simulator binaries in"

This reverts commit 0da0437b2afbd8ebef6b11f114cca33b118e7639 to unbreak
the following tests:
The file was modifiedlldb/tools/debugserver/source/DNB.cpp
The file was modifiedlldb/source/Plugins/DynamicLoader/MacOSX-DYLD/DynamicLoaderDarwin.cpp
The file was modifiedlldb/test/API/macosx/simulator/
The file was modifiedlldb/tools/debugserver/source/MacOSX/
The file was modifiedlldb/tools/debugserver/source/MacOSX/MachProcess.h
Commit f11305780f08969488add6c84439fc91d18692dc by david.sherwood
[CodeGen] Fix warnings in DAGCombiner::visitSCALAR_TO_VECTOR

In visitSCALAR_TO_VECTOR we try to optimise cases such as:

  scalar_to_vector (extract_vector_elt %x)

into vector shuffles of %x. However, it led to numerous warnings
when %x is a scalable vector type, so for now I've changed the
code to only perform the combination on fixed length vectors.
Although we probably could change the code to work with scalable
vectors in certain cases, without a proper profit analysis it
doesn't seem worth it at the moment.

This change fixes up one of the warnings in:


I've also added a simplified version of the same test to:


which already has checks for no warnings.

Differential Revision:
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
The file was modifiedllvm/test/CodeGen/AArch64/sve-fp.ll