Commit
667e1f71b83c48b635b13b64bbff28b95e68265c
by Tim NorthoverIR: remove "else" after "return". NFCI.
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 | llvm/lib/IR/Core.cpp |
Commit
d857e114b5e04f5143485a5aea7ad9b283768692
by simon.tatham[ARM,MVE] Fix valid immediate range for vsliq_n. In common with most MVE immediate shift instructions, the left shift takes an immediate in the range [0,n-1], while the right shift takes one in the range [1,n]. I had absent-mindedly made them both the latter. While I'm here, I've added a set of regression tests checking both ends of the immediate range for a representative sample of the immediate shifts.
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 | clang/include/clang/Basic/arm_mve.td |
 | clang/test/Sema/arm-mve-immediates.c |
Commit
9704ba652a0062c53ec66b068766df5c0cd5c620
by simon.tatham[ARM,MVE] Add missing IntrNoMem flag on IR intrinsics. A lot of the IR-level intrinsics we've been defining for MVE recently accidentally had `props = []` instead of `props = [IntrNoMem]`, so that optimization would have been overcautious about reordering them. All the affected cases were due to instantiating the multiclasses `MVEPredicated` and `MVEMXPredicated` without filling in the `props` parameter, because I //thought// I remembered having set the defaults in those multiclasses to `[IntrNoMem]`. In fact I hadn't done that. Now I have. (The IR intrinsics that //do// read and write memory are all explicitly marked as `[IntrReadMem]` or `[IntrWriteMem]` already, so they will override these defaults.)
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 | llvm/include/llvm/IR/IntrinsicsARM.td |
Commit
db7c92077963195df0807e976cc916b5c6e29a05
by arsenm2AMDGPU: Add register class to DS_SWIZZLE_B32 pattern Reduces diff for a future patch.
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 | llvm/lib/Target/AMDGPU/DSInstructions.td |
Commit
0274ed9dc75a0efb2b6130122226ee45f7e57dde
by arsenm2TableGen/GlobalISel: Fix slightly wrong generated comment
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 | llvm/test/TableGen/GlobalISelEmitter.td |
 | llvm/utils/TableGen/GlobalISelEmitter.cpp |
Commit
3952748ffdf017f83faddcb1240cb36cb4bb9c5b
by arsenm2AMDGPU/GlobalISel: Fix add of neg inline constant pattern
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 | llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp |
 | llvm/lib/Target/AMDGPU/SIInstructions.td |
 | llvm/lib/Target/AMDGPU/AMDGPUGISel.td |
 | llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.mir |
Commit
d964086c62422771c1d6dbe66ee8ea06e8f834b2
by arsenm2AMDGPU/GlobalISel: Add equiv xform for bitcast_fpimm_to_i32 Only partially fixes one pattern import.
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 | llvm/lib/Target/AMDGPU/AMDGPUGISel.td |
 | llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp |
 | llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h |
Commit
79450a4ea26a0e9731eaf2629f6dd8c1ffd8f407
by arsenm2AMDGPU/GlobalISel: Add selectVOP3Mods_nnan This doesn't enable any new imports yet, but moves the fmed patterns from failing on this to hitting the "complex suboperand referenced more than once" limitation in tablegen.
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 | llvm/lib/Target/AMDGPU/AMDGPUGISel.td |
 | llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp |
 | llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h |
Commit
e71af775684a83f0d1d05ab5225d36830d5aa87e
by arsenm2AMDGPU/GlobalISel: Add IMMPopCount xform Partially fixes BFE pattern import.
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 | llvm/lib/Target/AMDGPU/AMDGPUGISel.td |
 | llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp |
 | llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h |
Commit
7d677421607cbfdd8d1e96275c613d3db8a0e51f
by arsenm2AMDGPU/GlobalISel: Fix import of zext of s16 op patterns
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 | llvm/lib/Target/AMDGPU/VOP2Instructions.td |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.s16.mir |
 | llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.s16.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.s16.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.s16.mir |
Commit
c1d4963b447c9330c2ad50bb73bb93f9a42c9641
by arsenm2AMDGPU: Use new PatFrag system for d16 load nodes
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 | llvm/lib/Target/AMDGPU/SIInstrInfo.td |
Commit
3766f4baccac5cc17680ad4cefd1d5a0d3ba2870
by arsenm2AMDGPU: Use new PatFrag system for d16 stores
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 | llvm/lib/Target/AMDGPU/AMDGPUInstructions.td |
 | llvm/lib/Target/AMDGPU/DSInstructions.td |
Commit
c66b2e1c87ecde72eb37d3452ec9c1b8766ede30
by arsenm2AMDGPU: Eliminate more legacy codepred address space PatFrags These should now be limited to R600 code.
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 | llvm/lib/Target/AMDGPU/AMDGPUInstructions.td |
 | llvm/lib/Target/AMDGPU/R600Instructions.td |
 | llvm/lib/Target/AMDGPU/BUFInstructions.td |
 | llvm/lib/Target/AMDGPU/FLATInstructions.td |
Commit
9ffd0ed838191247e0da7df5e28e54a5129e76a7
by arsenm2AMDGPU/GlobalISel: Fix import of integer med3 This isn't too useful now, since nothing is currently trying to form min/max from cmp+select.
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 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-smed3.s16.mir |
 | llvm/lib/Target/AMDGPU/SIInstructions.td |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-umed3.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-umed3.s16.mir |
 | llvm/lib/Target/AMDGPU/AMDGPUInstructions.td |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-smed3.mir |