SuccessChanges

Summary

  1. [flang] Fix bogus error message with binding (details)
  2. [NFC] [TargetRegisterInfo] add another API to get srcreg through copy. (details)
  3. [RISCV] Add a VL output to vleff intrinsics. (details)
  4. [llvm-mca] Addressing build failures due to missing override specifiers (details)
  5. [mlir] Support FuncOpSignatureConversion for more FunctionLike ops. (details)
  6. [CodeGen][ObjC] Fix broken IR generated when there is a nil receiver (details)
  7. [AMDGPU] Test case demonstrating issues with generation of .debug_frame (details)
  8. [PowerPC] Duplicate inherited heuristic from base scheduler (details)
  9. [Inlining] Delete redundant optnone/alwaysinline check (details)
  10. [RISCV] Add intrinsics for RVV 1.0 vrgatherei16 (details)
  11. [RISCV] Add intrinsics for vector unordered indexed load in RVV 1.0 (details)
  12. [RISCV] Add intrinsics for RVV1.0 VFRSQRTE7 & VFRECE7 (details)
Commit 2de5ea3b3ed9882026d9dc6c5d8ec462ebe5f8ec by pklausler
[flang] Fix bogus error message with binding

ProcedureDesignator::GetInterfaceSymbol() needs to return
the procedure bound to a bindings.

Differential Revision: https://reviews.llvm.org/D95178
The file was modifiedflang/lib/Semantics/check-declarations.cpp
The file was addedflang/test/Semantics/call17.f90
The file was modifiedflang/lib/Evaluate/call.cpp
The file was modifiedflang/test/Semantics/resolve88.f90
Commit 8120cfedf55ade13a0a1a4a4629911aa2f8ed9c3 by czhengsz
[NFC] [TargetRegisterInfo] add another API to get srcreg through copy.

Reviewed By: nemanjai, jsji

Differential Revision: https://reviews.llvm.org/D92069
The file was modifiedllvm/lib/CodeGen/TargetRegisterInfo.cpp
The file was modifiedllvm/include/llvm/CodeGen/TargetRegisterInfo.h
Commit 3b5430eb0dad5b239d0671503f73f6b713aaaf40 by craig.topper
[RISCV] Add a VL output to vleff intrinsics.

The fault-only-first-load instructions can reduce VL if an element
other than element 0 triggers a memory fault. This can be used to
vectorize loops with data dependent exit conditions like strcmp or
strlen.

This patch adds a VL output to these intrinsics so that the new
VL value can be captured by software. This will be expanded to
'csrr gpr, vl' after the vleff instruction during SelectionDAG.

By doing this with one intrinsic we are able to guarantee that the
csrr reads the VL value produced by the vleff instruction. Having
it as a separate intrinsic would make it impossible to guarantee
ordering without making every other vector intrinsic have side
effects.

The intrinsics are expanded during lowering into two ISD nodes
that are glued together. These ISD nodes will go
through isel separately, but should maintain the glue so that they
get emitted adjacently by InstrEmitter.

I've only ran the chain through the vleff instruction, allowing
the READ_VL to be deleted if it is unused.

Reviewed By: HsiangKai

Differential Revision: https://reviews.llvm.org/D94286
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vleff-rv32.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.h
The file was modifiedllvm/lib/Target/RISCV/RISCVMCInstLower.cpp
The file was modifiedllvm/include/llvm/IR/IntrinsicsRISCV.td
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vleff-rv64.ll
Commit c6e8f81410a2942b5abd112aa6e468268e01d946 by wolfgang_pieb
[llvm-mca] Addressing build failures due to missing override specifiers
The file was modifiedllvm/tools/llvm-mca/Views/ResourcePressureView.h
The file was modifiedllvm/tools/llvm-mca/Views/TimelineView.h
The file was modifiedllvm/tools/llvm-mca/Views/InstructionInfoView.h
The file was modifiedllvm/tools/llvm-mca/Views/InstructionInfoView.cpp
Commit 0a7a1ac73d095eacd4499e889ce35191a9d1c648 by mikeurbach
[mlir] Support FuncOpSignatureConversion for more FunctionLike ops.

This extracts the implementation of getType, setType, and getBody from
FunctionSupport.h into the mlir::impl namespace and defines them
generically in FunctionSupport.cpp. This allows them to be used
elsewhere for any FunctionLike ops that use FunctionType for their
type signature.

Using the new helpers, FuncOpSignatureConversion is generalized to
work with all such FunctionLike ops. Convenience helpers are added to
configure the pattern for a given concrete FunctionLike op type.

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D95021
The file was modifiedmlir/include/mlir/Transforms/DialectConversion.h
The file was modifiedmlir/include/mlir/IR/FunctionSupport.h
The file was modifiedmlir/lib/Transforms/Utils/DialectConversion.cpp
The file was modifiedmlir/lib/IR/FunctionSupport.cpp
Commit 3d349ed7e1108686271a09314dafaa356df4006d by Akira
[CodeGen][ObjC] Fix broken IR generated when there is a nil receiver
check

This patch fixes a bug in emitARCOperationAfterCall where it inserts the
fall-back call after a bitcast instruction and then replaces the
bitcast's operand with the result of the fall-back call. The generated
IR without this patch looks like this:

msgSend.call:                                     ; preds = %entry
  %call = call i8* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend
  br label %msgSend.cont

msgSend.null-receiver:                            ; preds = %entry
  call void @llvm.objc.release(i8* %4)
  br label %msgSend.cont

msgSend.cont:
  %8 = phi i8* [ %call, %msgSend.call ], [ null, %msgSend.null-receiver ]
  %9 = bitcast i8* %10 to %0*
  %10 = call i8* @llvm.objc.retain(i8* %8)

Notice that `%9 = bitcast i8* %10` to %0* is taking operand %10 which is
defined after it.

To fix the bug, this patch modifies the insert point to point to the
bitcast instruction so that the fall-back call is inserted before the
bitcast. In addition, it teaches the function to look at phi
instructions that are generated when there is a check for a null
receiver and insert the retainRV/claimRV instruction right after the
call instead of inserting a fall-back call right after the phi
instruction.

rdar://73360225

Differential Revision: https://reviews.llvm.org/D95181
The file was modifiedclang/test/CodeGenObjC/ns_consume_null_check.m
The file was modifiedclang/lib/CodeGen/CGObjC.cpp
Commit b6c3a59c3f550ab9214de3988419fe1cb68679c9 by VenkataRamanaiah.Nalamothu
[AMDGPU] Test case demonstrating issues with generation of .debug_frame

This test case demonstrates that the Call Frame Information generation is
totally biased towards whether exceptions are enabled or not. Currently
LLVM does not generate CFI i.e. a .debug_frame for debug purpose even
if --force-dwarf-frame-section is enabled unless exceptions are enabled.

Reviewed By: scott.linder

Differential Revision: https://reviews.llvm.org/D94801
The file was addedllvm/test/CodeGen/AMDGPU/debug_frame.ll
Commit 449f2f7140e1d70d9c08bb609cde6cdd144c6035 by qiucofan
[PowerPC] Duplicate inherited heuristic from base scheduler

PowerPC has its custom scheduler heuristic. It calls parent classes'
tryCandidate in override version, but the function returns void, so this
way doesn't actually help. This patch duplicates code from base scheduler
into PPC machine scheduler class, which does what we wanted.

Reviewed By: steven.zhang

Differential Revision: https://reviews.llvm.org/D94464
The file was modifiedllvm/test/CodeGen/PowerPC/mma-phi-accs.ll
The file was modifiedllvm/test/CodeGen/PowerPC/loop-instr-form-prepare.ll
The file was modifiedllvm/test/CodeGen/PowerPC/more-dq-form-prepare.ll
The file was modifiedllvm/test/CodeGen/PowerPC/lsr-ctrloop.ll
The file was modifiedllvm/test/CodeGen/PowerPC/sched-addi.ll
The file was modifiedllvm/test/CodeGen/PowerPC/botheightreduce.mir
The file was modifiedllvm/test/CodeGen/PowerPC/rematerializable-instruction-machine-licm.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCMachineScheduler.cpp
The file was modifiedllvm/test/CodeGen/PowerPC/sms-simple.ll
The file was modifiedllvm/test/CodeGen/PowerPC/sms-phi-1.ll
The file was modifiedllvm/test/CodeGen/PowerPC/mma-intrinsics.ll
The file was modifiedllvm/test/CodeGen/PowerPC/stack-clash-dynamic-alloca.ll
The file was modifiedllvm/test/CodeGen/PowerPC/sms-cpy-1.ll
Commit bd3ca6666d14464b1bb7eecbd3cc227ee0614799 by lxfind
[Inlining] Delete redundant optnone/alwaysinline check

The same check is done in InlineCost: https://github.com/llvm/llvm-project/blob/8b0bd54d0ec968df28ccc58bbb537a7b7c074ef2/llvm/lib/Analysis/InlineCost.cpp#L2537-L2552
Also, doing a check on the callee here is confusing, because anything that deals with callee should be done in the inner loop where we proecss all calls from the same caller.

Differential Revision: https://reviews.llvm.org/D95186
The file was modifiedllvm/lib/Transforms/IPO/Inliner.cpp
Commit bea661d9a52f9abb4fef7cf195092e912c165d34 by shihpo.hung
[RISCV] Add intrinsics for RVV 1.0 vrgatherei16

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D95014
The file was modifiedllvm/include/llvm/IR/IntrinsicsRISCV.td
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
The file was addedllvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv64.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv32.ll
Commit 976cf53cc7a5dd03932a6e44b8a9350a05cdaa68 by shihpo.hung
[RISCV] Add intrinsics for vector unordered indexed load in RVV 1.0

Add unordered indexed load: vluxei

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D95028
The file was modifiedllvm/include/llvm/IR/IntrinsicsRISCV.td
The file was addedllvm/test/CodeGen/RISCV/rvv/vluxei-rv64.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vluxei-rv32.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
Commit 96677503315e689fd3c8f5ef164d8fb9725d4bb3 by shihpo.hung
[RISCV] Add intrinsics for RVV1.0 VFRSQRTE7 & VFRECE7

Reviewed By: craig.topper, frasercrmck

Differential Revision: https://reviews.llvm.org/D95113
The file was addedllvm/test/CodeGen/RISCV/vfrsqrte7-rv32.ll
The file was addedllvm/test/CodeGen/RISCV/vfrece7-rv32.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
The file was modifiedllvm/include/llvm/IR/IntrinsicsRISCV.td
The file was addedllvm/test/CodeGen/RISCV/vfrece7-rv64.ll
The file was addedllvm/test/CodeGen/RISCV/vfrsqrte7-rv64.ll