Commit
3dedad475da45c05bc4f66cd14e9f44581edf0bc
by Amara Emerson[AArch64][GlobalISel] Make G_USUBO legal and select it.
The expansion for wide subtractions includes G_USUBO.
Differential Revision: https://reviews.llvm.org/D95032
|
 | llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir |
 | llvm/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir |
 | llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp |
 | llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir |
 | llvm/test/CodeGen/AArch64/GlobalISel/select-saddo.mir |
 | llvm/test/CodeGen/AArch64/GlobalISel/select-ssubo.mir |
 | llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp |
 | llvm/test/CodeGen/AArch64/GlobalISel/select-usubo.mir |
Commit
f8f1b20e6b30624d2c0d18dc6a2d61643650d0c4
by craig.topper[RISCV] Don't create LMUL=8 pseudo instructions for ternary widening arithmetic instructions
These instructions produce 2*SEW result so the input can't have an LMUL=8 or the result would need a non-existant LMUL=16. So only create pseudos for LMUL up to 4.
Differential Revision: https://reviews.llvm.org/D95189
|
 | llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td |
Commit
5d354220d44f11c70f36d5a357ec2a2208a6ab92
by kai.wang[RISCV] Correct DWARF number for vector registers.
The DWARF numbers of vector registers are already defined in riscv-elf-psabi. The DWARF number for vector is start from 96. Correct the DWARF numbers of vector registers.
Differential Revision: https://reviews.llvm.org/D94749
|
 | llvm/lib/Target/RISCV/RISCVRegisterInfo.td |
Commit
be611431cd1f5c826a55b531db92a63e84323866
by aeubanks[NewPM][opt] Run the "default" AA pipeline by default
We tend to assume that the AA pipeline is by default the default AA pipeline and it's confusing when it's empty instead.
PR48779
Reviewed By: asbirlea
Differential Revision: https://reviews.llvm.org/D95117
|
 | llvm/test/Transforms/LoopVectorize/PowerPC/optimal-epilog-vectorization.ll |
 | llvm/test/Transforms/LoopVectorize/optimal-epilog-vectorization.ll |
 | llvm/test/Analysis/MemorySSA/pr43569.ll |
 | llvm/test/Transforms/ThinLTOBitcodeWriter/pr33536.ll |
 | llvm/test/Other/loop-pm-invalidation.ll |
 | llvm/test/Other/pass-pipeline-parsing.ll |
 | llvm/test/Transforms/Coroutines/coro-elide-musttail.ll |
 | llvm/test/Transforms/PhaseOrdering/X86/SROA-after-loop-unrolling.ll |
 | llvm/test/Transforms/LoopRotate/pr35210.ll |
 | llvm/test/Transforms/Coroutines/coro-retcon.ll |
 | llvm/test/Transforms/PhaseOrdering/X86/masked-memory-ops.ll |
 | llvm/test/Transforms/LoopVersioningLICM/loopversioningLICM1.ll |
 | llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-mod.ll |
 | llvm/test/Other/new-pm-lto-defaults.ll |
 | llvm/test/Other/new-pm-thinlto-prelink-samplepgo-defaults.ll |
 | llvm/test/Transforms/PhaseOrdering/globalaa-retained.ll |
 | llvm/test/Other/new-pm-defaults.ll |
 | llvm/test/Other/new-pm-thinlto-prelink-pgo-defaults.ll |
 | llvm/test/Transforms/PhaseOrdering/X86/addsub.ll |
 | llvm/test/Transforms/ThinLTOBitcodeWriter/split-vfunc.ll |
 | llvm/test/Other/new-pass-manager.ll |
 | llvm/test/Other/new-pm-thinlto-postlink-pgo-defaults.ll |
 | llvm/test/Other/new-pm-thinlto-defaults.ll |
 | llvm/test/Transforms/PhaseOrdering/ARM/arm_fill_q7.ll |
 | llvm/test/Transforms/PhaseOrdering/X86/vdiv.ll |
 | llvm/test/Transforms/PhaseOrdering/X86/loop-idiom-vs-indvars.ll |
 | llvm/test/Other/new-pm-pr42726-cgscc.ll |
 | llvm/tools/opt/NewPMDriver.cpp |
 | llvm/test/Transforms/SimplifyCFG/X86/invalidate-dom.ll |
 | llvm/test/Transforms/PhaseOrdering/instcombine-sroa-inttoptr.ll |
 | llvm/test/Other/new-pm-thinlto-postlink-samplepgo-defaults.ll |
 | llvm/test/Transforms/OpenMP/parallel_region_merging.ll |
 | llvm/test/Transforms/LoopVersioningLICM/loopversioningLICM2.ll |
 | llvm/test/Transforms/PhaseOrdering/X86/addsub-inseltpoison.ll |
 | llvm/test/Transforms/PhaseOrdering/pr39282.ll |
 | llvm/test/Transforms/Inline/cgscc-incremental-invalidate.ll |
Commit
c5c4dbd2790736008b1c60f1b737dfb824b90144
by kazu[CodeGen] Use llvm::append_range (NFC)
|
 | llvm/lib/CodeGen/MachineVerifier.cpp |
 | llvm/lib/CodeGen/CodeGenPrepare.cpp |
 | llvm/lib/CodeGen/Analysis.cpp |
 | llvm/lib/CodeGen/MachineRegisterInfo.cpp |
 | llvm/lib/CodeGen/MIRCanonicalizerPass.cpp |
 | llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp |
 | llvm/lib/CodeGen/SplitKit.cpp |
 | llvm/lib/CodeGen/MachineCSE.cpp |
Commit
cfa241680fd6c5d804fa57406100692f923d679f
by kazu[llvm] Don't include StringSwitch.h where unnecessary (NFC)
|
 | llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp |
 | llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp |
 | llvm/lib/IR/Core.cpp |
 | llvm/lib/MC/MCParser/COFFMasmParser.cpp |
 | llvm/lib/ObjectYAML/COFFEmitter.cpp |
 | llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp |
 | llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp |
 | llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp |
 | llvm/lib/Analysis/ObjCARCInstKind.cpp |
 | llvm/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp |
 | llvm/lib/Support/X86TargetParser.cpp |
 | llvm/lib/Target/AArch64/AArch64ISelLowering.cpp |
 | llvm/tools/dsymutil/dsymutil.cpp |
 | llvm/tools/llvm-cvtres/llvm-cvtres.cpp |
Commit
551aaa24afe6d029cc96399bcece948a5217530b
by kazu[llvm] Use isDigit (NFC)
|
 | llvm/include/llvm/TableGen/Record.h |
 | llvm/lib/CodeGen/TargetLoweringBase.cpp |
 | llvm/lib/ProfileData/SampleProfReader.cpp |
 | llvm/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp |
 | llvm/lib/DebugInfo/Symbolize/Symbolize.cpp |
 | llvm/lib/IR/AsmWriter.cpp |
 | llvm/lib/Support/Triple.cpp |
Commit
aee622fa200de9ad28334cf74416f2fd5391e2ee
by jpienaar[mlir] Enable passing crash reproducer stream factory method
Add factory to create streams for logging the reproducer. Allows for more general logging (beyond file) and logging the configuration/module separately (logged in order, configuration before module).
Also enable querying filename of ToolOutputFile.
Differential Revision: https://reviews.llvm.org/D94868
|
 | mlir/docs/PassManagement.md |
 | mlir/lib/Pass/Pass.cpp |
 | llvm/include/llvm/Support/ToolOutputFile.h |
 | mlir/include/mlir/Pass/PassManager.h |
Commit
ba9b4ea4eeaef039e80df10695a11e6ed35d415a
by aeubanksRevert "[NewPM][opt] Run the "default" AA pipeline by default"
This reverts commit be611431cd1f5c826a55b531db92a63e84323866.
Other/new-pm-lto-defaults.ll failing
|
 | llvm/test/Other/new-pass-manager.ll |
 | llvm/test/Other/new-pm-thinlto-postlink-pgo-defaults.ll |
 | llvm/test/Transforms/ThinLTOBitcodeWriter/split-vfunc.ll |
 | llvm/test/Transforms/LoopVectorize/optimal-epilog-vectorization.ll |
 | llvm/test/Transforms/PhaseOrdering/X86/addsub.ll |
 | llvm/test/Transforms/PhaseOrdering/instcombine-sroa-inttoptr.ll |
 | llvm/test/Transforms/PhaseOrdering/X86/loop-idiom-vs-indvars.ll |
 | llvm/test/Transforms/PhaseOrdering/pr39282.ll |
 | llvm/test/Transforms/Coroutines/coro-elide-musttail.ll |
 | llvm/test/Other/new-pm-thinlto-prelink-pgo-defaults.ll |
 | llvm/test/Other/pass-pipeline-parsing.ll |
 | llvm/test/Transforms/Coroutines/coro-retcon.ll |
 | llvm/test/Transforms/LoopVersioningLICM/loopversioningLICM1.ll |
 | llvm/test/Transforms/PhaseOrdering/X86/vdiv.ll |
 | llvm/test/Transforms/Inline/cgscc-incremental-invalidate.ll |
 | llvm/test/Analysis/MemorySSA/pr43569.ll |
 | llvm/test/Transforms/PhaseOrdering/X86/SROA-after-loop-unrolling.ll |
 | llvm/test/Transforms/LoopVectorize/PowerPC/optimal-epilog-vectorization.ll |
 | llvm/test/Transforms/OpenMP/parallel_region_merging.ll |
 | llvm/test/Other/new-pm-thinlto-defaults.ll |
 | llvm/test/Other/new-pm-thinlto-prelink-samplepgo-defaults.ll |
 | llvm/test/Other/new-pm-thinlto-postlink-samplepgo-defaults.ll |
 | llvm/tools/opt/NewPMDriver.cpp |
 | llvm/test/Other/new-pm-lto-defaults.ll |
 | llvm/test/Transforms/ThinLTOBitcodeWriter/pr33536.ll |
 | llvm/test/Transforms/PhaseOrdering/X86/masked-memory-ops.ll |
 | llvm/test/Other/loop-pm-invalidation.ll |
 | llvm/test/Transforms/SimplifyCFG/X86/invalidate-dom.ll |
 | llvm/test/Transforms/PhaseOrdering/ARM/arm_fill_q7.ll |
 | llvm/test/Transforms/LoopVersioningLICM/loopversioningLICM2.ll |
 | llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-mod.ll |
 | llvm/test/Other/new-pm-pr42726-cgscc.ll |
 | llvm/test/Transforms/LoopRotate/pr35210.ll |
 | llvm/test/Transforms/PhaseOrdering/X86/addsub-inseltpoison.ll |
 | llvm/test/Transforms/PhaseOrdering/globalaa-retained.ll |
 | llvm/test/Other/new-pm-defaults.ll |
Commit
a11bf9a7fbd3693d6d4bca8ef2ba1d2f0758f9be
by aeubanks[AMDGPU][Inliner] Remove amdgpu-inline and add a new TTI inline hook
Having a custom inliner doesn't really fit in with the new PM's pipeline. It's also extra technical debt.
amdgpu-inline only does a couple of custom things compared to the normal inliner: 1) It disables inlining if the number of BBs in a function would exceed some limit 2) It increases the threshold if there are pointers to private arrays(?)
These can all be handled as TTI inliner hooks. There already exists a hook for backends to multiply the inlining threshold.
This way we can remove the custom amdgpu-inline pass.
This caused inline-hint.ll to fail, and after some investigation, it looks like getInliningThresholdMultiplier() was previously getting applied twice in amdgpu-inline (https://reviews.llvm.org/D62707 fixed it not applying at all, so some later inliner change must have fixed something), so I had to change the threshold in the test.
Reviewed By: rampitec
Differential Revision: https://reviews.llvm.org/D94153
|
 | llvm/include/llvm/Analysis/TargetTransformInfoImpl.h |
 | llvm/include/llvm/CodeGen/BasicTTIImpl.h |
 | llvm/lib/Analysis/TargetTransformInfo.cpp |
 | llvm/test/CodeGen/AMDGPU/opt-pipeline.ll |
 | llvm/test/Transforms/Inline/AMDGPU/inline-amdgpu-vecbonus.ll |
 | llvm/lib/Analysis/InlineCost.cpp |
 | llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp |
 | llvm/lib/Target/AMDGPU/AMDGPU.h |
 | llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp |
 | llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn |
 | llvm/test/CodeGen/AMDGPU/amdgpu-inline.ll |
 | llvm/include/llvm/Analysis/TargetTransformInfo.h |
 | llvm/test/Transforms/Inline/AMDGPU/inline-hint.ll |
 | llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h |
 | llvm/lib/Target/AMDGPU/CMakeLists.txt |
 | llvm/test/Transforms/Inline/AMDGPU/amdgpu-inline-alloca-argument.ll |
 | llvm/lib/Target/AMDGPU/AMDGPUInline.cpp |
 | llvm/test/CodeGen/AMDGPU/inline-maxbb.ll |
Commit
c042aff8860df3cad2b274bf0a495e83ae36ddee
by mtrofin[NFC] Disallow unused prefixes under llvm/test
This patch sets the default for llvm tests, with the exception of tests under Reduce, because quite a few of them use 'FileCheck' as parameter to a tool, and including a flag as that parameter would complicate matters.
The rest of the patch undo-es the lit.local.cfg changes we progressively introduced as temporary measure to avoid regressions under various directories.
Differential Revision: https://reviews.llvm.org/D95111
|
 | llvm/test/Analysis/lit.local.cfg |
 | llvm/test/MC/ARM/lit.local.cfg |
 | llvm/test/FileCheck/lit.local.cfg |
 | llvm/test/MC/AMDGPU/lit.local.cfg |
 | llvm/test/Instrumentation/HWAddressSanitizer/prologue.ll |
 | llvm/test/Instrumentation/MemorySanitizer/msan_asm_conservative.ll |
 | llvm/test/Instrumentation/MemorySanitizer/freeze.ll |
 | llvm/test/Instrumentation/MemorySanitizer/check-struct.ll |
 | llvm/test/CodeGen/lit.local.cfg |
 | llvm/test/Transforms/lit.local.cfg |
 | llvm/test/Reduce/lit.local.cfg |
 | llvm/test/Instrumentation/MemorySanitizer/array_types.ll |
 | llvm/test/Instrumentation/MemorySanitizer/msan_eager.ll |
 | llvm/test/lit.cfg.py |
 | llvm/test/Instrumentation/MemorySanitizer/msan_x86_bts_asm.ll |
 | llvm/test/MC/AArch64/lit.local.cfg |
 | llvm/test/MC/RISCV/lit.local.cfg |
 | llvm/test/Instrumentation/MemorySanitizer/reduce.ll |
 | llvm/test/Instrumentation/HWAddressSanitizer/basic.ll |
 | llvm/test/Instrumentation/MemorySanitizer/check-array.ll |
 | llvm/test/Instrumentation/AddressSanitizer/global_metadata_array.ll |
 | llvm/test/Other/lit.local.cfg |
Commit
b0e89906f5b7e505a1ea315ab4ff612b1607fda8
by kyrtzidis[ASTReader] Allow controlling separately whether validation should be disabled for a PCH vs a module file
This addresses an issue with how the PCH preable works, specifically:
1. When using a PCH/preamble the module hash changes and a different cache directory is used 2. When the preamble is used, PCH & PCM validation is disabled.
Due to combination of #1 and #2, reparsing with preamble enabled can end up loading a stale module file before a header change and using it without updating it because validation is disabled and it doesn’t check that the header has changed and the module file is out-of-date.
rdar://72611253
Differential Revision: https://reviews.llvm.org/D95159
|
 | clang/lib/Frontend/PrecompiledPreamble.cpp |
 | clang/test/Index/Inputs/preamble-reparse-changed-module/head.h |
 | clang/test/Index/Inputs/preamble-reparse-changed-module/new-head.h |
 | clang/lib/Frontend/ASTUnit.cpp |
 | clang/lib/Frontend/FrontendAction.cpp |
 | clang/lib/Serialization/ASTReader.cpp |
 | clang/lib/Frontend/FrontendActions.cpp |
 | clang/lib/Frontend/ChainedIncludesSource.cpp |
 | clang/include/clang/Serialization/ASTReader.h |
 | clang/test/Index/Inputs/preamble-reparse-changed-module/module.modulemap |
 | clang/test/Index/preamble-reparse-changed-module.m |
 | clang/include/clang/Frontend/CompilerInstance.h |
 | clang/tools/c-index-test/c-index-test.c |
 | clang/include/clang/Driver/Options.td |
 | clang/tools/c-index-test/core_main.cpp |
 | clang/include/clang/Lex/PreprocessorOptions.h |
 | clang/lib/Frontend/CompilerInstance.cpp |
Commit
f9b5f6937ebed5dccabfc3c287f11d18b68a36f6
by Lang Hames[JITLink][ELF/x86-64] Range check 32-bit relocs.
Also switch to using little_<b> / ulittle_<b> types to write results for consistency with MachO.
|
 | llvm/lib/ExecutionEngine/JITLink/ELF_x86_64.cpp |
Commit
6699029b67bf0f5389896f9f929a344b64cfd9c7
by aeubanks[NewPM][opt] Run the "default" AA pipeline by default
We tend to assume that the AA pipeline is by default the default AA pipeline and it's confusing when it's empty instead.
PR48779
Initially reverted due to BasicAA running analyses in an unspecified order (multiple function calls as parameters), fixed by fetching analyses before the call to construct BasicAA.
Reviewed By: asbirlea
Differential Revision: https://reviews.llvm.org/D95117
|
 | llvm/test/Transforms/LoopVectorize/PowerPC/optimal-epilog-vectorization.ll |
 | llvm/test/Transforms/SimplifyCFG/X86/invalidate-dom.ll |
 | llvm/test/Other/new-pm-thinlto-defaults.ll |
 | llvm/lib/Analysis/BasicAliasAnalysis.cpp |
 | llvm/test/Analysis/MemorySSA/pr43569.ll |
 | llvm/test/Other/new-pm-thinlto-prelink-pgo-defaults.ll |
 | llvm/test/Other/loop-pm-invalidation.ll |
 | llvm/test/Transforms/PhaseOrdering/pr39282.ll |
 | llvm/test/Other/new-pm-thinlto-postlink-pgo-defaults.ll |
 | llvm/test/Transforms/ThinLTOBitcodeWriter/split-vfunc.ll |
 | llvm/test/Transforms/PhaseOrdering/X86/addsub-inseltpoison.ll |
 | llvm/test/Transforms/PhaseOrdering/X86/addsub.ll |
 | llvm/test/Transforms/LoopVersioningLICM/loopversioningLICM1.ll |
 | llvm/test/Transforms/PhaseOrdering/X86/loop-idiom-vs-indvars.ll |
 | llvm/test/Transforms/Inline/cgscc-incremental-invalidate.ll |
 | llvm/test/Transforms/PhaseOrdering/X86/masked-memory-ops.ll |
 | llvm/test/Transforms/PhaseOrdering/ARM/arm_fill_q7.ll |
 | llvm/test/Transforms/Coroutines/coro-retcon.ll |
 | llvm/test/Transforms/LoopVersioningLICM/loopversioningLICM2.ll |
 | llvm/test/Other/new-pm-defaults.ll |
 | llvm/test/Transforms/ThinLTOBitcodeWriter/pr33536.ll |
 | llvm/test/Other/pass-pipeline-parsing.ll |
 | llvm/test/Other/new-pm-thinlto-prelink-samplepgo-defaults.ll |
 | llvm/test/Other/new-pm-lto-defaults.ll |
 | llvm/test/Other/new-pm-pr42726-cgscc.ll |
 | llvm/test/Transforms/PhaseOrdering/instcombine-sroa-inttoptr.ll |
 | llvm/test/Transforms/OpenMP/parallel_region_merging.ll |
 | llvm/tools/opt/NewPMDriver.cpp |
 | llvm/test/Transforms/Coroutines/coro-elide-musttail.ll |
 | llvm/test/Transforms/PhaseOrdering/X86/vdiv.ll |
 | llvm/test/Transforms/PhaseOrdering/X86/SROA-after-loop-unrolling.ll |
 | llvm/test/Other/new-pass-manager.ll |
 | llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-mod.ll |
 | llvm/test/Transforms/PhaseOrdering/globalaa-retained.ll |
 | llvm/test/Other/new-pm-thinlto-postlink-samplepgo-defaults.ll |
 | llvm/test/Transforms/LoopVectorize/optimal-epilog-vectorization.ll |
 | llvm/test/Transforms/LoopRotate/pr35210.ll |
Commit
f374138058b6f7ddfeeb145a5c98b9c8d0d95f82
by aeubanks[test] Make incorrect-exit-count.ll work under NPM
|
 | llvm/test/Analysis/ScalarEvolution/incorrect-exit-count.ll |
Commit
16d4bbef30a9e625e04653047759d5636f9e58a5
by hanchung[mlir][Linalg] Introduce linalg.pad_tensor op.
`linalg.pad_tensor` is an operation that pads the `source` tensor with given `low` and `high` padding config.
Example 1:
```mlir %pad_value = ... : f32 %1 = linalg.pad_tensor %0 low[1, 2] high[2, 3] { ^bb0(%arg0 : index, %arg1 : index): linalg.yield %pad_value : f32 } : tensor<?x?xf32> to tensor<?x?xf32> ```
Example 2: ```mlir %pad_value = ... : f32 %1 = linalg.pad_tensor %arg0 low[2, %arg1, 3, 3] high[3, 3, %arg1, 2] { ^bb0(%arg2: index, %arg3: index, %arg4: index, %arg5: index): linalg.yield %pad_value : f32 } : tensor<1x2x2x?xf32> to tensor<6x?x?x?xf32> ```
Reviewed By: nicolasvasilache
Differential Revision: https://reviews.llvm.org/D93704
|
 | mlir/test/Dialect/Linalg/invalid.mlir |
 | mlir/include/mlir/Dialect/Linalg/IR/LinalgOps.td |
 | mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp |
 | mlir/test/Dialect/Linalg/roundtrip.mlir |
Commit
2cb130f7661176f2c2eaa7554f2a55863cfc0ed3
by hanchung[mlir][StandardToSPIRV] Add support for lowering uitofp to SPIR-V
- Extend spirv::ConstantOp::getZero/One to handle float, vector of int, and vector of float. - Refactor ZeroExtendI1Pattern to use getZero/One methods. - Add one more test for lowering std.zexti which extends vector<4xi1> to vector<4xi64>.
Reviewed By: antiagainst
Differential Revision: https://reviews.llvm.org/D95120
|
 | mlir/lib/Conversion/StandardToSPIRV/StandardToSPIRV.cpp |
 | mlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp |
 | mlir/test/Conversion/StandardToSPIRV/std-ops-to-spirv.mlir |